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2024-09-09 08:59:52 +00:00
parent f75098198c
commit 46ba6f09ec
1372 changed files with 1231198 additions and 1184 deletions
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wlan/8192es/DriverSrcPkg/Driver/HowToMake.txt
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How to build ?
1. Modify the "platform.mk" to select you platform or add an configuration for your platform.
2. Modify the "config.mk" to configure the driver option(select the chip, features, ...).
3. Overwirte "Makefile" by "Makefile_nrs" if your platform is not realtek system.
4. Run "make".
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/1x_kmsm_aes.c
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/* This is an independent implementation of the encryption algorithm: */
/* */
/* RIJNDAEL by Joan Daemen and Vincent Rijmen */
/* */
/* which is a candidate algorithm in the Advanced Encryption Standard */
/* programme of the US National Institute of Standards and Technology. */
/* */
/* Copyright in this implementation is held by Dr B R Gladman but I */
/* hereby give permission for its free direct or derivative use subject */
/* to acknowledgment of its origin and compliance with any conditions */
/* that the originators of the algorithm place on its exploitation. */
/* */
/* Dr Brian Gladman (gladman@seven77.demon.co.uk) 14th January 1999 */
#if 0
#include "stdafx.h"
#include <time.h>
#include <string.h>
#include <assert.h>
#endif
#ifdef __KERNEL__
#include <linux/time.h>
#include <linux/string.h>
#include <linux/slab.h>
#elif defined(__ECOS)
#include <cyg/hal/plf_intr.h>
#include <cyg/io/eth/rltk/819x/wrapper/sys_support.h>
#include <cyg/io/eth/rltk/819x/wrapper/skbuff.h>
#include <cyg/io/eth/rltk/819x/wrapper/timer.h>
#include <cyg/io/eth/rltk/819x/wrapper/wrapper.h>
#endif
#include "./8192cd_cfg.h"
#if defined(INCLUDE_WPA_PSK) || (defined(RTK_NL80211) && defined(CONFIG_IEEE80211W))
#ifdef RTL_WPA2
//#define MODULE_TEST
/*#include "aes_defs.h" */
#ifdef _SHOW_
#define _VERBOSE_ 1
#elif !defined(_VERBOSE_)
#define _VERBOSE_ 0
#endif
// david, move define to Makefile
// kenny
//#define BIG_ENDIAN 1
#if defined(__BORLANDC__) /* show what compiler we used */
#define COMPILER_ID "Borland"
//#define LITTLE_ENDIAN 1
// modified by chilong
#define AUTH_LITTLE_ENDIAN 1
#elif defined(_MSC_VER)
#define COMPILER_ID "Microsoft"
//#define LITTLE_ENDIAN 1
// modified by chilong
#define AUTH_LITTLE_ENDIAN 1
#elif defined(__GNUC__)
#define COMPILER_ID "GNU"
/* marked by chilong
#ifndef BIG_ENDIAN // assume gcc = little-endian, unless told otherwise
#define LITTLE_ENDIAN 1
#endif
*/
// modified by chilong
#ifndef _BIG_ENDIAN_ // assume gcc = little-endian, unless told otherwise
#define AUTH_LITTLE_ENDIAN 1
#endif
// modified by chilong
#else /* assume big endian, if compiler is unknown */
#define COMPILER_ID "Unknown"
#endif
/* 1. Standard types for AES cryptography source code */
typedef unsigned char u08b; /* an 8 bit unsigned character type */
typedef unsigned short u16b; /* a 16 bit unsigned integer type */
typedef unsigned int u32b; /* a 32 bit unsigned integer type */
#ifndef _RTL_WPA_WINDOW
#ifndef __LINUX_2_6__
#ifndef __ECOS
typedef int bool;
#endif
#endif
#endif
/* 2. Standard interface for AES cryptographic routines */
/* These are all based on 32-bit unsigned values and will therefore */
/* require endian conversions for big-endian architectures */
#ifdef __cplusplus
extern "C"
{
#endif
u32b * AES_SetKey (const u32b in_key[ ], const u32b key_len);
void AES_Encrypt(const u32b in_blk[4], u32b out_blk[4]);
void AES_Decrypt(const u32b in_blk[4], u32b out_blk[4]);
#ifdef __cplusplus
};
#endif
/* 3. Basic macros for speeding up generic operations */
/* Circular rotate of 32 bit values */
#ifdef _MSC_VER
#include <stdlib.h>
#pragma intrinsic(_lrotr,_lrotl)
#define rotr(x,n) _lrotr(x,n)
#define rotl(x,n) _lrotl(x,n)
#else
#define rotr(x,n) (((x) >> ((int)(n))) | ((x) << (32 - (int)(n))))
#define rotl(x,n) (((x) << ((int)(n))) | ((x) >> (32 - (int)(n))))
#endif
/* Extract byte from a 32 bit quantity (little endian notation) */
#define byte(x,n) ((u08b)((x) >> (8 * n)))
/* For inverting byte order in input/output 32 bit words, if needed */
// #ifdef LITTLE_ENDIAN
// modified by chilong
#ifdef AUTH_LITTLE_ENDIAN
#define bswap(x) (x)
#else
#define bswap(x) ((rotl((x), 8) & 0x00ff00ff) | (rotr((x), 8) & 0xff00ff00))
#endif
//end of aes_def.h
/*------------------ DLW debug code */
#if _VERBOSE_
#include <stdio.h>
int rNum;
void ShowBlk(const u32b *b,int final)
{
int i,j;
u32b x;
u08b a;
printf("%s %2d: ",(final) ? "Final" : "Round",rNum++);
for (i=0;i<4;i++)
{
printf(" ");
x = b[i]; /* always used internally as "little-endian" */
for (j=0;j<4;j++)
{
a = byte(x,j);
printf(" %02X",a);
}
}
printf("\n");
}
void ShowKeySched(const u32b *key,int cnt,const char *hdrMsg)
{
int i,j;
u32b x;
u08b a;
printf("%s\n",hdrMsg);
for (i=0;i<4*cnt;i++)
{
x = key[i]; /* key always used as "little-endian" */
printf(" ");
for (j=0;j<4;j++)
{
a = byte(x,j);
printf(" %02X",a);
}
if ((i%4) == 3) printf("\n");
}
}
#define SetR(r) { rNum = r; }
#else
#define ShowBlk(b,f)
#define SetR(r)
#define ShowKeySched(key,cnt,hdrMsg)
#endif
/*---------------- end of DLW debug */
#define LARGE_TABLES
u08b pow_tab[256];
u08b log_tab[256];
u08b sbx_tab[256];
u08b isb_tab[256];
u32b rco_tab[ 10];
u32b ft_tab[4][256];
u32b it_tab[4][256];
#ifdef LARGE_TABLES
u32b fl_tab[4][256];
u32b il_tab[4][256];
#endif
u32b tab_gen = 0;
u32b k_len;
u32b e_key[64];
u32b d_key[64];
#define ff_mult(a,b) (a && b ? pow_tab[(log_tab[a] + log_tab[b]) % 255] : 0)
#define f_rn(bo, bi, n, k) \
bo[n] = ft_tab[0][byte(bi[n],0)] ^ \
ft_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
ft_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
ft_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
#define i_rn(bo, bi, n, k) \
bo[n] = it_tab[0][byte(bi[n],0)] ^ \
it_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
it_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
it_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
#ifdef LARGE_TABLES
#define ls_box(x) \
( fl_tab[0][byte(x, 0)] ^ \
fl_tab[1][byte(x, 1)] ^ \
fl_tab[2][byte(x, 2)] ^ \
fl_tab[3][byte(x, 3)] )
#define f_rl(bo, bi, n, k) \
bo[n] = fl_tab[0][byte(bi[n],0)] ^ \
fl_tab[1][byte(bi[(n + 1) & 3],1)] ^ \
fl_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
fl_tab[3][byte(bi[(n + 3) & 3],3)] ^ *(k + n)
#define i_rl(bo, bi, n, k) \
bo[n] = il_tab[0][byte(bi[n],0)] ^ \
il_tab[1][byte(bi[(n + 3) & 3],1)] ^ \
il_tab[2][byte(bi[(n + 2) & 3],2)] ^ \
il_tab[3][byte(bi[(n + 1) & 3],3)] ^ *(k + n)
#else
#define ls_box(x) \
((u32b)sbx_tab[byte(x, 0)] << 0) ^ \
((u32b)sbx_tab[byte(x, 1)] << 8) ^ \
((u32b)sbx_tab[byte(x, 2)] << 16) ^ \
((u32b)sbx_tab[byte(x, 3)] << 24)
#define f_rl(bo, bi, n, k) \
bo[n] = (u32b)sbx_tab[byte(bi[n],0)] ^ \
rotl(((u32b)sbx_tab[byte(bi[(n + 1) & 3],1)]), 8) ^ \
rotl(((u32b)sbx_tab[byte(bi[(n + 2) & 3],2)]), 16) ^ \
rotl(((u32b)sbx_tab[byte(bi[(n + 3) & 3],3)]), 24) ^ *(k + n)
#define i_rl(bo, bi, n, k) \
bo[n] = (u32b)isb_tab[byte(bi[n],0)] ^ \
rotl(((u32b)isb_tab[byte(bi[(n + 3) & 3],1)]), 8) ^ \
rotl(((u32b)isb_tab[byte(bi[(n + 2) & 3],2)]), 16) ^ \
rotl(((u32b)isb_tab[byte(bi[(n + 1) & 3],3)]), 24) ^ *(k + n)
#endif
void gen_tabs(void)
{ u32b i, t;
u08b p, q;
/* log and power tables for GF(2**8) finite field with */
/* 0x11b as modular polynomial - the simplest prmitive */
/* root is 0x11, used here to generate the tables */
for(i = 0,p = 1; i < 256; ++i)
{
pow_tab[i] = (u08b)p; log_tab[p] = (u08b)i;
p = p ^ (p << 1) ^ (p & 0x80 ? 0x01b : 0);
}
log_tab[1] = 0; p = 1;
for(i = 0; i < 10; ++i)
{
rco_tab[i] = p;
p = (p << 1) ^ (p & 0x80 ? 0x1b : 0);
}
/* note that the affine byte transformation matrix in */
/* rijndael specification is in big endian format with */
/* bit 0 as the most significant bit. In the remainder */
/* of the specification the bits are numbered from the */
/* least significant end of a byte. */
for(i = 0; i < 256; ++i)
{
p = (i ? pow_tab[255 - log_tab[i]] : 0); q = p;
q = (q >> 7) | (q << 1); p ^= q;
q = (q >> 7) | (q << 1); p ^= q;
q = (q >> 7) | (q << 1); p ^= q;
q = (q >> 7) | (q << 1); p ^= q ^ 0x63;
sbx_tab[i] = (u08b)p; isb_tab[p] = (u08b)i;
}
for(i = 0; i < 256; ++i)
{
p = sbx_tab[i];
#ifdef LARGE_TABLES
t = p; fl_tab[0][i] = t;
fl_tab[1][i] = rotl(t, 8);
fl_tab[2][i] = rotl(t, 16);
fl_tab[3][i] = rotl(t, 24);
#endif
t = ((u32b)ff_mult(2, p)) |
((u32b)p << 8) |
((u32b)p << 16) |
((u32b)ff_mult(3, p) << 24);
ft_tab[0][i] = t;
ft_tab[1][i] = rotl(t, 8);
ft_tab[2][i] = rotl(t, 16);
ft_tab[3][i] = rotl(t, 24);
p = isb_tab[i];
#ifdef LARGE_TABLES
t = p; il_tab[0][i] = t;
il_tab[1][i] = rotl(t, 8);
il_tab[2][i] = rotl(t, 16);
il_tab[3][i] = rotl(t, 24);
#endif
t = ((u32b)ff_mult(14, p)) |
((u32b)ff_mult( 9, p) << 8) |
((u32b)ff_mult(13, p) << 16) |
((u32b)ff_mult(11, p) << 24);
it_tab[0][i] = t;
it_tab[1][i] = rotl(t, 8);
it_tab[2][i] = rotl(t, 16);
it_tab[3][i] = rotl(t, 24);
#if _VERBOSE_
if (i<4) /* helpful for debugging on new platform */
{ /* (compare with results from known platform) */
if (i==0)
printf("%8s : %08X %08X %08X %08X\n","rco_tab",
rco_tab[0],rco_tab[1],rco_tab[2],rco_tab[3]);
#define _ShowTab(tName) printf("%8s[%d]: %08X %08X %08X %08X\n",#tName,i, \
tName[0][i],tName[1][i],tName[2][i],tName[3][i]);
_ShowTab(it_tab);
_ShowTab(ft_tab);
#ifdef LARGE_TABLES
_ShowTab(il_tab);
_ShowTab(fl_tab);
#endif
}
#endif
}
tab_gen = 1;
};
#define star_x(x) (((x) & 0x7f7f7f7f) << 1) ^ ((((x) & 0x80808080) >> 7) * 0x1b)
#define imix_col(y,x) \
u = star_x(x); \
v = star_x(u); \
w = star_x(v); \
t = w ^ (x); \
(y) = u ^ v ^ w; \
(y) ^= rotr(u ^ t, 8) ^ \
rotr(v ^ t, 16) ^ \
rotr(t,24)
/* initialise the key schedule from the user supplied key */
#define loop4(i) \
{ t = ls_box(rotr(t, 8)) ^ rco_tab[i]; \
t ^= e_key[4 * i]; e_key[4 * i + 4] = t; \
t ^= e_key[4 * i + 1]; e_key[4 * i + 5] = t; \
t ^= e_key[4 * i + 2]; e_key[4 * i + 6] = t; \
t ^= e_key[4 * i + 3]; e_key[4 * i + 7] = t; \
}
#define loop6(i) \
{ t = ls_box(rotr(t, 8)) ^ rco_tab[i]; \
t ^= e_key[6 * i]; e_key[6 * i + 6] = t; \
t ^= e_key[6 * i + 1]; e_key[6 * i + 7] = t; \
t ^= e_key[6 * i + 2]; e_key[6 * i + 8] = t; \
t ^= e_key[6 * i + 3]; e_key[6 * i + 9] = t; \
t ^= e_key[6 * i + 4]; e_key[6 * i + 10] = t; \
t ^= e_key[6 * i + 5]; e_key[6 * i + 11] = t; \
}
#define loop8(i) \
{ t = ls_box(rotr(t, 8)) ^ rco_tab[i]; \
t ^= e_key[8 * i]; e_key[8 * i + 8] = t; \
t ^= e_key[8 * i + 1]; e_key[8 * i + 9] = t; \
t ^= e_key[8 * i + 2]; e_key[8 * i + 10] = t; \
t ^= e_key[8 * i + 3]; e_key[8 * i + 11] = t; \
t = e_key[8 * i + 4] ^ ls_box(t); \
e_key[8 * i + 12] = t; \
t ^= e_key[8 * i + 5]; e_key[8 * i + 13] = t; \
t ^= e_key[8 * i + 6]; e_key[8 * i + 14] = t; \
t ^= e_key[8 * i + 7]; e_key[8 * i + 15] = t; \
}
u32b *AES_SetKey(const u32b in_key[], const u32b key_len)
{ u32b i, t, u, v, w;
if(!tab_gen)
gen_tabs();
k_len = (key_len + 31) / 32;
for (i=0;i<k_len;i++)
e_key[i] = bswap(in_key[i]);
t = e_key[k_len-1];
switch(k_len)
{
case 4: for(i = 0; i < 10; ++i)
loop4(i);
break;
case 6: for(i = 0; i < 8; ++i)
loop6(i);
break;
case 8: for(i = 0; i < 7; ++i)
loop8(i);
break;
}
d_key[0] = e_key[0]; d_key[1] = e_key[1];
d_key[2] = e_key[2]; d_key[3] = e_key[3];
for(i = 4; i < 4 * k_len + 24; ++i)
{
imix_col(d_key[i], e_key[i]);
}
ShowKeySched(e_key,4,"Encryption key schedule:");
ShowKeySched(d_key,4,"Decryption key schedule:");
return e_key;
};
/* encrypt a block of text */
#define f_nround(bo, bi, k) \
f_rn(bo, bi, 0, k); \
f_rn(bo, bi, 1, k); \
f_rn(bo, bi, 2, k); \
f_rn(bo, bi, 3, k); \
ShowBlk(bo,0); \
k += 4
#define f_lround(bo, bi, k) \
f_rl(bo, bi, 0, k); \
f_rl(bo, bi, 1, k); \
f_rl(bo, bi, 2, k); \
f_rl(bo, bi, 3, k); \
ShowBlk(bo,1);
void AES_Encrypt(const u32b in_blk[4], u32b out_blk[4])
{ u32b b0[4], b1[4], *kp;
b0[0] = bswap(in_blk[0]) ^ e_key[0];
b0[1] = bswap(in_blk[1]) ^ e_key[1];
b0[2] = bswap(in_blk[2]) ^ e_key[2];
b0[3] = bswap(in_blk[3]) ^ e_key[3];
SetR(1); ShowBlk(b0,0);
kp = e_key + 4;
if(k_len > 6)
{
f_nround(b1, b0, kp); f_nround(b0, b1, kp);
}
if(k_len > 4)
{
f_nround(b1, b0, kp); f_nround(b0, b1, kp);
}
f_nround(b1, b0, kp); f_nround(b0, b1, kp);
f_nround(b1, b0, kp); f_nround(b0, b1, kp);
f_nround(b1, b0, kp); f_nround(b0, b1, kp);
f_nround(b1, b0, kp); f_nround(b0, b1, kp);
f_nround(b1, b0, kp); f_lround(b0, b1, kp);
out_blk[0] = bswap(b0[0]);
out_blk[1] = bswap(b0[1]);
out_blk[2] = bswap(b0[2]);
out_blk[3] = bswap(b0[3]);
};
/* decrypt a block of text */
#define i_nround(bo, bi, k) \
i_rn(bo, bi, 0, k); \
i_rn(bo, bi, 1, k); \
i_rn(bo, bi, 2, k); \
i_rn(bo, bi, 3, k); \
k -= 4
#define i_lround(bo, bi, k) \
i_rl(bo, bi, 0, k); \
i_rl(bo, bi, 1, k); \
i_rl(bo, bi, 2, k); \
i_rl(bo, bi, 3, k)
void AES_Decrypt(const u32b in_blk[4], u32b out_blk[4])
{ u32b b0[4], b1[4], *kp;
b0[0] = bswap(in_blk[0]) ^ e_key[4 * k_len + 24];
b0[1] = bswap(in_blk[1]) ^ e_key[4 * k_len + 25];
b0[2] = bswap(in_blk[2]) ^ e_key[4 * k_len + 26];
b0[3] = bswap(in_blk[3]) ^ e_key[4 * k_len + 27];
kp = d_key + 4 * (k_len + 5);
if(k_len > 6)
{
i_nround(b1, b0, kp); i_nround(b0, b1, kp);
}
if(k_len > 4)
{
i_nround(b1, b0, kp); i_nround(b0, b1, kp);
}
i_nround(b1, b0, kp); i_nround(b0, b1, kp);
i_nround(b1, b0, kp); i_nround(b0, b1, kp);
i_nround(b1, b0, kp); i_nround(b0, b1, kp);
i_nround(b1, b0, kp); i_nround(b0, b1, kp);
i_nround(b1, b0, kp); i_lround(b0, b1, kp);
out_blk[0] = bswap(b0[0]);
out_blk[1] = bswap(b0[1]);
out_blk[2] = bswap(b0[2]);
out_blk[3] = bswap(b0[3]);
};
enum
{
BLK_SIZE = 16, // # octets in an AES block
MAX_PACKET = 3*512, // largest packet size
N_RESERVED = 0, // reserved nonce octet value
A_DATA = 0x40, // the Adata bit in the flags
M_SHIFT = 3, // how much to shift the 3-bit M field
L_SHIFT = 0, // how much to shift the 3-bit L field
L_SIZE = 2 // size of the l(m) length field (in octets)
};
typedef union _block // AES cipher block
{
u32b x[BLK_SIZE/4]; // access as 8-bit octets or 32-bit words
u08b b[BLK_SIZE];
}block;
typedef struct _packet
{
BOOLEAN encrypted; // TRUE if encrypted
u08b TA[6]; // xmit address
int micLength; // # octets of MIC appended to plaintext (M)
int clrCount; // # cleartext octets covered by MIC
u32b pktNum[2]; // unique packet sequence number (like WEP IV)
block key; // the encryption key (K)
int length; // # octets in data[]
u08b data[MAX_PACKET+2*BLK_SIZE]; // packet contents
}packet;
/*
input : 256 bits, 32 bytes, 4 block for TKIP
128 bits, 16 bytes, 2 block for CCMP, WRAP, and WEP
up to 32 block for WPA2
output: 8 bytes MIC | Wraped key data
*/
#define BLOCKSIZE8 8
void AES_WRAP(u08b * plain, int plain_len,
u08b * iv, int iv_len,
u08b * kek, int kek_len,
u08b *cipher, u16b *cipher_len)
{
int i, j, k, nblock = plain_len/BLOCKSIZE8;
#ifdef RTL_WPA2
static u08b R[32][BLOCKSIZE8], A[BLOCKSIZE8], xor[BLOCKSIZE8];
#else
u08b R[4][BLOCKSIZE8], A[BLOCKSIZE8], xor[BLOCKSIZE8];
#endif
static packet p;
static block m,x;
memcpy(&p.key.b , kek, kek_len);
AES_SetKey(p.key.x, BLK_SIZE*8); // run the key schedule
//Initialize Variable
memcpy(A, iv, BLOCKSIZE8);
for(i = 0; i < nblock ; i++)
memcpy(&R[i], plain + i*BLOCKSIZE8, BLOCKSIZE8);
//Caalculate Intermediate Values
for(j = 0 ; j < 6 ; j++ )
for (i = 0 ; i < nblock ; i++)
{
memcpy(&m.b, A, BLOCKSIZE8);
memcpy((&m.b[0]) + BLOCKSIZE8, &(R[i]), BLOCKSIZE8);
// => B = AES(K, A|R[i])
AES_Encrypt(m.x,x.x);
// => A = MSB(64,B) ^t where t = (n*j) + i
memset(xor, 0, sizeof xor);
xor[7] |= ((nblock * j) + i + 1);
for(k = 0 ; k < 8 ; k++)
A[k] = x.b[k] ^ xor[k];
// => R[i] = LSB(64,B)
for(k = 0 ; k < 8 ; k++)
R[i][k] = x.b[k + BLOCKSIZE8];
}
//Output the result
memcpy(cipher, A, BLOCKSIZE8);
for(i = 0; i<nblock ; i++)
memcpy(cipher + (i+1)*BLOCKSIZE8, &R[i], BLOCKSIZE8);
*cipher_len = plain_len + BLOCKSIZE8;
}
void AES_UnWRAP(u08b * cipher, int cipher_len,
u08b * kek, int kek_len,
u08b * plain, int plain_len)
{
int i, j, k, nblock = (cipher_len/BLOCKSIZE8) - 1;
#ifdef RTL_WPA2
if (nblock > 32) {
printk("AES_UnWRAP Error: cipher len exceeds!\n");
return;
}
u08b R[32][BLOCKSIZE8], A[BLOCKSIZE8], xor[BLOCKSIZE8];
#else
if (nblock > 4) {
printk("AES_UnWRAP Error: cipher len exceeds!\n");
return;
}
u08b R[4][BLOCKSIZE8], A[BLOCKSIZE8], xor[BLOCKSIZE8];
#endif
packet *p;
block m,x;
if ((plain_len < BLOCKSIZE8) || (plain_len < cipher_len)) {
printk("AES_UnWRAP Error: cipher len exceeds plain len!\n");
return;
}
p = (packet *)kmalloc(sizeof(packet), GFP_ATOMIC);
if (p == NULL)
return;
memcpy(p->key.b , kek, kek_len);
AES_SetKey(p->key.x, BLK_SIZE*8); // run the key schedule
//Initialize Variable
memcpy(A, cipher, BLOCKSIZE8);
for(i = 0; i < nblock ; i++)
memcpy(&R[i], cipher + (i+1)*BLOCKSIZE8, BLOCKSIZE8);
//Compute internediate Value
for(j=5 ; j>=0 ; j--)
for(i= nblock-1 ; i>=0 ; i--)
{
// => B = AES-1((A^t) |R[i])
memset(xor, 0, sizeof xor);
xor[7] |= ((nblock * j) + i + 1);
for(k = 0 ; k < 8 ; k++)
x.b[k] = A[k] ^ xor[k];
memcpy((&x.b[0]) + BLOCKSIZE8, &(R[i]), BLOCKSIZE8);
AES_Decrypt(x.x,m.x);
memcpy(A, &m.b[0], BLOCKSIZE8);
//for(k=0 ; k<BLOCKSIZE8 ; k++)
// A[k] = m.b[k];
for(k=0 ; k<BLOCKSIZE8 ; k++)
R[i][k] = m.b[k + BLOCKSIZE8];
}
memcpy(plain, A, BLOCKSIZE8);
for(i = 0; i < nblock ; i++)
memcpy(plain + (i+1)*BLOCKSIZE8, &R[i], BLOCKSIZE8);
kfree(p);
}
#ifdef MODULE_TEST
void TestAESWRAP()
{
unsigned char kek[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
unsigned char plaintext[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
unsigned char cipher[16+ 8];
/*
unsigned char iv[] = {0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6};
unsigned char plaintext1[] ={0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F};
AES_WRAP(plaintext, 16,
iv, 8,
kek, 16,
cipher);
*/
AES_UnWRAP(cipher, 24,
kek, 16,
plaintext, 24);
}
#endif
#endif // RTL_WPA2
#endif // INCLUDE_WPA_PSK
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/1x_kmsm_hmac.c
Executable
+1568
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File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/1x_md5c.c
Executable
+418
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@@ -0,0 +1,418 @@
/* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
rights reserved.
License to copy and use this software is granted provided that it
is identified as the "RSA Data Security, Inc. MD5 Message-Digest
Algorithm" in all material mentioning or referencing this software
or this function.
License is also granted to make and use derivative works provided
that such works are identified as "derived from the RSA Data
Security, Inc. MD5 Message-Digest Algorithm" in all material
mentioning or referencing the derived work.
RSA Data Security, Inc. makes no representations concerning either
the merchantability of this software or the suitability of this
software for any particular purpose. It is provided "as is"
without express or implied warranty of any kind.
These notices must be retained in any copies of any part of this
documentation and/or software.
*/
//#include "8021x.h"
#include "./8192cd_cfg.h"
#if defined(INCLUDE_WPA_PSK) || defined(WIFI_HAPD) || defined(RTK_NL80211)
#include "1x_md5c.h"
#define S11 7
#define S12 12
#define S13 17
#define S14 22
#define S21 5
#define S22 9
#define S23 14
#define S24 20
#define S31 4
#define S32 11
#define S33 16
#define S34 23
#define S41 6
#define S42 10
#define S43 15
#define S44 21
static void MD5Transform(UINT4 [4], UINT8 [64]);
static void Encode(UINT8 *, UINT4 *, UINT32);
static void Decode(UINT4 *, UINT8 *, UINT32);
static void MD5_memcpy(POINTER, POINTER, UINT32);
static void MD5_memset(POINTER, int, UINT32);
static UINT8 PADDING[64] = {
0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
/* F, G, H and I are basic MD5 functions.
*/
#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
#define H(x, y, z) ((x) ^ (y) ^ (z))
#define I(x, y, z) ((y) ^ ((x) | (~z)))
/* ROTATE_LEFT rotates x left n bits.
*/
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32-(n))))
/* FF, GG, HH, and II transformations for rounds 1, 2, 3, and 4.
Rotation is separate from addition to prevent recomputation.
*/
#define FF(a, b, c, d, x, s, ac) { \
(a) += F ((b), (c), (d)) + (x) + (UINT4)(ac); \
(a) = ROTATE_LEFT ((a), (s)); \
(a) += (b); \
}
#define GG(a, b, c, d, x, s, ac) { \
(a) += G ((b), (c), (d)) + (x) + (UINT4)(ac); \
(a) = ROTATE_LEFT ((a), (s)); \
(a) += (b); \
}
#define HH(a, b, c, d, x, s, ac) { \
(a) += H ((b), (c), (d)) + (x) + (UINT4)(ac); \
(a) = ROTATE_LEFT ((a), (s)); \
(a) += (b); \
}
#define II(a, b, c, d, x, s, ac) { \
(a) += I ((b), (c), (d)) + (x) + (UINT4)(ac); \
(a) = ROTATE_LEFT ((a), (s)); \
(a) += (b); \
}
/* MD5 initialization. Begins an MD5 operation, writing a new context.
*/
void wlan_MD5_Init (context)
MD5_CTX *context; /* context */
{
context->count[0] = context->count[1] = 0;
/* Load magic initialization constants.
*/
context->state[0] = 0x67452301;
context->state[1] = 0xefcdab89;
context->state[2] = 0x98badcfe;
context->state[3] = 0x10325476;
}
/* MD5 block update operation. Continues an MD5 message-digest
operation, processing another message block, and updating the
context.
*/
void wlan_MD5_Update (context, input, inputLen)
MD5_CTX *context; /* context */
UINT8 *input; /* input block */
UINT32 inputLen; /* length of input block */
{
UINT32 i, index, partLen;
/* Compute number of bytes mod 64 */
index = (UINT32)((context->count[0] >> 3) & 0x3F);
/* Update number of bits */
if ((context->count[0] += ((UINT4)inputLen << 3))
< ((UINT4)inputLen << 3))
context->count[1]++;
context->count[1] += ((UINT4)inputLen >> 29);
partLen = 64 - index;
/* Transform as many times as possible.
*/
if (inputLen >= partLen) {
MD5_memcpy
((POINTER)&context->buffer[index], (POINTER)input, partLen);
MD5Transform (context->state, context->buffer);
for (i = partLen; i + 63 < inputLen; i += 64)
MD5Transform (context->state, &input[i]);
index = 0;
}
else
i = 0;
/* Buffer remaining input */
MD5_memcpy
((POINTER)&context->buffer[index], (POINTER)&input[i],
inputLen-i);
}
/* MD5 finalization. Ends an MD5 message-digest operation, writing the
the message digest and zeroizing the context.
*/
void wlan_MD5_Final (digest, context)
UINT8 digest[16]; /* message digest */
MD5_CTX *context; /* context */
{
UINT8 bits[8];
UINT32 index, padLen;
/* Save number of bits */
Encode (bits, context->count, 8);
/* Pad out to 56 mod 64.
*/
index = (UINT32)((context->count[0] >> 3) & 0x3f);
padLen = (index < 56) ? (56 - index) : (120 - index);
wlan_MD5_Update (context, PADDING, padLen);
/* Append length (before padding) */
wlan_MD5_Update (context, bits, 8);
/* Store state in digest */
Encode (digest, context->state, 16);
/* Zeroize sensitive information.
*/
MD5_memset ((POINTER)context, 0, sizeof (*context));
}
/* MD5 basic transformation. Transforms state based on block.
*/
static void MD5Transform (state, block)
UINT4 state[4];
UINT8 block[64];
{
UINT4 a = state[0], b = state[1], c = state[2], d = state[3], x[16];
Decode (x, block, 64);
/* Round 1 */
FF (a, b, c, d, x[ 0], S11, 0xd76aa478); /* 1 */
FF (d, a, b, c, x[ 1], S12, 0xe8c7b756); /* 2 */
FF (c, d, a, b, x[ 2], S13, 0x242070db); /* 3 */
FF (b, c, d, a, x[ 3], S14, 0xc1bdceee); /* 4 */
FF (a, b, c, d, x[ 4], S11, 0xf57c0faf); /* 5 */
FF (d, a, b, c, x[ 5], S12, 0x4787c62a); /* 6 */
FF (c, d, a, b, x[ 6], S13, 0xa8304613); /* 7 */
FF (b, c, d, a, x[ 7], S14, 0xfd469501); /* 8 */
FF (a, b, c, d, x[ 8], S11, 0x698098d8); /* 9 */
FF (d, a, b, c, x[ 9], S12, 0x8b44f7af); /* 10 */
FF (c, d, a, b, x[10], S13, 0xffff5bb1); /* 11 */
FF (b, c, d, a, x[11], S14, 0x895cd7be); /* 12 */
FF (a, b, c, d, x[12], S11, 0x6b901122); /* 13 */
FF (d, a, b, c, x[13], S12, 0xfd987193); /* 14 */
FF (c, d, a, b, x[14], S13, 0xa679438e); /* 15 */
FF (b, c, d, a, x[15], S14, 0x49b40821); /* 16 */
/* Round 2 */
GG (a, b, c, d, x[ 1], S21, 0xf61e2562); /* 17 */
GG (d, a, b, c, x[ 6], S22, 0xc040b340); /* 18 */
GG (c, d, a, b, x[11], S23, 0x265e5a51); /* 19 */
GG (b, c, d, a, x[ 0], S24, 0xe9b6c7aa); /* 20 */
GG (a, b, c, d, x[ 5], S21, 0xd62f105d); /* 21 */
GG (d, a, b, c, x[10], S22, 0x2441453); /* 22 */
GG (c, d, a, b, x[15], S23, 0xd8a1e681); /* 23 */
GG (b, c, d, a, x[ 4], S24, 0xe7d3fbc8); /* 24 */
GG (a, b, c, d, x[ 9], S21, 0x21e1cde6); /* 25 */
GG (d, a, b, c, x[14], S22, 0xc33707d6); /* 26 */
GG (c, d, a, b, x[ 3], S23, 0xf4d50d87); /* 27 */
GG (b, c, d, a, x[ 8], S24, 0x455a14ed); /* 28 */
GG (a, b, c, d, x[13], S21, 0xa9e3e905); /* 29 */
GG (d, a, b, c, x[ 2], S22, 0xfcefa3f8); /* 30 */
GG (c, d, a, b, x[ 7], S23, 0x676f02d9); /* 31 */
GG (b, c, d, a, x[12], S24, 0x8d2a4c8a); /* 32 */
/* Round 3 */
HH (a, b, c, d, x[ 5], S31, 0xfffa3942); /* 33 */
HH (d, a, b, c, x[ 8], S32, 0x8771f681); /* 34 */
HH (c, d, a, b, x[11], S33, 0x6d9d6122); /* 35 */
HH (b, c, d, a, x[14], S34, 0xfde5380c); /* 36 */
HH (a, b, c, d, x[ 1], S31, 0xa4beea44); /* 37 */
HH (d, a, b, c, x[ 4], S32, 0x4bdecfa9); /* 38 */
HH (c, d, a, b, x[ 7], S33, 0xf6bb4b60); /* 39 */
HH (b, c, d, a, x[10], S34, 0xbebfbc70); /* 40 */
HH (a, b, c, d, x[13], S31, 0x289b7ec6); /* 41 */
HH (d, a, b, c, x[ 0], S32, 0xeaa127fa); /* 42 */
HH (c, d, a, b, x[ 3], S33, 0xd4ef3085); /* 43 */
HH (b, c, d, a, x[ 6], S34, 0x4881d05); /* 44 */
HH (a, b, c, d, x[ 9], S31, 0xd9d4d039); /* 45 */
HH (d, a, b, c, x[12], S32, 0xe6db99e5); /* 46 */
HH (c, d, a, b, x[15], S33, 0x1fa27cf8); /* 47 */
HH (b, c, d, a, x[ 2], S34, 0xc4ac5665); /* 48 */
/* Round 4 */
II (a, b, c, d, x[ 0], S41, 0xf4292244); /* 49 */
II (d, a, b, c, x[ 7], S42, 0x432aff97); /* 50 */
II (c, d, a, b, x[14], S43, 0xab9423a7); /* 51 */
II (b, c, d, a, x[ 5], S44, 0xfc93a039); /* 52 */
II (a, b, c, d, x[12], S41, 0x655b59c3); /* 53 */
II (d, a, b, c, x[ 3], S42, 0x8f0ccc92); /* 54 */
II (c, d, a, b, x[10], S43, 0xffeff47d); /* 55 */
II (b, c, d, a, x[ 1], S44, 0x85845dd1); /* 56 */
II (a, b, c, d, x[ 8], S41, 0x6fa87e4f); /* 57 */
II (d, a, b, c, x[15], S42, 0xfe2ce6e0); /* 58 */
II (c, d, a, b, x[ 6], S43, 0xa3014314); /* 59 */
II (b, c, d, a, x[13], S44, 0x4e0811a1); /* 60 */
II (a, b, c, d, x[ 4], S41, 0xf7537e82); /* 61 */
II (d, a, b, c, x[11], S42, 0xbd3af235); /* 62 */
II (c, d, a, b, x[ 2], S43, 0x2ad7d2bb); /* 63 */
II (b, c, d, a, x[ 9], S44, 0xeb86d391); /* 64 */
state[0] += a;
state[1] += b;
state[2] += c;
state[3] += d;
/* Zeroize sensitive information.
*/
MD5_memset ((POINTER)x, 0, sizeof (x));
}
/* Encodes input (UINT4) into output (UINT8). Assumes len is
a multiple of 4.
*/
static void Encode (output, input, len)
UINT8 *output;
UINT4 *input;
UINT32 len;
{
UINT32 i, j;
for (i = 0, j = 0; j < len; i++, j += 4) {
output[j] = (UINT8)(input[i] & 0xff);
output[j+1] = (UINT8)((input[i] >> 8) & 0xff);
output[j+2] = (UINT8)((input[i] >> 16) & 0xff);
output[j+3] = (UINT8)((input[i] >> 24) & 0xff);
}
}
/* Decodes input (UINT8) into output (UINT4). Assumes len is
a multiple of 4.
*/
static void Decode (output, input, len)
UINT4 *output;
UINT8 *input;
UINT32 len;
{
UINT32 i, j;
for (i = 0, j = 0; j < len; i++, j += 4)
output[i] = ((UINT4)input[j]) | (((UINT4)input[j+1]) << 8) |
(((UINT4)input[j+2]) << 16) | (((UINT4)input[j+3]) << 24);
}
/* Note: Replace "for loop" with standard memcpy if possible.
*/
static void MD5_memcpy (output, input, len)
POINTER output;
POINTER input;
UINT32 len;
{
UINT32 i;
for (i = 0; i < len; i++)
output[i] = input[i];
}
/* Note: Replace "for loop" with standard memset if possible.
*/
static void MD5_memset (output, value, len)
POINTER output;
int value;
UINT32 len;
{
UINT32 i;
for (i = 0; i < len; i++)
((char *)output)[i] = (char)value;
}
#if 0
/*
UINT8* text; pointer to data stream
int text_len; length of data stream
UINT8* key; pointer to authentication key
int key_len; length of authentication key
UINT8* digest; caller digest to be filled in
*/
void hmac_md5(UINT8 *text, INT32 text_len, UINT8 *key, INT32 key_len,UINT8 *digest)
{
MD5_CTX context;
UINT8 k_ipad[65]; /* inner padding -
* key XORd with ipad
*/
UINT8 k_opad[65]; /* outer padding -
* key XORd with opad
*/
UINT8 tk[16];
int i;
/* if key is longer than 64 bytes reset it to key=MD5(key) */
if (key_len > 64) {
MD5_CTX tctx;
MD5Init(&tctx);
MD5Update(&tctx, key, key_len);
MD5Final(tk, &tctx);
key = tk;
key_len = 16;
}
/*
* the HMAC_MD5 transform looks like:
*
* MD5(K XOR opad, MD5(K XOR ipad, text))
*
* where K is an n byte key
* ipad is the byte 0x36 repeated 64 times
* opad is the byte 0x5c repeated 64 times
* and text is the data being protected
*/
/* start out by storing key in pads */
memset(k_ipad, 0x0, sizeof(k_ipad));
memset(k_opad, 0x0, sizeof(k_opad));
memcpy(k_ipad, key, key_len);
memcpy(k_opad, key, key_len);
//bzero( k_ipad, sizeof k_ipad);
//bzero( k_opad, sizeof k_opad);
//bcopy( key, k_ipad, key_len);
//bcopy( key, k_opad, key_len);
/* XOR key with ipad and opad values */
for (i=0; i<64; i++) {
k_ipad[i] ^= 0x36;
k_opad[i] ^= 0x5c;
}
/*
* perform inner MD5
*/
MD5Init(&context); /* init context for 1st
* pass */
MD5Update(&context, k_ipad, 64); /* start with inner pad */
MD5Update(&context, text, text_len); /* then text of datagram */
MD5Final(digest, &context); /* finish up 1st pass */
/*
* perform outer MD5
*/
MD5Init(&context); /* init context for 2nd
* pass */
MD5Update(&context, k_opad, 64); /* start with outer pad */
MD5Update(&context, digest, 16); /* then results of 1st
* hash */
MD5Final(digest, &context); /* finish up 2nd pass */
}
#endif
#endif // INCLUDE_WPA_PSK
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/1x_md5c.h
Executable
+63
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@@ -0,0 +1,63 @@
/*
* 8021x_md5c.h - header file for MD5C.C
*/
#ifndef P8021X_MD5C_H
#define P8021X_MD5C_H
/* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
rights reserved.
License to copy and use this software is granted provided that it
is identified as the "RSA Data Security, Inc. MD5 Message-Digest
Algorithm" in all material mentioning or referencing this software
or this function.
License is also granted to make and use derivative works provided
that such works are identified as "derived from the RSA Data
Security, Inc. MD5 Message-Digest Algorithm" in all material
mentioning or referencing the derived work.
RSA Data Security, Inc. makes no representations concerning either
the merchantability of this software or the suitability of this
software for any particular purpose. It is provided "as is"
without express or implied warranty of any kind.
These notices must be retained in any copies of any part of this
documentation and/or software.
*/
/* MD5_TYPE.H - RSAREF types and constants */
/* POINTER defines a generic pointer type */
typedef unsigned char *POINTER;
/* UINT2 defines a two byte word */
typedef unsigned short int UINT2;
/* UINT4 defines a four byte word */
typedef unsigned int UINT4;
#if 0
typedef unsigned char UINT8;
typedef unsigned long UINT32;
typedef int INT32;
#endif
/* MD5 context. */
typedef struct {
UINT4 state[4]; /* state (ABCD) */
UINT4 count[2]; /* number of bits, modulo 2^64 (lsb first) */
unsigned char buffer[64]; /* input buffer */
} MD5_CTX;
void wlan_MD5_Init(MD5_CTX *);
void wlan_MD5_Update(MD5_CTX *, UINT8 *, UINT32);
void wlan_MD5_Final(unsigned char [16], MD5_CTX *);
//void hmac_md5(UINT8 *, INT32, UINT8 * , INT32, UINT8 * );
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/1x_rc4.c
Executable
+371
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/* crypto/rc4/rc4_enc.c */
/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
* All rights reserved.
*
* This package is an SSL implementation written
* by Eric Young (eay@cryptsoft.com).
* The implementation was written so as to conform with Netscapes SSL.
*
* This library is free for commercial and non-commercial use as long as
* the following conditions are aheared to. The following conditions
* apply to all code found in this distribution, be it the RC4, RSA,
* lhash, DES, etc., code; not just the SSL code. The SSL documentation
* included with this distribution is covered by the same copyright terms
* except that the holder is Tim Hudson (tjh@cryptsoft.com).
*
* Copyright remains Eric Young's, and as such any Copyright notices in
* the code are not to be removed.
* If this package is used in a product, Eric Young should be given attribution
* as the author of the parts of the library used.
* This can be in the form of a textual message at program startup or
* in documentation (online or textual) provided with the package.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* "This product includes cryptographic software written by
* Eric Young (eay@cryptsoft.com)"
* The word 'cryptographic' can be left out if the rouines from the library
* being used are not cryptographic related :-).
* 4. If you include any Windows specific code (or a derivative thereof) from
* the apps directory (application code) you must include an acknowledgement:
* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
*
* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The licence and distribution terms for any publically available version or
* derivative of this code cannot be changed. i.e. this code cannot simply be
* copied and put under another distribution licence
* [including the GNU Public Licence.]
*/
#include "./8192cd_cfg.h"
#ifdef INCLUDE_WPA_PSK
#include "1x_rc4.h"
/* RC4 as implemented from a posting from
* Newsgroups: sci.crypt
* From: sterndark@netcom.com (David Sterndark)
* Subject: RC4 Algorithm revealed.
* Message-ID: <sternCvKL4B.Hyy@netcom.com>
* Date: Wed, 14 Sep 1994 06:35:31 GMT
*/
void RC4(RC4_KEY *key, unsigned long len, const unsigned char *indata,
unsigned char *outdata)
{
register RC4_INT *d;
register RC4_INT x,y,tx,ty;
int i;
x=key->x;
y=key->y;
d=key->data;
#if defined(RC4_CHUNK)
/*
* The original reason for implementing this(*) was the fact that
* pre-21164a Alpha CPUs don't have byte load/store instructions
* and e.g. a byte store has to be done with 64-bit load, shift,
* and, or and finally 64-bit store. Peaking data and operating
* at natural word size made it possible to reduce amount of
* instructions as well as to perform early read-ahead without
* suffering from RAW (read-after-write) hazard. This resulted
* in ~40%(**) performance improvement on 21064 box with gcc.
* But it's not only Alpha users who win here:-) Thanks to the
* early-n-wide read-ahead this implementation also exhibits
* >40% speed-up on SPARC and 20-30% on 64-bit MIPS (depending
* on sizeof(RC4_INT)).
*
* (*) "this" means code which recognizes the case when input
* and output pointers appear to be aligned at natural CPU
* word boundary
* (**) i.e. according to 'apps/openssl speed rc4' benchmark,
* crypto/rc4/rc4speed.c exhibits almost 70% speed-up...
*
* Cavets.
*
* - RC4_CHUNK="unsigned long long" should be a #1 choice for
* UltraSPARC. Unfortunately gcc generates very slow code
* (2.5-3 times slower than one generated by Sun's WorkShop
* C) and therefore gcc (at least 2.95 and earlier) should
* always be told that RC4_CHUNK="unsigned long".
*
* <appro@fy.chalmers.se>
*/
# define RC4_STEP ( \
x=(x+1) &0xff, \
tx=d[x], \
y=(tx+y)&0xff, \
ty=d[y], \
d[y]=tx, \
d[x]=ty, \
(RC4_CHUNK)d[(tx+ty)&0xff]\
)
if ( ( ((unsigned long)indata & (sizeof(RC4_CHUNK)-1)) |
((unsigned long)outdata & (sizeof(RC4_CHUNK)-1)) ) == 0 )
{
RC4_CHUNK ichunk,otp;
const union { long one; char little; } is_endian = {1};
/*
* I reckon we can afford to implement both endian
* cases and to decide which way to take at run-time
* because the machine code appears to be very compact
* and redundant 1-2KB is perfectly tolerable (i.e.
* in case the compiler fails to eliminate it:-). By
* suggestion from Terrel Larson <terr@terralogic.net>
* who also stands for the is_endian union:-)
*
* Special notes.
*
* - is_endian is declared automatic as doing otherwise
* (declaring static) prevents gcc from eliminating
* the redundant code;
* - compilers (those I've tried) don't seem to have
* problems eliminating either the operators guarded
* by "if (sizeof(RC4_CHUNK)==8)" or the condition
* expressions themselves so I've got 'em to replace
* corresponding #ifdefs from the previous version;
* - I chose to let the redundant switch cases when
* sizeof(RC4_CHUNK)!=8 be (were also #ifdefed
* before);
* - in case you wonder "&(sizeof(RC4_CHUNK)*8-1)" in
* [LB]ESHFT guards against "shift is out of range"
* warnings when sizeof(RC4_CHUNK)!=8
*
* <appro@fy.chalmers.se>
*/
if (!is_endian.little)
{ /* BIG-ENDIAN CASE */
# define BESHFT(c) (((sizeof(RC4_CHUNK)-(c)-1)*8)&(sizeof(RC4_CHUNK)*8-1))
for (;len&-sizeof(RC4_CHUNK);len-=sizeof(RC4_CHUNK))
{
ichunk = *(RC4_CHUNK *)indata;
otp = RC4_STEP<<BESHFT(0);
otp |= RC4_STEP<<BESHFT(1);
otp |= RC4_STEP<<BESHFT(2);
otp |= RC4_STEP<<BESHFT(3);
if (sizeof(RC4_CHUNK)==8)
{
otp |= RC4_STEP<<BESHFT(4);
otp |= RC4_STEP<<BESHFT(5);
otp |= RC4_STEP<<BESHFT(6);
otp |= RC4_STEP<<BESHFT(7);
}
*(RC4_CHUNK *)outdata = otp^ichunk;
indata += sizeof(RC4_CHUNK);
outdata += sizeof(RC4_CHUNK);
}
if (len)
{
RC4_CHUNK mask=(RC4_CHUNK)-1, ochunk;
ichunk = *(RC4_CHUNK *)indata;
ochunk = *(RC4_CHUNK *)outdata;
otp = 0;
i = BESHFT(0);
mask <<= (sizeof(RC4_CHUNK)-len)<<3;
switch (len&(sizeof(RC4_CHUNK)-1))
{
case 7: otp = RC4_STEP<<i, i-=8;
case 6: otp |= RC4_STEP<<i, i-=8;
case 5: otp |= RC4_STEP<<i, i-=8;
case 4: otp |= RC4_STEP<<i, i-=8;
case 3: otp |= RC4_STEP<<i, i-=8;
case 2: otp |= RC4_STEP<<i, i-=8;
case 1: otp |= RC4_STEP<<i, i-=8;
case 0: ; /*
* it's never the case,
* but it has to be here
* for ultrix?
*/
}
ochunk &= ~mask;
ochunk |= (otp^ichunk) & mask;
*(RC4_CHUNK *)outdata = ochunk;
}
key->x=x;
key->y=y;
return;
}
else
{ /* LITTLE-ENDIAN CASE */
# define LESHFT(c) (((c)*8)&(sizeof(RC4_CHUNK)*8-1))
for (;len&-sizeof(RC4_CHUNK);len-=sizeof(RC4_CHUNK))
{
ichunk = *(RC4_CHUNK *)indata;
otp = RC4_STEP;
otp |= RC4_STEP<<8;
otp |= RC4_STEP<<16;
otp |= RC4_STEP<<24;
if (sizeof(RC4_CHUNK)==8)
{
otp |= RC4_STEP<<LESHFT(4);
otp |= RC4_STEP<<LESHFT(5);
otp |= RC4_STEP<<LESHFT(6);
otp |= RC4_STEP<<LESHFT(7);
}
*(RC4_CHUNK *)outdata = otp^ichunk;
indata += sizeof(RC4_CHUNK);
outdata += sizeof(RC4_CHUNK);
}
if (len)
{
RC4_CHUNK mask=(RC4_CHUNK)-1, ochunk;
ichunk = *(RC4_CHUNK *)indata;
ochunk = *(RC4_CHUNK *)outdata;
otp = 0;
i = 0;
mask >>= (sizeof(RC4_CHUNK)-len)<<3;
switch (len&(sizeof(RC4_CHUNK)-1))
{
case 7: otp = RC4_STEP, i+=8;
case 6: otp |= RC4_STEP<<i, i+=8;
case 5: otp |= RC4_STEP<<i, i+=8;
case 4: otp |= RC4_STEP<<i, i+=8;
case 3: otp |= RC4_STEP<<i, i+=8;
case 2: otp |= RC4_STEP<<i, i+=8;
case 1: otp |= RC4_STEP<<i, i+=8;
case 0: ; /*
* it's never the case,
* but it has to be here
* for ultrix?
*/
}
ochunk &= ~mask;
ochunk |= (otp^ichunk) & mask;
*(RC4_CHUNK *)outdata = ochunk;
}
key->x=x;
key->y=y;
return;
}
}
#endif
#define LOOP(in,out) \
x=((x+1)&0xff); \
tx=d[x]; \
y=(tx+y)&0xff; \
d[x]=ty=d[y]; \
d[y]=tx; \
(out) = d[(tx+ty)&0xff]^ (in);
#ifndef RC4_INDEX
#define RC4_LOOP(a,b,i) LOOP(*((a)++),*((b)++))
#else
#define RC4_LOOP(a,b,i) LOOP(a[i],b[i])
#endif
i=(int)(len>>3L);
if (i)
{
for (;;)
{
RC4_LOOP(indata,outdata,0);
RC4_LOOP(indata,outdata,1);
RC4_LOOP(indata,outdata,2);
RC4_LOOP(indata,outdata,3);
RC4_LOOP(indata,outdata,4);
RC4_LOOP(indata,outdata,5);
RC4_LOOP(indata,outdata,6);
RC4_LOOP(indata,outdata,7);
#ifdef RC4_INDEX
indata+=8;
outdata+=8;
#endif
if (--i == 0) break;
}
}
i=(int)len&0x07;
if (i)
{
for (;;)
{
RC4_LOOP(indata,outdata,0); if (--i == 0) break;
RC4_LOOP(indata,outdata,1); if (--i == 0) break;
RC4_LOOP(indata,outdata,2); if (--i == 0) break;
RC4_LOOP(indata,outdata,3); if (--i == 0) break;
RC4_LOOP(indata,outdata,4); if (--i == 0) break;
RC4_LOOP(indata,outdata,5); if (--i == 0) break;
RC4_LOOP(indata,outdata,6); if (--i == 0) break;
}
}
key->x=x;
key->y=y;
}
#ifndef COMPACK_SIZE
const char *RC4_options(void)
{
#ifdef RC4_INDEX
if (sizeof(RC4_INT) == 1)
return("rc4(idx,char)");
else
return("rc4(idx,int)");
#else
if (sizeof(RC4_INT) == 1)
return("rc4(ptr,char)");
else
return("rc4(ptr,int)");
#endif
}
#endif
/* RC4 as implemented from a posting from
* Newsgroups: sci.crypt
* From: sterndark@netcom.com (David Sterndark)
* Subject: RC4 Algorithm revealed.
* Message-ID: <sternCvKL4B.Hyy@netcom.com>
* Date: Wed, 14 Sep 1994 06:35:31 GMT
*/
void RC4_set_key(RC4_KEY *key, int len, const unsigned char *data)
{
register RC4_INT tmp;
register int id1,id2;
register RC4_INT *d;
unsigned int i;
d= &(key->data[0]);
for (i=0; i<256; i++)
d[i]=i;
key->x = 0;
key->y = 0;
id1=id2=0;
#define SK_LOOP(n) { \
tmp=d[(n)]; \
id2 = (data[id1] + tmp + id2) & 0xff; \
if (++id1 == len) id1=0; \
d[(n)]=d[id2]; \
d[id2]=tmp; }
for (i=0; i < 256; i+=4)
{
SK_LOOP(i+0);
SK_LOOP(i+1);
SK_LOOP(i+2);
SK_LOOP(i+3);
}
}
#endif // INCLUDE_WPA_PSK
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/1x_rc4.h
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/* crypto/rc4/rc4.h */
/* Copyright (C) 1995-1997 Eric Young (eay@cryptsoft.com)
* All rights reserved.
*
* This package is an SSL implementation written
* by Eric Young (eay@cryptsoft.com).
* The implementation was written so as to conform with Netscapes SSL.
*
* This library is free for commercial and non-commercial use as long as
* the following conditions are aheared to. The following conditions
* apply to all code found in this distribution, be it the RC4, RSA,
* lhash, DES, etc., code; not just the SSL code. The SSL documentation
* included with this distribution is covered by the same copyright terms
* except that the holder is Tim Hudson (tjh@cryptsoft.com).
*
* Copyright remains Eric Young's, and as such any Copyright notices in
* the code are not to be removed.
* If this package is used in a product, Eric Young should be given attribution
* as the author of the parts of the library used.
* This can be in the form of a textual message at program startup or
* in documentation (online or textual) provided with the package.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* "This product includes cryptographic software written by
* Eric Young (eay@cryptsoft.com)"
* The word 'cryptographic' can be left out if the rouines from the library
* being used are not cryptographic related :-).
* 4. If you include any Windows specific code (or a derivative thereof) from
* the apps directory (application code) you must include an acknowledgement:
* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
*
* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The licence and distribution terms for any publically available version or
* derivative of this code cannot be changed. i.e. this code cannot simply be
* copied and put under another distribution licence
* [including the GNU Public Licence.]
*/
#ifndef HEADER_RC4_H
#define HEADER_RC4_H
#ifdef OPENSSL_NO_RC4
#error RC4 is disabled.
#endif
//#include <openssl/opensslconf.h> /* RC4_INT */
#define RC4_INT unsigned int
#ifdef __cplusplus
extern "C" {
#endif
typedef struct rc4_key_st
{
RC4_INT x,y;
RC4_INT data[256];
} RC4_KEY;
const char *RC4_options(void);
void RC4_set_key(RC4_KEY *key, int len, const unsigned char *data);
void RC4(RC4_KEY *key, unsigned long len, const unsigned char *indata,
unsigned char *outdata);
#ifdef __cplusplus
}
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8188e_hw.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8188e_reg.h
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192c_reg.h
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd.h
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_11h.c
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/*
* Software TKIP encryption/descryption routines
*
* $Id: 8192cd_tkip.c,v 1.4.4.2 2010/09/30 05:27:28 button Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define _8192CD_11H_C_
#ifdef __KERNEL__
#include <linux/module.h>
#include <asm/byteorder.h>
#elif defined(__ECOS)
#include <cyg/io/eth/rltk/819x/wrapper/sys_support.h>
#include <cyg/io/eth/rltk/819x/wrapper/skbuff.h>
#include <cyg/io/eth/rltk/819x/wrapper/timer.h>
#include <cyg/io/eth/rltk/819x/wrapper/wrapper.h>
#endif
#include "./8192cd_cfg.h"
#if !defined(__KERNEL__) && !defined(__ECOS)
#include "./sys-support.h"
#endif
#include "./8192cd.h"
#ifdef __KERNEL__
#include "./ieee802_mib.h"
#elif defined(__ECOS)
#include <cyg/io/eth/rltk/819x/wlan/ieee802_mib.h>
#endif
#include "./8192cd_util.h"
#include "./8192cd_headers.h"
#include "./8192cd_debug.h"
#if (defined(DOT11D) || defined(DOT11H))
#define MAX_CHANNEL_SET_NUMBER 20
typedef struct _PER_CHANNEL_ENTRY_ {
unsigned char firstChannel;
unsigned char numberOfChannel;
unsigned char maxTxDbm;
} PER_CHANNEL_ENTRY;
typedef struct _BAND_TABLE_ELEMENT_ {
unsigned char channel_set_number;
PER_CHANNEL_ENTRY channel_set[MAX_CHANNEL_SET_NUMBER];
} BAND_TABLE_ELEMENT;
typedef struct _COUNTRY_IE_ELEMENT_ {
unsigned int countryNumber;
unsigned char countryA2[3];
unsigned char A_Band_Region; //if support 5G A band? ; 0 == no support ; aBandRegion == real region domain
unsigned char G_Band_Region; //if support 2.4G G band? ; 0 == no support ; bBandRegion == real region domain
} COUNTRY_IE_ELEMENT;
static const COUNTRY_IE_ELEMENT countryIEArray[] =
{
/*
format: countryNumber | CountryCode(A2)
*/
{8,"AL ", 3, 3}, /*ALBANIA*/
{12,"DZ ", 3, 3}, /*ALGERIA*/
{32,"AR ", 3, 3}, /*ARGENTINA*/
{51,"AM ", 3, 3}, /*ARMENIA*/
{36,"AU ", 3, 3}, /*AUSTRALIA*/
{40,"AT ", 3, 3}, /*AUSTRIA*/
{31,"AZ ", 3, 3}, /*AZERBAIJAN*/
{48,"BH ", 3, 3}, /*BAHRAIN*/
{112,"BY", 3, 3}, /*BELARUS*/
{56,"BE ", 3, 3}, /*BELGIUM*/
{84,"BZ ", 3, 3}, /*BELIZE*/
{68,"BO ", 3, 3}, /*BOLIVIA*/
{76,"BR ", 3, 3}, /*BRAZIL*/
{96,"BN ", 3, 3}, /*BRUNEI*/
{100,"BG ", 3, 3}, /*BULGARIA*/
{124,"CA ", 1, 1}, /*CANADA*/
{152,"CL ", 3, 3}, /*CHILE*/
{156,"CN ",13,13}, /*CHINA*/
{170,"CO ", 1, 1}, /*COLOMBIA*/
{188,"CR ", 3, 3}, /*COSTA RICA*/
{191,"HR ", 3, 3}, /*CROATIA*/
{196,"CY ", 3, 3}, /*CYPRUS*/
{203,"CZ ", 3, 3}, /*CZECH REPUBLIC*/
{208,"DK ", 3, 3}, /*DENMARK*/
{214,"DO ", 1, 1}, /*DOMINICAN REPUBLIC*/
{218,"EC ", 3, 3}, /*ECUADOR*/
{818,"EG ", 3, 3}, /*EGYPT*/
{222,"SV ", 3, 3}, /*EL SALVADOR*/
{233,"EE ", 3, 3}, /*ESTONIA*/
{246,"FI ", 3, 3}, /*FINLAND*/
{250,"FR ", 3, 3}, /*FRANCE*/
{268,"GE ", 3, 3}, /*GEORGIA*/
{276,"DE ", 3, 3}, /*GERMANY*/
{300,"GR ", 3, 3}, /*GREECE*/
{320,"GT ", 1, 1}, /*GUATEMALA*/
{340,"HN ", 3, 3}, /*HONDURAS*/
{344,"HK ", 3, 3}, /*HONG KONG*/
{348,"HU ", 3, 3}, /*HUNGARY*/
{352,"IS ", 3, 3}, /*ICELAND*/
{356,"IN ", 3, 3}, /*INDIA*/
{360,"ID ", 3, 3}, /*INDONESIA*/
{364,"IR ", 3, 3}, /*IRAN*/
{372,"IE ", 3, 3}, /*IRELAND*/
{376,"IL ", 7, 7}, /*ISRAEL*/
{380,"IT ", 3, 3}, /*ITALY*/
{392,"JP ", 6, 6}, /*JAPAN*/
{400,"JO ", 3, 3}, /*JORDAN*/
{398,"KZ ", 3, 3}, /*KAZAKHSTAN*/
{410,"KR ", 3, 3}, /*NORTH KOREA*/
{408,"KP ", 3, 3}, /*KOREA REPUBLIC*/
{414,"KW ", 3, 3}, /*KUWAIT*/
{428,"LV ", 3, 3}, /*LATVIA*/
{422,"LB ", 3, 3}, /*LEBANON*/
{438,"LI ", 3, 3}, /*LIECHTENSTEIN*/
{440,"LT ", 3, 3}, /*LITHUANIA*/
{442,"LU ", 3, 3}, /*LUXEMBOURG*/
{446,"MO ", 3, 3}, /*CHINA MACAU*/
{807,"MK ", 3, 3}, /*MACEDONIA*/
{458,"MY ", 3, 3}, /*MALAYSIA*/
{484,"MX ", 1, 1}, /*MEXICO*/
{492,"MC ", 3, 3}, /*MONACO*/
{504,"MA ", 3, 3}, /*MOROCCO*/
{528,"NL ", 3, 3}, /*NETHERLANDS*/
{554,"NZ ", 3, 3}, /*NEW ZEALAND*/
{578,"NO ", 3, 3}, /*NORWAY*/
{512,"OM ", 3, 3}, /*OMAN*/
{586,"PK ", 3, 3}, /*PAKISTAN*/
{591,"PA ", 1, 1}, /*PANAMA*/
{604,"PE ", 3, 3}, /*PERU*/
{608,"PH ", 3, 3}, /*PHILIPPINES*/
{616,"PL ", 3, 3}, /*POLAND*/
{620,"PT ", 3, 3}, /*PORTUGAL*/
{630,"PR ", 1, 1}, /*PUERTO RICO*/
{634,"QA ", 3, 3}, /*QATAR*/
{642,"RO ", 3, 3}, /*ROMANIA*/
{643,"RU ",12,12}, /*RUSSIAN*/
{682,"SA ", 3, 3}, /*SAUDI ARABIA*/
{702,"SG ", 3, 3}, /*SINGAPORE*/
{703,"SK ", 3, 3}, /*SLOVAKIA*/
{705,"SI ", 3, 3}, /*SLOVENIA*/
{710,"ZA ", 3, 3}, /*SOUTH AFRICA*/
{724,"ES ", 3, 3}, /*SPAIN*/
{752,"SE ", 3, 3}, /*SWEDEN*/
{756,"CH ", 3, 3}, /*SWITZERLAND*/
{760,"SY ", 3, 3}, /*SYRIAN ARAB REPUBLIC*/
{158,"TW ",11,11}, /*TAIWAN*/
{764,"TH ", 3, 3}, /*THAILAND*/
{780,"TT ", 3, 3}, /*TRINIDAD AND TOBAGO*/
{788,"TN ", 3, 3}, /*TUNISIA*/
{792,"TR ", 3, 3}, /*TURKEY*/
{804,"UA ", 3, 3}, /*UKRAINE*/
{784,"AE ", 3, 3}, /*UNITED ARAB EMIRATES*/
{826,"GB ", 3, 3}, /*UNITED KINGDOM*/
{840,"US ", 1, 1}, /*UNITED STATES*/
{858,"UY ", 3, 3}, /*URUGUAY*/
{860,"UZ ", 1, 1}, /*UZBEKISTAN*/
{862,"VE ", 3, 3}, /*VENEZUELA*/
{704,"VN ", 3, 3}, /*VIET NAM*/
{887,"YE ", 3, 3}, /*YEMEN*/
{716,"ZW ", 3, 3}, /*ZIMBABWE*/
};
static const BAND_TABLE_ELEMENT country_ie_channel_2_4g[] = {
/* number of channel set | array of channel sets{first channel, num of channel, tx power}
transmit tx power is copy from CAMEO
*/
/* (1) FCC */ {1, {{1, 11, 30}}},
/* (2) IC */ {1, {{1, 11, 30}}},
/* (3) ETSI */ {1, {{1, 13, 30}}},
/* (4) SPAIN */ {1, {{1, 13, 30}}},
/* (5) FRANCE */ {1, {{10, 4, 30}}},
/* (6) MKK */ {1, {{1, 14, 30}}},
/* (7) ISRAEL */ {1, {{3, 11, 30}}},
/* (8) MKK1 */ {1, {{1, 14, 30}}},
/* (9) MKK2 */ {1, {{1, 14, 30}}},
/* (10) MKK3 */ {1, {{1, 14, 30}}},
/* (11) NCC (Taiwan) */ {1, {{1, 11, 30}}},
/* (12) RUSSIAN */ {1, {{1, 13, 30}}},
/* (13) CN */ {1, {{1, 13, 30}}},
/* (14) Global */ {1, {{1, 14, 30}}},
/* (15) World_wide */ {1, {{1, 13, 30}}},
/* (16) Test */ {1, {{1, 14, 30}}},
};
static const BAND_TABLE_ELEMENT country_ie_channel_5g[] = {
/* number of channel set | array of channel sets {first channel, num of channel, tx power},
transmit tx power is copy from CAMEO
*/
/*(1) FCC */ {20, {{36,1,30}, {40,1,30}, {44,1,30}, {48,1,30},
{52,1,30}, {56,1,30}, {60,1,30}, {64,1,30},
{100,1,20},{104,1,20},{108,1,20},{112,1,20},{116,1,20},{136,1,20},{140,1,20},
{149,1,30},{153,1,30},{157,1,30},{161,1,30},{165,1,30} }
},
/* (2) IC */ {12, {{36,1,30}, {40,1,30}, {44,1,30}, {48,1,30},
{52,1,30}, {56,1,30}, {60,1,30}, {64,1,30},
{149,1,30},{153,1,30},{157,1,30},{161,1,30} }
},
/* (3) ETSI */ {19, {{36,1,30}, {40,1,30}, {44,1,30}, {48,1,30},
{52,1,30}, {56,1,30}, {60,1,30}, {64,1,30},
{100,1,20},{104,1,20},{108,1,20},{112,1,20},{116,1,20},{120,1,20},{124,1,20},{128,1,20},{132,1,20},{136,1,20},{140,1,20} }
},
/* (4) SPAIN */ {3, {{36,4,30}, //36, 40, 44, 48
{52,4,30}, //52, 56, 60, 64
{100,11,20} } //100, 104, 108, 112, 116,120,124,128,132,136,140
},
/* (5) FRANCE */ {3, {{36,4,30}, //36, 40, 44, 48
{52,4,30}, //52, 56, 60, 64
{100,11,20} } //100, 104, 108, 112, 116,120,124,128,132,136,140
},
/* (6) MKK */ {19, {{36,1,30}, {40,1,30}, {44,1,30}, {48,1,30},
{52,1,30}, {56,1,30}, {60,1,30}, {64,1,30},
{100,1,20},{104,1,20},{108,1,20},{112,1,20},{116,1,20},{120,1,20},{124,1,20},{128,1,20},{132,1,20},{136,1,20},{140,1,20} }
},
/* (7) ISRAEL */ {19, {{36,1,30}, {40,1,30}, {44,1,30}, {48,1,30},
{52,1,30}, {56,1,30}, {60,1,30}, {64,1,30},
{100,1,30},{104,1,30},{108,1,30},{112,1,30},{116,1,30},{120,1,30},{124,1,30},{128,1,30},{132,1,30},{136,1,30},{140,1,30} }
},
/* (8) MKK1 */ {1, {{34,4,30} } // 34, 38, 42, 46
},
/* (9) MKK2 */ {1, {{36,4,30} } //36, 40, 44, 48
},
/* (10) MKK3 */ {2, {{36,4,30}, //36, 40, 44, 48
{52,4,30} } //52, 56, 60, 64
},
/* (11) NCC (Taiwan) */
{15, {{56,1,30}, {60,1,30}, {64,1,30},
{100,1,20},{104,1,20},{108,1,20},{112,1,20},{116,1,20},{136,1,20},{140,1,20},
{149,1,30},{153,1,30},{157,1,30},{161,1,30},{165,1,30} }
},
/* (12) RUSSIAN */{16, {{36,1,20}, {40,1,20}, {44,1,20}, {48,1,20},
{52,1,20}, {56,1,20}, {60,1,20}, {64,1,20},
{132,1,30},{136,1,30},{140,1,30},
{149,1,30},{153,1,30},{157,1,30},{161,1,30},{165,1,30}}
},
/* (13) CN */ {13, {{36,1,30}, {40,1,30}, {44,1,30}, {48,1,30},
{52,1,30}, {56,1,30}, {60,1,30}, {64,1,30},
{149,1,30},{153,1,30},{157,1,30},{161,1,30},{165,1,30} }
},
/* (14) Global */ {20, {{36,1,30}, {40,1,30}, {44,1,30}, {48,1,30},
{52,1,30}, {56,1,30}, {60,1,30}, {64,1,30},
{100,1,30},{104,1,30},{108,1,30},{112,1,30},{116,1,30},{136,1,30},{140,1,30},
{149,1,30},{153,1,30},{157,1,30},{161,1,30},{165,1,30} }
},
/* (15) World_wide */
{20, {{36,1,30}, {40,1,30}, {44,1,30}, {48,1,30},
{52,1,30}, {56,1,30}, {60,1,30}, {64,1,30},
{100,1,30},{104,1,30},{108,1,30},{112,1,30},{116,1,30},{136,1,30},{140,1,30},
{149,1,30},{153,1,30},{157,1,30},{161,1,30},{165,1,30} }
},
/* (16) Test */ {4, {{36,4,30}, //36, 40, 44, 48
{52,4,30}, //52, 56, 60, 64
{100,12,30}, //100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144
{149,8,30} } //149, 153, 157, 161, 165, 169, 173, 177
},
/* (17) 5M10M */ {1, {{146,25,30} } // 146 ~ 170
},
};
void check_country_channel_table(struct rtl8192cd_priv *priv) {
unsigned char i = 0, country_num;
priv->countryTableIdx = 0;
if(COUNTRY_CODE_ENABLED || priv->pmib->dot11hTPCEntry.tpc_enable)
{
country_num = sizeof(countryIEArray)/sizeof(COUNTRY_IE_ELEMENT);
for (i=0; i<country_num; i++) {
if (!memcmp(priv->pmib->dot11dCountry.dot11CountryString, countryIEArray[i].countryA2, 2)) {
priv->countryTableIdx = i + 1;
break;
}
}
if (priv->countryTableIdx == 0) {
printk("can't found country code(%s)\n", priv->pmib->dot11dCountry.dot11CountryString);
}
}
}
unsigned char * construct_country_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen) {
const COUNTRY_IE_ELEMENT * country_ie;
const BAND_TABLE_ELEMENT * band_table = NULL;
unsigned char temp[MAX_CHANNEL_SET_NUMBER*3 + 3 + 1];/*channel sets + country code + 1 possible padding*/
unsigned int len = 0;
country_ie = &(countryIEArray[priv->countryTableIdx-1]);
if ( priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_2G) {
if(country_ie->G_Band_Region) {
band_table = &(country_ie_channel_2_4g[country_ie->G_Band_Region-1]);
}
}
else {
if(country_ie->A_Band_Region) {
band_table = &(country_ie_channel_5g[country_ie->A_Band_Region-1]);
}
}
if(band_table) {
memcpy(temp + len, country_ie->countryA2, 3);
len += 3;
memcpy(temp + len, (unsigned char *)band_table->channel_set, band_table->channel_set_number*3);
len += band_table->channel_set_number*3;
/*add padding, the length of country ie must divided by two*/
if(len%2) {
temp[len] = 0;
len++;
}
pbuf = set_ie(pbuf, _COUNTRY_IE_, len, temp, frlen);
}
return pbuf;
}
#endif
#ifdef DOT11H
#if defined(CLIENT_MODE) || defined(CONFIG_RTK_MESH)
unsigned char * construct_power_capability_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen) {
unsigned char temp[2];
temp[0] = priv->pmib->dot11hTPCEntry.min_tx_power;
temp[1] = priv->pmib->dot11hTPCEntry.max_tx_power;
pbuf = set_ie(pbuf, _PWR_CAPABILITY_IE_, 2, temp, frlen);
return pbuf;
}
unsigned char * construct_supported_channel_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen) {
const COUNTRY_IE_ELEMENT * country_ie;
const BAND_TABLE_ELEMENT * band_table = NULL;
unsigned char temp[MAX_CHANNEL_SET_NUMBER*2];/*channel sets*/
unsigned int i,j = 0;
if(priv->countryTableIdx) {
country_ie = &(countryIEArray[priv->countryTableIdx-1]);
if ( priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_2G) {
if(country_ie->G_Band_Region) {
band_table = &(country_ie_channel_2_4g[country_ie->G_Band_Region-1]);
}
}
else {
if(country_ie->A_Band_Region) {
band_table = &(country_ie_channel_5g[country_ie->A_Band_Region-1]);
}
}
if(band_table) {
for(i = 0; i < band_table->channel_set_number; i++) {
temp[j++] = band_table->channel_set[i].firstChannel;
temp[j++] = band_table->channel_set[i].numberOfChannel;
}
pbuf = set_ie(pbuf, _SUPPORTED_CHANNEL_IE_, j, temp, frlen);
}
}
return pbuf;
}
#endif
unsigned char * construct_TPC_report_ie(struct rtl8192cd_priv *priv, unsigned char *pbuf, unsigned int *frlen) {
unsigned char temp[2];
temp[0] = priv->pmib->dot11hTPCEntry.tpc_tx_power;
temp[1] = priv->pmib->dot11hTPCEntry.tpc_link_margin;
pbuf = set_ie(pbuf, _TPC_REPORT_IE_, 2, temp, frlen);
return pbuf;
}
void issue_TPC_report(struct rtl8192cd_priv *priv, unsigned char *da, unsigned char dialog_token) {
unsigned char *pbuf;
unsigned int frlen;
DECLARE_TXINSN(txinsn);
txinsn.q_num = MANAGE_QUE_NUM;
txinsn.fr_type = _PRE_ALLOCMEM_;
#ifdef P2P_SUPPORT // 2013
if(OPMODE&WIFI_P2P_SUPPORT){
txinsn.tx_rate = _6M_RATE_;
}else
#endif
txinsn.tx_rate = find_rate(priv, NULL, 0, 1);
txinsn.lowest_tx_rate = txinsn.tx_rate;
txinsn.fixed_rate = 1;
pbuf = txinsn.pframe = get_mgtbuf_from_poll(priv);
if (pbuf == NULL)
goto issue_TPC_report_fail;
txinsn.phdr = get_wlanhdr_from_poll(priv);
if (txinsn.phdr == NULL)
goto issue_TPC_report_fail;
memset((void *)(txinsn.phdr), 0, sizeof(struct wlan_hdr));
pbuf[0] = _SPECTRUM_MANAGEMENT_CATEGORY_ID_;
pbuf[1] = _TPC_REPORT_ACTION_ID_;
pbuf[2] = dialog_token;
frlen = 3;
construct_TPC_report_ie(priv, pbuf + frlen, &frlen);
txinsn.fr_len += frlen;
SetFrameSubType((txinsn.phdr), WIFI_WMM_ACTION);
memcpy((void *)GetAddr1Ptr((txinsn.phdr)), da, MACADDRLEN);
memcpy((void *)GetAddr2Ptr((txinsn.phdr)), GET_MY_HWADDR, MACADDRLEN);
memcpy((void *)GetAddr3Ptr((txinsn.phdr)), BSSID, MACADDRLEN);
if ((rtl8192cd_firetx(priv, &txinsn)) == SUCCESS)
return;
issue_TPC_report_fail:
if (txinsn.phdr)
release_wlanhdr_to_poll(priv, txinsn.phdr);
if (txinsn.pframe)
release_mgtbuf_to_poll(priv, txinsn.pframe);
return;
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_a4_sta.c
Executable
+242
View File
@@ -0,0 +1,242 @@
/*
* a4 sta functions
*
* $Id: 8192cd_a4_sta.c,v 1.1 2010/10/13 06:38:58 davidhsu Exp $
*
* Copyright (c) 2010 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define _8192CD_A4_STA_C_
#ifdef __KERNEL__
#include <linux/slab.h>
#include <linux/sched.h>
#include <linux/timer.h>
#endif
#include "./8192cd_cfg.h"
#ifdef A4_STA
#include "./8192cd.h"
#include "./8192cd_headers.h"
#include "./8192cd_debug.h"
//#define A4_STA_DEBUG
static struct a4_sta_db_entry *alloc_entry(struct rtl8192cd_priv *priv)
{
int i;
for (i=0; i<MAX_A4_TBL_NUM; i++) {
if (!priv->a4_ent[i].used) {
priv->a4_ent[i].used = 1;
return &priv->a4_ent[i].entry;
}
}
return NULL;
}
static void free_entry(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *entry)
{
int i;
for (i=0; i<MAX_A4_TBL_NUM; i++) {
if (priv->a4_ent[i].used && (entry == &priv->a4_ent[i].entry)) {
priv->a4_ent[i].used = 0;
break;
}
}
}
static int mac_hash(unsigned char *networkAddr)
{
unsigned long x;
x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5];
return x & (A4_STA_HASH_SIZE - 1);
}
static void mac_hash_link(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *ent, int hash)
{
ent->next_hash = priv->machash[hash];
if (ent->next_hash != NULL)
ent->next_hash->pprev_hash = &ent->next_hash;
priv->machash[hash] = ent;
ent->pprev_hash = &priv->machash[hash];
}
static void mac_hash_unlink(struct a4_sta_db_entry *ent)
{
*(ent->pprev_hash) = ent->next_hash;
if (ent->next_hash != NULL)
ent->next_hash->pprev_hash = ent->pprev_hash;
ent->next_hash = NULL;
ent->pprev_hash = NULL;
}
static unsigned long _timeout(struct rtl8192cd_priv *priv)
{
unsigned long timeout;
timeout = jiffies - A4_STA_AGEING_TIME*HZ;
return timeout;
}
static int has_expired(struct rtl8192cd_priv *priv, struct a4_sta_db_entry *fdb)
{
if (time_before_eq(fdb->ageing_timer, _timeout(priv)))
return 1;
return 0;
}
void a4_sta_cleanup(struct rtl8192cd_priv *priv)
{
int i;
if (priv->pshare->rf_ft_var.a4_enable) {
for (i=0; i<A4_STA_HASH_SIZE; i++) {
struct a4_sta_db_entry *f;
f = priv->machash[i];
while (f != NULL) {
struct a4_sta_db_entry *g;
g = f->next_hash;
mac_hash_unlink(f);
free_entry(priv, f);
f = g;
}
}
}
}
void a4_sta_expire(struct rtl8192cd_priv *priv)
{
int i;
if (priv->pshare->rf_ft_var.a4_enable) {
for (i=0; i<A4_STA_HASH_SIZE; i++) {
struct a4_sta_db_entry *f;
f = priv->machash[i];
while (f != NULL) {
struct a4_sta_db_entry *g;
g = f->next_hash;
if (has_expired(priv, f)) {
#ifdef A4_STA_DEBUG
panic_printk("A4 STA Expire (%02d) emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n",
i,
f->mac[0],
f->mac[1],
f->mac[2],
f->mac[3],
f->mac[4],
f->mac[5],
f->stat->hwaddr[0],
f->stat->hwaddr[1],
f->stat->hwaddr[2],
f->stat->hwaddr[3],
f->stat->hwaddr[4],
f->stat->hwaddr[5]);
#endif
mac_hash_unlink(f);
free_entry(priv, f);
}
f = g;
}
}
}
}
void a4_sta_add(struct rtl8192cd_priv *priv, struct stat_info *pstat, unsigned char *mac)
{
struct a4_sta_db_entry *db;
int hash;
ASSERT(mac);
hash = mac_hash(mac);
db = priv->machash[hash];
while (db != NULL) {
if (!memcmp(db->mac, mac, ETH_ALEN)) {
db->stat = pstat;
db->ageing_timer = jiffies;
return;
}
db = db->next_hash;
}
db = alloc_entry(priv);
if (db == NULL) {
DEBUG_ERR("alloc_entry() failed for a4_sta_db_entry!\n");
return;
}
memcpy(db->mac, mac, ETH_ALEN);
db->stat = pstat;
db->ageing_timer = jiffies;
#ifdef A4_STA_DEBUG
panic_printk("A4 STA Add emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n",
db->mac[0],
db->mac[1],
db->mac[2],
db->mac[3],
db->mac[4],
db->mac[5],
db->stat->hwaddr[0],
db->stat->hwaddr[1],
db->stat->hwaddr[2],
db->stat->hwaddr[3],
db->stat->hwaddr[4],
db->stat->hwaddr[5]);
#endif
mac_hash_link(priv, db, hash);
}
struct stat_info *a4_sta_lookup(struct rtl8192cd_priv *priv, unsigned char *mac)
{
struct a4_sta_db_entry *db;
ASSERT(mac);
db = priv->machash[mac_hash(mac)];
while (db != NULL) {
if (!memcmp(db->mac, mac, ETH_ALEN)) {
#ifdef A4_STA_DEBUG
panic_printk("A4 STA LOOKUP emac:%02x%02x%02x%02x%02x%02x, wmac:%02x%02x%02x%02x%02x%02x\n",
db->mac[0],
db->mac[1],
db->mac[2],
db->mac[3],
db->mac[4],
db->mac[5],
db->stat->hwaddr[0],
db->stat->hwaddr[1],
db->stat->hwaddr[2],
db->stat->hwaddr[3],
db->stat->hwaddr[4],
db->stat->hwaddr[5]);
#endif
return db->stat;
}
db = db->next_hash;
}
return NULL;
}
#endif /* A4_STA */
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_aes.c
Executable
+1495
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_br_ext.c
Executable
+2602
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_br_ext.h
Executable
+49
View File
@@ -0,0 +1,49 @@
/*
* Headler file defines some data structure and macro of bridge extention
*
* $Id: 8192cd_br_ext.h,v 1.1.4.1 2010/07/28 13:15:27 davidhsu Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_BR_EXT_H_
#define _8192CD_BR_EXT_H_
#define NAT25_HASH_BITS 4
#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS)
#define NAT25_AGEING_TIME 300
#ifdef CL_IPV6_PASS
#define MAX_NETWORK_ADDR_LEN 17
#else
#define MAX_NETWORK_ADDR_LEN 11
#endif
struct nat25_network_db_entry
{
struct nat25_network_db_entry *next_hash;
struct nat25_network_db_entry **pprev_hash;
atomic_t use_count;
unsigned char macAddr[6];
unsigned long ageing_timer;
#ifdef __ECOS
unsigned int used;
#endif
unsigned char networkAddr[MAX_NETWORK_ADDR_LEN];
};
enum NAT25_METHOD {
NAT25_MIN,
NAT25_CHECK,
NAT25_INSERT,
NAT25_LOOKUP,
NAT25_PARSE,
NAT25_MAX
};
#endif // _8192CD_BR_EXT_H_
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_cfg.h
Executable
+2875
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_cfg80211.c
Executable
+6598
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_cfg80211.h
Executable
+381
View File
@@ -0,0 +1,381 @@
/*
* Copyright (c) 2011 Atheros Communications Inc.
* Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef RTK_NL80211
#define RTK_NL80211
#endif
#ifdef RTK_NL80211
#include "./wifi.h"/*cfg p2p cfg p2p*/
#include "osdep_service.h"
#define DSSET_IE_LEN 1
#define HTCAP_IE_LEN 26
#define HTINFO_IE_LEN 22
#define MAX_PROBED_SSIDS 32
#define VIF_NUM RTL8192CD_NUM_VWLAN //eric-vap
#define IF_NUM (VIF_NUM+2) //#vap + root + vxd
#define VIF_NAME_SIZE 10
/*cfg p2p cfg p2p*/
#define MAX_IE_LEN 768
#define MAX_ASSOC_REQ_LEN 512
#define MAX_ASSOC_RSP_LEN 512
// cliWW
extern void notify_cfg_evt(struct rtl8192cd_priv *priv, unsigned char *mac, int event, unsigned char *extra);
#define RATETAB_ENT(_rate, _rateid, _flags) { \
.bitrate = (_rate), \
.flags = (_flags), \
.hw_value = (_rateid), \
}
static struct ieee80211_rate realtek_rates[] = {
RATETAB_ENT(10, 0x1, 0),
RATETAB_ENT(20, 0x2, 0),
RATETAB_ENT(55, 0x4, 0),
RATETAB_ENT(110, 0x8, 0),
RATETAB_ENT(60, 0x10, 0),
RATETAB_ENT(90, 0x20, 0),
RATETAB_ENT(120, 0x40, 0),
RATETAB_ENT(180, 0x80, 0),
RATETAB_ENT(240, 0x100, 0),
RATETAB_ENT(360, 0x200, 0),
RATETAB_ENT(480, 0x400, 0),
RATETAB_ENT(540, 0x800, 0),
};
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
enum nl80211_chan_width {
NL80211_CHAN_WIDTH_20_NOHT,
NL80211_CHAN_WIDTH_20,
NL80211_CHAN_WIDTH_40,
NL80211_CHAN_WIDTH_80,
NL80211_CHAN_WIDTH_80p80,
NL80211_CHAN_WIDTH_160,
};
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
#define WLAN_CIPHER_SUITE_GCMP 0x000FAC08
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0)
#define WLAN_AKM_SUITE_PSK_SHA256 0x000FAC06
#endif
#define realtek_g_rates (realtek_rates + 0)
#define realtek_g_rates_size 12
#define realtek_a_rates (realtek_rates + 4)
#define realtek_a_rates_size 8
#define realtek_g_htcap (IEEE80211_HT_CAP_SUP_WIDTH_20_40 | \
IEEE80211_HT_CAP_SGI_20 | \
IEEE80211_HT_CAP_SGI_40)
#define realtek_a_htcap (IEEE80211_HT_CAP_SUP_WIDTH_20_40 | \
IEEE80211_HT_CAP_SGI_20 | \
IEEE80211_HT_CAP_SGI_40)
#define realtek_a_vhtcap (IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_80MHZ)
/* WMI_CONNECT_CMDID */
enum network_type {
INFRA_NETWORK = 0x01,
ADHOC_NETWORK = 0x02,
ADHOC_CREATOR = 0x04,
AP_NETWORK = 0x10,
};
enum scan_abort_case {
SCAN_ABORT_DEL_IFACE = 0,
SCAN_ABORT_START_AP,
};
#if 0/*cfg p2p cfg p2p*/
enum mgmt_type {
MGMT_BEACON = 0,
MGMT_PROBERSP = 1,
MGMT_ASSOCRSP = 2,
MGMT_ASSOCREQ = 3,
MGMT_PROBEREQ = 4,
};
#endif
static const u32 cipher_suites[] = {
WLAN_CIPHER_SUITE_WEP40,
WLAN_CIPHER_SUITE_WEP104,
WLAN_CIPHER_SUITE_TKIP,
WLAN_CIPHER_SUITE_CCMP,
WLAN_CIPHER_SUITE_AES_CMAC,
WLAN_CIPHER_SUITE_GCMP,
//CCKM_KRK_CIPHER_SUITE,
//WLAN_CIPHER_SUITE_SMS4,
};
#define CHAN2G(_channel, _freq, _flags) { \
.band = IEEE80211_BAND_2GHZ, \
.hw_value = (_channel), \
.center_freq = (_freq), \
.flags = (_flags), \
.max_antenna_gain = 0, \
.max_power = 30, \
}
#define CHAN5G(_channel, _flags) { \
.band = IEEE80211_BAND_5GHZ, \
.hw_value = (_channel), \
.center_freq = 5000 + (5 * (_channel)), \
.flags = (_flags), \
.max_antenna_gain = 0, \
.max_power = 30, \
}
static struct ieee80211_channel realtek_2ghz_channels[] = {
CHAN2G(1, 2412, IEEE80211_CHAN_NO_HT40MINUS),
CHAN2G(2, 2417, IEEE80211_CHAN_NO_HT40MINUS),
CHAN2G(3, 2422, IEEE80211_CHAN_NO_HT40MINUS),
CHAN2G(4, 2427, IEEE80211_CHAN_NO_HT40MINUS),
CHAN2G(5, 2432, 0),
CHAN2G(6, 2437, 0),
CHAN2G(7, 2442, 0),
CHAN2G(8, 2447, IEEE80211_CHAN_NO_HT40PLUS),
CHAN2G(9, 2452, IEEE80211_CHAN_NO_HT40PLUS),
CHAN2G(10, 2457, IEEE80211_CHAN_NO_HT40PLUS),
CHAN2G(11, 2462, IEEE80211_CHAN_NO_HT40PLUS),
CHAN2G(12, 2467, IEEE80211_CHAN_NO_HT40PLUS),
CHAN2G(13, 2472, IEEE80211_CHAN_NO_HT40PLUS),
CHAN2G(14, 2484, IEEE80211_CHAN_NO_HT40PLUS |
IEEE80211_CHAN_NO_HT40MINUS
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)
| IEEE80211_CHAN_NO_OFDM
#endif
)
};
static struct ieee80211_channel realtek_5ghz_a_channels[] = {
/* UNII-1 */
CHAN5G(36, IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(40, IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(44, IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(48, IEEE80211_CHAN_NO_HT40PLUS),
/* UNII-2 */
CHAN5G(52,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(56,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(60,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(64,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40PLUS),
/* MID */
CHAN5G(100,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(104,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(108,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(112,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(116,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(120,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(124,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(128,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(132,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(136,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(140,
IEEE80211_CHAN_RADAR | IEEE80211_CHAN_NO_HT40PLUS |
IEEE80211_CHAN_NO_HT40MINUS),
/* UNII-3 */
CHAN5G(149, IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(153, IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(157, IEEE80211_CHAN_NO_HT40MINUS),
CHAN5G(161, IEEE80211_CHAN_NO_HT40PLUS),
CHAN5G(165, IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS)
};
static struct ieee80211_supported_band realtek_band_2ghz = {
.band = NL80211_BAND_2GHZ,
.n_channels = ARRAY_SIZE(realtek_2ghz_channels),
.channels = realtek_2ghz_channels,
.n_bitrates = realtek_g_rates_size,
.bitrates = realtek_g_rates,
.ht_cap = {
.cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40,
.ht_supported = true,
.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
.ampdu_density = 7,
.mcs = {
.rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
.rx_highest = cpu_to_le16(300),
.tx_params = IEEE80211_HT_MCS_TX_DEFINED
}
}
};
static struct ieee80211_supported_band realtek_band_5ghz = {
.band = NL80211_BAND_5GHZ,
.n_channels = ARRAY_SIZE(realtek_5ghz_a_channels),
.channels = realtek_5ghz_a_channels,
.n_bitrates = realtek_a_rates_size,
.bitrates = realtek_a_rates,
.ht_cap = {
.cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
IEEE80211_HT_CAP_TX_STBC | IEEE80211_HT_CAP_RX_STBC,
.ht_supported = true,
.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K,
.ampdu_density = 7,
.mcs = {
.rx_mask = {0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0},
.rx_highest = cpu_to_le16(300),
.tx_params = IEEE80211_HT_MCS_TX_DEFINED
}
},
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)
.vht_cap = {
.vht_supported = true,
.cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 | IEEE80211_VHT_CAP_SHORT_GI_80 |
IEEE80211_VHT_CAP_TXSTBC | IEEE80211_VHT_CAP_RXSTBC_1 |
#ifdef BEAMFORMING_SUPPORT
IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
(1 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT) | (1 << IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT) |
#endif
IEEE80211_VHT_CAP_HTC_VHT | (7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT),
.vht_mcs = {
.rx_mcs_map = cpu_to_le16(0xfffa),
.tx_mcs_map = cpu_to_le16(0xfffa),
.rx_highest = cpu_to_le16(780),
.tx_highest = cpu_to_le16(780),
}
}
#endif
};
struct rtk_clnt_info {
struct wpa_ie_info wpa_ie;
struct rsn_ie_info rsn_ie;
unsigned char assoc_req[MAX_ASSOC_REQ_LEN];
unsigned short assoc_req_len;
unsigned char assoc_rsp[MAX_ASSOC_RSP_LEN];
unsigned short assoc_rsp_len;
};
struct rtk_iface_info {
unsigned char used;
unsigned char ndev_name[32];
struct rtl8192cd_priv *priv;
};
struct survey_info_t {
unsigned int channel;
unsigned int chbusytime;
unsigned int rx_time;
unsigned int tx_time;
s8 noise;
};
struct rtknl {
struct class *cl;
struct device *dev;
struct wiphy *wiphy;
struct rtl8192cd_priv *priv;
struct net_device *ndev_add;
struct rtk_clnt_info clnt_info;
unsigned char num_vif;
int idx_vif;
unsigned char num_vap;
unsigned char num_vxd;
unsigned int vif_flag;
unsigned char wiphy_registered;
unsigned int cipher;
unsigned int wpa;
unsigned int psk;
unsigned int sha256;
unsigned char ndev_name[VIF_NUM][VIF_NAME_SIZE];
unsigned char ndev_name_vxd[VIF_NAME_SIZE];
unsigned char root_ifname[VIF_NAME_SIZE];
unsigned char root_mac[ETH_ALEN];
unsigned char vap_mac[VIF_NUM][ETH_ALEN];
struct rtl8192cd_priv *priv_root;
struct rtl8192cd_priv *priv_vxd;
struct rtk_iface_info rtk_iface[VIF_NUM+2];
//for survey_dump
struct survey_info_t survey_info[ARRAY_SIZE(realtek_5ghz_a_channels)];
/* By brian, to support per channel statistic
unsigned int chbusytime;
unsigned int rx_time;
unsigned int tx_time;
*/
//openwrt_psd
unsigned int psd_chnl;
unsigned int psd_bw;
unsigned int psd_pts;
unsigned int psd_fft_info[1040];
//openwrt_tx_power_use
unsigned int pwr_rate;
int pwr_cur;
int pwr_set_dbm;
unsigned char keep_legacy;
};
/* HT Capabilities Info field within HT Capabilities element */
#define HT_CAP_INFO_SHORT_GI20MHZ ((u16) BIT(5))
#define HT_CAP_INFO_SHORT_GI40MHZ ((u16) BIT(6))
/* VHT Defines */
#define VHT_CAP_SHORT_GI_80 ((u32) BIT(5))
#if defined(VAP_MAC_DRV_READ_FLASH)
int read_flash_hw_mac_vap( unsigned char *mac, int vap_idx);
#endif
unsigned char is_WRT_scan_iface(const char* if_name); //eric-vap
void realtek_cfg80211_inform_ss_result(struct rtl8192cd_priv *priv);
struct rtknl *realtek_cfg80211_create(void);
int realtek_rtknl_init(struct rtknl *rtk);
int realtek_cfg80211_init(struct rtknl *rtk,struct rtl8192cd_priv *priv);
int realtek_interface_add(struct rtl8192cd_priv *priv, struct rtknl *rtk, const char *name,
enum nl80211_iftype type, u8 fw_vif_idx, u8 nw_type);
int realtek_cfg80211_deinit(struct rtl8192cd_priv *priv, struct rtknl *rtk);
int realtek_interface_del(struct rtl8192cd_priv *priv, struct rtknl *rtk, struct net_device *ndev);
int realtek_cfg80211_destroy(struct rtknl *rtk);
int event_indicate_cfg80211(struct rtl8192cd_priv *priv, unsigned char *mac, int event, void *extra);
void close_vxd_vap(struct rtl8192cd_priv *priv_root);
int check_5M10M_config(struct rtl8192cd_priv *priv);
void realtek_change_iftype(struct rtl8192cd_priv *priv ,enum nl80211_iftype type);
void rtk_cfg80211_rx_mgmt(struct rtl8192cd_priv *priv , struct rx_frinfo *pfrinfo, unsigned char channel);
#ifdef RTK_NL80211_HS_CLI
void realtek_cfg80211_RemainOnChExpire(unsigned long task_priv);
#endif
#endif /* RTK_NL80211 */
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_comapi.c
Executable
+3994
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File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_comapi.h
Executable
+113
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@@ -0,0 +1,113 @@
/*
* Header file for API-compatible handling routines
*
*
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_COMAPI_H_
#define _8192CD_COMAPI_H_
#include "./8192cd.h"
typedef struct rtl8192cd_priv RTL_PRIV;
#define MAX_CONFIG_FILE_SIZE (64*1024) // for 8192, added to 64k
#define MAX_PARAM_BUF_SIZE (1024) // for 8192, added to 20k
#ifdef CONFIG_RTL_COMAPI_CFGFILE
/* Following is a example for PARAMETERs completely compatible to other vendors'
* configure file - chris 2010/02/01 */
#undef VENDOR_PARAM_COMPATIBLE
#ifdef VENDOR_PARAM_COMPATIBLE
int Set_CountryRegion_Proc (RTL_PRIV *priv, char *arg);
int Set_CountryRegionABand_Proc (RTL_PRIV *priv, char *arg);
int Set_SSID_Proc (RTL_PRIV *priv, char *arg);
struct mib_cfg_func{
char name[20]; /*mib name*/
int (*set_proc)(RTL_PRIV *priv, char *arg);
};
static struct mib_cfg_func *TMP_MIBCFG, RTL_SUPPORT_MIBCFG[] = {
{"CountryRegion", Set_CountryRegion_Proc},
{"CountryRegionABand", Set_CountryRegionABand_Proc},
{"SSID", Set_SSID_Proc}
};
int Set_CountryRegion_Proc(RTL_PRIV *priv, char *arg)
{
int val = simple_strtol(arg, 0 ,10);
if (DOMAIN_FCC <= val && val <= DOMAIN_MAX ) {
priv->pmib->dot11StationConfigEntry.dot11RegDomain = val;
return TRUE;
} else {
printk("contry region out of range [%d-%d]\n", DOMAIN_FCC, DOMAIN_MAX);
return FALSE;
}
}
int Set_CountryRegionABand_Proc(RTL_PRIV *priv, char *arg)
{
int val = simple_strtol(arg, 0 ,10);
priv->pmib->dot11StationConfigEntry.dot11RegDomainABand = val;
return TRUE;
}
int Set_SSID_Proc(RTL_PRIV *priv, char *arg)
{
strcpy(priv->pmib->dot11StationConfigEntry.dot11DesiredSSID, arg);
return TRUE;
}
#else
extern int set_mib(struct rtl8192cd_priv *priv, unsigned char *data);
#endif //VENDOR_PARAM_COMPATIBLE
#endif //CONFIG_RTL_COMAPI_CFGFILE
#ifdef WIFI_WPAS_CLI
#define WPA_IE_ID 0xdd
#define WPA2_IE_ID 0x30
#define RSN_HEADER_LEN 4
#define WPA_SELECTOR_LEN 4
#define RSN_SELECTOR_LEN 4
#define VENDOR_SPECIFIC_IE 221
#ifdef CONFIG_RTL_WAPI_SUPPORT
#ifndef IW_AUTH_WAPI_VERSION_1
#define IW_AUTH_WAPI_VERSION_1 0x00000008
#endif
#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK
#define IW_AUTH_KEY_MGMT_WAPI_PSK 0x04
#endif
#ifndef IW_AUTH_KEY_MGMT_WAPI_CERT
#define IW_AUTH_KEY_MGMT_WAPI_CERT 0x08
#endif
#ifndef IW_AUTH_WAPI_ENABLED
#define IW_AUTH_WAPI_ENABLED 0x20
#endif
#ifndef IW_ENCODE_ALG_SM4
#define IW_ENCODE_ALG_SM4 0x20
#endif
#endif // CONFIG_RTL_WAPI_SUPPORT
#endif // WIFI_WPAS_CLI
#endif // _8192CD_COMAPI_H_
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_debug.h
Executable
+386
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@@ -0,0 +1,386 @@
/*
* Debug headler file. It defines various print out method
*
* $Id: 8192cd_debug.h,v 1.2.4.2 2010/12/01 13:38:00 button Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_DEBUG_H_
#define _8192CD_DEBUG_H_
#if 1
//#define _MESH_MOD_
#define printMac(da) printk("%02X:%02X:%02X:%02X:%02X:%02X\n", 0xff&*(da), 0xff&*(da+1), 0xff&*(da+2), 0xff&*(da+3), 0xff&*(da+4), 0xff&*(da+5));
#define printMac4(pframe) {\
printMac(GetAddr1Ptr(pframe));\
printMac(GetAddr2Ptr(pframe));\
printMac(GetAddr3Ptr(pframe));\
printMac(GetAddr4Ptr(pframe));\
}
#define printHex(d,n) {int i; \
for(i=0; i<n; i++) { printk("%02X:", *(d+i)); \
if( i%40==39) printk("\n "); \
} }
#endif
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
/*
* Compact form for string representation of MAC address
* To be used, e.g., for constructing dbus paths for P2P Devices
*/
#define COMPACT_MACSTR "%02x%02x%02x%02x%02x%02x"
#endif
#ifdef _DEBUG_RTL8192CD_
extern unsigned long rtl8192cd_debug_err; /* err flag */
extern unsigned long rtl8192cd_debug_info; /* info flag */
extern unsigned long rtl8192cd_debug_trace; /* trace flag */
extern unsigned long rtl8192cd_debug_warn; /* warn flag */
/* Bit definition for bit31-bit8 of rtl8190_debug */
enum _module_define_ {
_OSDEP_ = 0x00000001,
_SME_ = 0x00000002,
_IOCTL_ = 0x00000004,
_TX_ = 0x00000008,
_RX_ = 0x00000010,
_HW_ = 0x00000020,
_SECURITY_ = 0x00000040,
_UTIL_ = 0x00000080,
_TKIP_ = 0x00000100,
_AES_ = 0x00000200,
_HOST_ = 0x00000400,
_BR_EXT_ = 0x00000800,
_EEPROM_ = 0x00001000,
_PSK_ = 0x00002000,
_MP_ = 0x00004000,
_MIB_ = 0x00008000,
_LED_ = 0x00010000,
_WPS_ = 0x00020000,
_DHW_ = 0x00040000,
_HAL_ = 0x00080000,
_DM_ = 0x00100000,
_88E_HW_ = 0x00200000,
_DFS_ = 0x00400000,
_OTHER_ = 0x00800000,
_MESH_SME_ = 0x02000000,
_MESH_SECURITY_ = 0x04000000,
_MESH_TX_ = 0x08000000,
_MESH_RX_ = 0x10000000,
_MESH_UTIL_ = 0x20000000,
#ifdef CONFIG_POWER_SAVE
_PWR_CTRL_ = 0x40000000,
#else
_MESH_ROUTE_ = 0x40000000,
#endif
_DM_COM_ = 0x80000000,
};
#if defined(_8192CD_OSDEP_C_)
#define _MODULE_DEFINE _OSDEP_
#define _MODULE_NAME "osdep"
#elif defined(_8192CD_SME_C_)
#define _MODULE_DEFINE _SME_
#define _MODULE_NAME "sme"
#elif defined(_8192CD_IOCTL_C_)
#define _MODULE_DEFINE _IOCTL_
#define _MODULE_NAME "ioctl"
#elif defined(_8192CD_PROC_C_)
#define _MODULE_DEFINE _PROC_
#define _MODULE_NAME "proc"
#elif defined(_8192CD_TX_C_)
#define _MODULE_DEFINE _TX_
#define _MODULE_NAME "tx"
#elif defined(_8192CD_RX_C_)
#define _MODULE_DEFINE _RX_
#define _MODULE_NAME "rx"
#elif defined(_8192CD_HW_C_)
#define _MODULE_DEFINE _HW_
#define _MODULE_NAME "hw"
#elif defined(_8192D_HW_C_)
#define _MODULE_DEFINE _DHW_
#define _MODULE_NAME "dhw"
#elif defined(_8192CD_SECURITY_C_)
#define _MODULE_DEFINE _SECURITY_
#define _MODULE_NAME "security"
#elif defined(_8192CD_UTILS_C_)
#define _MODULE_DEFINE _UTIL_
#define _MODULE_NAME "util"
#elif defined(_8192CD_TKIP_C_)
#define _MODULE_DEFINE _TKIP_
#define _MODULE_NAME "tkip"
#elif defined(_8192CD_AES_C_)
#define _MODULE_DEFINE _AES_
#define _MODULE_NAME "aes"
#elif defined(_8192CD_BR_EXT_C_)
#define _MODULE_DEFINE _BR_EXT_
#define _MODULE_NAME "br_ext"
#elif defined(_8192CD_EEPROM_C_)
#define _MODULE_DEFINE _EEPROM_
#define _MODULE_NAME "eeprom"
#elif defined(_8192CD_PSK_C_)
#define _MODULE_DEFINE _PSK_
#define _MODULE_NAME "psk"
#elif defined(_8192CD_MP_C_)
#define _MODULE_DEFINE _MP_
#define _MODULE_NAME "mp"
#elif defined(_8192CD_MIB_C_)
#define _MODULE_DEFINE _MIB_
#define _MODULE_NAME "mib"
#elif defined(_8192CD_DMEM_C_)
//not yet
#elif defined(_HAL8192CDM_C_)
#define _MODULE_DEFINE _HAL_
#define _MODULE_NAME "hal"
#elif defined(_8192CD_A4_STA_C_)
#define _MODULE_DEFINE _A4STA_
#define _MODULE_NAME "a4_sta"
#elif defined(_8192CD_WSCD_C_)
#define _MODULE_DEFINE _WPS_
#define _MODULE_NAME "wps"
#elif defined(_MESH_SME_C_)
#define _MODULE_DEFINE _MESH_SME_
#define _MODULE_NAME "mesh_sme"
#elif defined(_MESH_TX_C_)
#define _MODULE_DEFINE _MESH_TX_
#define _MODULE_NAME "mesh_tx"
#elif defined(_MESH_RX_C_)
#define _MODULE_DEFINE _MESH_RX_
#define _MODULE_NAME "mehs_rx"
#elif defined(_MESH_SECURITY_C_)
#define _MODULE_DEFINE _MESH_SECURITY_
#define _MODULE_NAME "mesh_secutiry"
#elif defined(_MESH_UTILS_C_)
#define _MODULE_DEFINE _MESH_UTIL_
#define _MODULE_NAME "mesh_util"
#elif defined(_MESH_ROUTE_C_)
#define _MODULE_DEFINE _MESH_ROUTE_
#define _MODULE_NAME "mesh_route"
#elif defined(_8192CD_PWRCTRL_C_)
#define _MODULE_DEFINE _PWR_CTRL_
#define _MODULE_NAME "pwr_ctrl"
#elif defined(_MESH_PROC_C_)
#define _MODULE_DEFINE _MESH_PROC_
#define _MODULE_NAME "mesh_proc"
#elif defined(_MESH_11KV_C_)
//not yet
#elif defined(_HAL8192CDM_C_)
#define _MODULE_DEFINE _DM_
#define _MODULE_NAME "DM"
#elif defined(_8188E_HW_C_)
#define _MODULE_DEFINE _88E_HW_
#define _MODULE_NAME "88E_hw"
#elif defined(_HALDM_COMMON_C_)
#define _MODULE_DEFINE _DM_COM_
#define _MODULE_NAME "DM_COM"
#elif defined(_8812_HW_C_)
#define _MODULE_DEFINE _OTHER_
#define _MODULE_NAME "8812_hw"
#elif defined(_8192CD_HOST_C_)
#define _MODULE_DEFINE _HOST_
#define _MODULE_NAME "host"
#elif defined(_8192CD_LED_C_)
#define _MODULE_DEFINE _LED_
#define _MODULE_NAME "led"
#elif defined(_8192CD_DFS_C_)
#define _MODULE_DEFINE _DFS_
#define _MODULE_NAME "dfs"
#else
#define _MODULE_DEFINE _OTHER_
#define _MODULE_NAME "other"
#endif
/* Macro for DEBUG_ERR(), DEBUG_TRACE(), DEBUG_WARN(), DEBUG_INFO() */
#ifdef __GNUC__
#ifdef CONFIG_RTL8671
#define DEBUG_ERR printk
#define DEBUG_TRACE printk
#define DEBUG_INFO printk
#define DEBUG_WARN printk
#define _DEBUG_ERR printk
#define _DEBUG_INFO printk
#define DBFENTER
#define DBFEXIT
#define PRINT_INFO printk
#else
#define __DEBUG_ERR(name, fmt, args...) \
if (rtl8192cd_debug_err&_MODULE_DEFINE) \
printk("%s-"_MODULE_NAME"-err: " fmt, name, ## args);
#define __DEBUG_TRACE(name) \
if (rtl8192cd_debug_trace&_MODULE_DEFINE) \
printk("%s-"_MODULE_NAME"-trace: %s----->\n", name, (char *)__FUNCTION__);
#define __DEBUG_INFO(name, fmt, args...) \
if (rtl8192cd_debug_info&_MODULE_DEFINE) \
printk("%s-"_MODULE_NAME"-info: " fmt, name, ## args);
#define __DEBUG_WARN(name, fmt, args...) \
if (rtl8192cd_debug_warn&_MODULE_DEFINE) \
printk("%s-"_MODULE_NAME"-warn: " fmt, name, ## args);
#define DEBUG_ERR(fmt, args...) __DEBUG_ERR(priv->dev->name, fmt, ## args)
#define DEBUG_INFO(fmt, args...) __DEBUG_INFO(priv->dev->name, fmt, ## args)
#define DEBUG_TRACE __DEBUG_TRACE(priv->dev->name)
#define DEBUG_WARN(fmt, args...) __DEBUG_WARN(priv->dev->name, fmt, ## args)
#define _DEBUG_ERR(fmt, args...) __DEBUG_ERR("wlan", fmt, ## args)
#define _DEBUG_INFO(fmt, args...) __DEBUG_INFO("wlan", fmt, ## args)
#define _DEBUG_TRACE __DEBUG_TRACE("wlan")
#define _DEBUG_WARN(fmt, args...) __DEBUG_WARN("wlan", fmt, ## args)
#define DBFENTER printk("----->%s\n", (char *)__FUNCTION__)
#define DBFEXIT printk("%s----->\n", (char *)__FUNCTION__)
#define PRINT_INFO(fmt, args...) printk(fmt, ## args)
#endif
#endif // __GNUC__
/*
#ifdef __DRAYTEK_OS__
#define __FUNCTION__ ""
#define DEBUG_ERR Print
#define DEBUG_INFO Print
#define DEBUG_TRACE
#define DEBUG_WARN Print
#define _DEBUG_ERR DEBUG_ERR
#define _DEBUG_INFO DEBUG_INFO
#define _DEBUG_TRACE DEBUG_TRACE
#define _DEBUG_WARN DEBUG_WARN
#define DBFENTER
#define DBFEXIT
#define PRINT_INFO Print
#endif // __DRAYTEK_OS__
#ifdef GREEN_HILL
#define DEBUG_ERR printk
#define DEBUG_INFO printk
#define DEBUG_TRACE printk
#define DEBUG_WARN printk
#define _DEBUG_ERR printk
#define _DEBUG_INFO printk
#define _DEBUG_TRACE printk
#define _DEBUG_WARN printk
#define DBFENTER printk
#define DBFEXIT printk
#define PRINT_INFO printk
#endif // GREEN_HILL
*/
#else // not _DEBUG_RTL8192CD_
#ifdef __GNUC__
#define DEBUG_ERR(fmt, args...) {}
#define DEBUG_INFO(fmt, args...) {}
#define DEBUG_TRACE {}
#define DEBUG_WARN(fmt, args...) {}
#define _DEBUG_ERR(fmt, args...) {}
#define _DEBUG_INFO(fmt, args...) {}
#define _DEBUG_TRACE {}
#define _DEBUG_WARN(fmt, args...) {}
#define DBFENTER {}
#define DBFEXIT {}
#define PRINT_INFO(fmt, args...) {}
#endif // __GNUC__
/*
#ifdef __DRAYTEK_OS__
#define __FUNCTION__ ""
#define DEBUG_ERR
#define DEBUG_INFO
#define DEBUG_TRACE
#define DEBUG_WARN
#define _DEBUG_ERR
#define _DEBUG_INFO
#define _DEBUG_TRACE
#define _DEBUG_WARN
#define DBFENTER
#define DBFEXIT
#define PRINT_INFO
#endif // __DRAYTEK_OS__
#ifdef GREEN_HILL
#define DEBUG_ERR(fmt, args...) {}
#define DEBUG_INFO(fmt, args...) {}
#define DEBUG_TRACE {}
#define DEBUG_WARN(fmt, args...) {}
#define _DEBUG_ERR(fmt, args...) {}
#define _DEBUG_INFO(fmt, args...) {}
#define _DEBUG_TRACE {}
#define _DEBUG_WARN(fmt, args...) {}
#define DBFENTER {}
#define DBFEXIT {}
#define PRINT_INFO(fmt, args...) {}
#endif // GREEN_HILL
*/
#endif // _DEBUG_RTL8192CD_
#endif // _8192CD_DEBUG_H_
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_dfs.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_dfs_det.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_dmem.c
Executable
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/*
* D-MEM supporting module for RTL8190 802.11N wireless NIC on RTL865x platform
*
* $Id: 8192cd_dmem.c,v 1.2 2010/01/19 06:04:03 jimmylin Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifdef __ECOS
#include <cyg/io/eth/rltk/819x/wrapper/sys_support.h>
#include <cyg/io/eth/rltk/819x/wrapper/skbuff.h>
#include <cyg/io/eth/rltk/819x/wrapper/timer.h>
#include <cyg/io/eth/rltk/819x/wrapper/wrapper.h>
#endif
#ifndef _8192CD_DMEM_C_
#define _8192CD_DMEM_C_
#include "./8192cd.h"
//#include "./8190n_fastExtDev.h"
#include "./8192cd_cfg.h"
#ifdef RTL8192CD_VARIABLE_USED_DMEM
#include "./8192cd_dmem.h"
#define RTL8192CD_MAX_SPEEDUP_STA 2
#define RTL8192CD_SPEEDUP_PRIV_COUNT 1
/* ========================== All variables using D-MEM ========================== */
static void rtl8192cd_dmem_AID_OBJ_init(void);
static void *rtl8192cd_dmem_AID_OBJ_alloc(void *miscInfo);
static void rtl8192cd_dmem_AID_OBJ_free(void *miscInfo);
static void rtl8192cd_dmem_pmib_init(void);
static void *rtl8192cd_dmem_pmib_alloc(void *miscInfo);
static void rtl8192cd_dmem_pmib_free(void *miscInfo);
#ifdef PRIV_STA_BUF
extern struct aid_obj *alloc_sta_obj(struct rtl8192cd_priv*);
extern void free_sta_obj(struct rtl8192cd_priv *priv, struct aid_obj *obj);
#endif
static _rtl8192cd_dmem_callBack_t _8192cd_dmem_callBack_list[] =
{
/* ID Init CallBack Allocate CallBack Free CallBack */
{ AID_OBJ, rtl8192cd_dmem_AID_OBJ_init, rtl8192cd_dmem_AID_OBJ_alloc, rtl8192cd_dmem_AID_OBJ_free},
{ PMIB, rtl8192cd_dmem_pmib_init, rtl8192cd_dmem_pmib_alloc, rtl8192cd_dmem_pmib_free},
/* ==================================================================== */
{ _RTL8192CD_DMEM_ITEM_MAX, NULL, NULL},
};
/* ========================== External APIs of D-MEM module ========================== */
/*
Initiation function for DMEM library
*/
void rtl8192cd_dmem_init( void )
{
_rtl8192cd_dmem_callBack_t *ptr;
ptr = &_8192cd_dmem_callBack_list[0];
while ( (ptr->id > _RTL8192CD_DMEM_ITEM_MIN) &&
(ptr->id < _RTL8192CD_DMEM_ITEM_MAX))
{
/* Call the Callback function to decide the memory of allocated */
if (ptr->initCallBackFunc)
{
((_dummyFunc_void_void)(ptr->initCallBackFunc))();
}
/* Next Entry */
ptr ++;
}
}
void *rtl8192cd_dmem_alloc( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo )
{
void *retval;
_rtl8192cd_dmem_callBack_t *ptr;
retval = NULL;
if ( (id <= _RTL8192CD_DMEM_ITEM_MIN) ||
(id >= _RTL8192CD_DMEM_ITEM_MAX))
{
printk("%s %d : ERROR (%d)\n", __FUNCTION__, __LINE__, id);
goto out;
}
ptr = &_8192cd_dmem_callBack_list[0];
while ( ptr->allcateCallBackFunc )
{
if ( ptr->id == id )
{
/* Call the Callback function to decide the memory of allocated */
retval = ((_dummyFunc_voidStar_voidStar)(ptr->allcateCallBackFunc))(miscInfo);
goto out;
}
/* Next Entry */
ptr ++;
}
out:
return retval;
}
void rtl8192cd_dmem_free( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo )
{
_rtl8192cd_dmem_callBack_t *ptr;
if ( (id <= _RTL8192CD_DMEM_ITEM_MIN) ||
(id >= _RTL8192CD_DMEM_ITEM_MAX))
{
printk("%s %d : ERROR (%d)\n", __FUNCTION__, __LINE__, id);
goto out;
}
ptr = &_8192cd_dmem_callBack_list[0];
while ( ptr->freeCallBackFunc )
{
if ( ptr->id == id )
{
/* Call the Callback function to decide the memory of allocated */
((_dummyFunc_void_voidStar)(ptr->freeCallBackFunc))(miscInfo);
goto out;
}
/* Next Entry */
ptr ++;
}
out:
return;
}
/* ========================== Internal APIs for per-variable of D-MEM module ========================== */
/* ==============================================
*
* AID_OBJ
*
*
* ============================================== */
__DRAM_IN_865X struct aid_obj _rtl8192cd_aid_Array[RTL8192CD_MAX_SPEEDUP_STA];
void *_rtl8192cd_aid_externalMem_Array[NUM_STAT];
static void rtl8192cd_dmem_AID_OBJ_init(void)
{
memset(_rtl8192cd_aid_Array, 0, sizeof(struct aid_obj) * RTL8192CD_MAX_SPEEDUP_STA);
memset(_rtl8192cd_aid_externalMem_Array, 0, sizeof(_rtl8192cd_aid_externalMem_Array));
}
static void *rtl8192cd_dmem_AID_OBJ_alloc(void *miscInfo)
{
/* For AID_OBJ : miscInfo would be [unsigned int *] to decision the index of aidarray to allocate */
unsigned int index = *((unsigned int*)miscInfo);
if ( (index < 0) ||
(index >= NUM_STAT))
{
printk("%s %d : ERROR ( Index : %d )\n", __FUNCTION__, __LINE__, index);
return NULL;
}
/* Allocate from external memory */
if ( index >= RTL8192CD_MAX_SPEEDUP_STA )
{
#ifdef PRIV_STA_BUF
_rtl8192cd_aid_externalMem_Array[index] = alloc_sta_obj(NULL);
#else
_rtl8192cd_aid_externalMem_Array[index] = kmalloc(sizeof(struct aid_obj), GFP_ATOMIC);
#endif
if (_rtl8192cd_aid_externalMem_Array[index] == NULL)
{
printk("%s %d : Error : Allocation FAILED!\n", __FUNCTION__, __LINE__);
return NULL;
}
return _rtl8192cd_aid_externalMem_Array[index];
}
memset(&(_rtl8192cd_aid_Array[index]), 0, sizeof(struct aid_obj));
return (void*)(&(_rtl8192cd_aid_Array[index]));
}
static void rtl8192cd_dmem_AID_OBJ_free(void *miscInfo)
{
/* For AID_OBJ : miscInfo would be [unsigned int *] to decision the index of aidarray to free */
unsigned int index = *((unsigned int*)miscInfo);
if ( (index < 0) ||
(index >= NUM_STAT))
{
printk("%s %d : ERROR ( Index : %d )\n", __FUNCTION__, __LINE__, index);
return;
}
/* Free memory to external memory module */
if ( index >= RTL8192CD_MAX_SPEEDUP_STA )
{
if ( _rtl8192cd_aid_externalMem_Array[index] )
{
#ifdef PRIV_STA_BUF
free_sta_obj(NULL, _rtl8192cd_aid_externalMem_Array[index]);
#else
kfree(_rtl8192cd_aid_externalMem_Array[index]);
#endif
_rtl8192cd_aid_externalMem_Array[index] = NULL;
}
return;
}
memset(&(_rtl8192cd_aid_Array[index]), 0, sizeof(struct aid_obj));
}
/* =================== The following variable are mapped to PRIV =================== */
/* ==============================================
*
* PMIB
*
*
* ============================================== */
__DRAM_IN_865X struct wifi_mib _rtl8192cd_pmib[RTL8192CD_SPEEDUP_PRIV_COUNT];
int _rtl8192cd_pmib_usageMap[RTL8192CD_SPEEDUP_PRIV_COUNT];
static void rtl8192cd_dmem_pmib_init(void)
{
memset(_rtl8192cd_pmib_usageMap, 0, sizeof(int) * RTL8192CD_SPEEDUP_PRIV_COUNT);
memset(_rtl8192cd_pmib, 0, sizeof(struct wifi_mib) * RTL8192CD_SPEEDUP_PRIV_COUNT);
}
static void *rtl8192cd_dmem_pmib_alloc(void *miscInfo)
{
int idx ;
/* miscInfo is useless */
for ( idx = 0 ; idx < RTL8192CD_SPEEDUP_PRIV_COUNT ; idx ++ )
{
if ( _rtl8192cd_pmib_usageMap[idx] == 0 )
{ /* Unused entry : use it */
_rtl8192cd_pmib_usageMap[idx] = 1;
memset(&(_rtl8192cd_pmib[idx]), 0, sizeof(struct wifi_mib));
return &(_rtl8192cd_pmib[idx]);
}
}
/* Allocate from externel memory if speedup PMIB is exhausted */
return kmalloc(sizeof(struct wifi_mib), GFP_ATOMIC);
}
static void rtl8192cd_dmem_pmib_free(void *miscInfo)
{
int idx;
/* miscInfo is pointed to the address of PMIB to free */
/* Free PMIB if it is speeded up by DMEM */
for ( idx = 0 ; idx < RTL8192CD_SPEEDUP_PRIV_COUNT ; idx ++ )
{
if ( (unsigned long)(&(_rtl8192cd_pmib[idx])) == (unsigned long)miscInfo )
{ /* Entry is found : free it */
memset(&(_rtl8192cd_pmib[idx]), 0, sizeof(struct wifi_mib));
_rtl8192cd_pmib_usageMap[idx] = 0;
return;
}
}
/* It would be allocated from external memory: kfree it */
kfree(miscInfo);
}
#endif // RTL8192CD_VARIABLE_USED_DMEM
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_dmem.h
Executable
+44
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/*
* Header of D-MEM supporting module for RTL8190 802.11N wireless NIC on RTL865x platform
*
* $Id: 8192cd_dmem.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_DMEM_H
#define _8192CD_DMEM_H
/* ========================= External ========================= */
enum _RTL8192CD_DMEM_ITEM_ID {
_RTL8192CD_DMEM_ITEM_MIN,
/* ============================== Add here ============================== */
AID_OBJ,
PMIB,
/* =================================================================== */
_RTL8192CD_DMEM_ITEM_MAX,
};
void rtl8192cd_dmem_init( void );
void *rtl8192cd_dmem_alloc( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo );
void rtl8192cd_dmem_free( enum _RTL8192CD_DMEM_ITEM_ID id, void *miscInfo );
/* ========================= Internal ========================= */
typedef void* (*_dummyFunc_voidStar_voidStar)(void*);
typedef void (*_dummyFunc_void_voidStar)(void*);
typedef void (*_dummyFunc_void_void)(void);
typedef struct _rtl8192cd_dmem_list_s
{
int id;
void * initCallBackFunc;
void * allcateCallBackFunc;
void * freeCallBackFunc;
} _rtl8192cd_dmem_callBack_t;
#endif /* _8192CD_DMEM_H */
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_eeprom.c
Executable
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/*
* Routines to read and write eeprom
*
* $Id: 8192cd_eeprom.c,v 1.1 2009/11/06 12:26:48 victoryman Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define _8192CD_EEPROM_C_
#if 0
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/module.h>
#endif
#include "./8192cd_cfg.h"
#include "./8192cd.h"
#include "./8192cd_hw.h"
#include "./8192cd_util.h"
#include "./8192cd_debug.h"
#define VOID void
#define EEPROM_MAX_SIZE 256
#define CSR_EEPROM_CONTROL_REG _9346CR_
#define CLOCK_RATE 50 //100us
static VOID ShiftOutBits(struct rtl8192cd_priv *priv, USHORT data, USHORT count);
static USHORT ShiftInBits(struct rtl8192cd_priv *priv);
static VOID RaiseClock(struct rtl8192cd_priv *priv, USHORT *x);
static VOID LowerClock(struct rtl8192cd_priv *priv, USHORT *x);
static VOID EEpromCleanup(struct rtl8192cd_priv *priv);
static USHORT WaitEEPROMCmdDone(struct rtl8192cd_priv *priv);
static VOID StandBy(struct rtl8192cd_priv *priv);
//*****************************************************************************
//
// I/O based Read EEPROM Routines
//
//*****************************************************************************
//-----------------------------------------------------------------------------
// Procedure: ReadEEprom
//
// Description: This routine serially reads one word out of the EEPROM.
//
// Arguments:
// Reg - EEPROM word to read.
//
// Returns:
// Contents of EEPROM word (Reg).
//-----------------------------------------------------------------------------
static USHORT
ReadEEprom(
struct rtl8192cd_priv *priv,
UCHAR AddressSize,
USHORT Reg)
{
USHORT x;
USHORT data;
// select EEPROM, reset bits, set EECS
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDI | EEDO | EESK | CR9346_EEM0);
x |= CR9346_EEM1 | EECS;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 6 bits long
ShiftOutBits(priv, EEPROM_READ_OPCODE, 3);
ShiftOutBits(priv, Reg, AddressSize);
// Now read the data (16 bits) in from the selected EEPROM word
data = ShiftInBits(priv);
EEpromCleanup(priv);
return data;
}
//-----------------------------------------------------------------------------
// Procedure: ShiftOutBits
//
// Description: This routine shifts data bits out to the EEPROM.
//
// Arguments:
// data - data to send to the EEPROM.
// count - number of data bits to shift out.
//
// Returns: (none)
//-----------------------------------------------------------------------------
static VOID
ShiftOutBits(
struct rtl8192cd_priv *priv,
USHORT data,
USHORT count)
{
USHORT x,mask;
mask = 0x01 << (count - 1);
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDO | EEDI);
do
{
x &= ~EEDI;
if(data & mask)
x |= EEDI;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
delay_us(CLOCK_RATE);
RaiseClock(priv, &x);
LowerClock(priv, &x);
mask = mask >> 1;
} while(mask);
x &= ~EEDI;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
}
//-----------------------------------------------------------------------------
// Procedure: ShiftInBits
//
// Description: This routine shifts data bits in from the EEPROM.
//
// Arguments:
//
// Returns:
// The contents of that particular EEPROM word
//-----------------------------------------------------------------------------
static USHORT
ShiftInBits(
struct rtl8192cd_priv *priv)
{
USHORT x,d,i;
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~( EEDO | EEDI);
d = 0;
for(i=0; i<16; i++)
{
d = d << 1;
RaiseClock(priv, &x);
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDI);
if(x & EEDO)
d |= 1;
LowerClock(priv, &x);
}
return d;
}
//-----------------------------------------------------------------------------
// Procedure: RaiseClock
//
// Description: This routine raises the EEPOM's clock input (EESK)
//
// Arguments:
// x - Ptr to the EEPROM control register's current value
//
// Returns: (none)
//-----------------------------------------------------------------------------
static VOID
RaiseClock(
struct rtl8192cd_priv *priv,
USHORT *x)
{
*x = *x | EESK;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)(*x));
delay_us(CLOCK_RATE);
}
//-----------------------------------------------------------------------------
// Procedure: LowerClock
//
// Description: This routine lower's the EEPOM's clock input (EESK)
//
// Arguments:
// x - Ptr to the EEPROM control register's current value
//
// Returns: (none)
//-----------------------------------------------------------------------------
static VOID
LowerClock(
struct rtl8192cd_priv *priv,
USHORT *x)
{
*x = *x & ~EESK;
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)(*x));
delay_us(CLOCK_RATE);
}
//-----------------------------------------------------------------------------
// Procedure: EEpromCleanup
//
// Description: This routine returns the EEPROM to an idle state
//
// Arguments:
//
// Returns: (none)
//-----------------------------------------------------------------------------
static VOID
EEpromCleanup(
struct rtl8192cd_priv *priv)
{
USHORT x;
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EECS | EEDI);
RTL_W8(CSR_EEPROM_CONTROL_REG, (UCHAR)x);
RaiseClock(priv, &x);
LowerClock(priv, &x);
}
//*****************************************************************************
//
// EEPROM Write Routines
//
//*****************************************************************************
//-----------------------------------------------------------------------------
// Procedure: D100UpdateChecksum
//
// Description: Calculates the checksum and writes it to the EEProm. This
// routine assumes that the checksum word is the last word in
// a 64 word EEPROM. It calculates the checksum accroding to
// the formula: Checksum = 0xBABA - (sum of first 63 words).
//
// Arguments:
// Adapter - Ptr to this card's adapter data structure
//
// Returns: (none)
//-----------------------------------------------------------------------------
/*static VOID
UpdateChecksum(
struct rtl8192cd_priv *priv)
{
USHORT Checksum=0;
// USHORT Iter;
// for (Iter = 0; Iter < 0x3F; Iter++)
// Checksum += ReadEEprom( CSRBaseIoAddress, Iter );
Checksum = (USHORT)0xBABA - Checksum;
// WriteEEprom( CSRBaseIoAddress, 0x3F, Checksum );
}*/
//-----------------------------------------------------------------------------
// Procedure: WriteEEprom
//
// Description: This routine writes a word to a specific EEPROM location.
//
// Arguments:
// Adapter - Ptr to this card's adapter data structure.
// reg - The EEPROM word that we are going to write to.
// data - The data (word) that we are going to write to the EEPROM.
//
// Returns: (none)
//-----------------------------------------------------------------------------
static VOID
WriteEEprom(
struct rtl8192cd_priv *priv,
UCHAR AddressSize,
USHORT reg,
USHORT data)
{
UCHAR x;
// select EEPROM, mask off ASIC and reset bits, set EECS
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EEDI | EEDO | EESK | CR9346_EEM0);
x |= CR9346_EEM1 | EECS;
RTL_W8(CSR_EEPROM_CONTROL_REG, x);
ShiftOutBits(priv, EEPROM_EWEN_OPCODE, 5);
/////ShiftOutBits(CSRBaseIoAddress, reg, 4);
ShiftOutBits(priv, 0, 6);
StandBy(priv);
// Erase this particular word. Write the erase opcode and register
// number in that order. The opcode is 3bits in length; reg is 6 bits long.
ShiftOutBits(priv, EEPROM_ERASE_OPCODE, 3);
ShiftOutBits(priv, reg, AddressSize);
if (WaitEEPROMCmdDone(priv) == FALSE)
{
return;
}
StandBy(priv);
// write the new word to the EEPROM
// send the write opcode the EEPORM
ShiftOutBits(priv, EEPROM_WRITE_OPCODE, 3);
// select which word in the EEPROM that we are writing to.
ShiftOutBits(priv, reg, AddressSize);
// write the data to the selected EEPROM word.
ShiftOutBits(priv, data, 16);
if (WaitEEPROMCmdDone(priv) == FALSE)
{
// DbgPrint("D100: Failed EEPROM Write");
return;
}
StandBy(priv);
ShiftOutBits(priv, EEPROM_EWDS_OPCODE, 5);
ShiftOutBits(priv, reg, 4);
EEpromCleanup(priv);
return;
}
//-----------------------------------------------------------------------------
// Procedure: WaitEEPROMCmdDone
//
// Description: This routine waits for the the EEPROM to finish its command.
// Specifically, it waits for EEDO (data out) to go high.
//
// Arguments:
// Adapter - Ptr to this card's adapter data structure.
//
// Returns:
// TRUE - If the command finished
// FALSE - If the command never finished (EEDO stayed low)
//-----------------------------------------------------------------------------
static USHORT
WaitEEPROMCmdDone(
struct rtl8192cd_priv *priv)
{
UCHAR x;
USHORT i;
StandBy(priv);
for (i=0; i<200; i++)
{
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
if (x & EEDO)
return (TRUE);
delay_us(CLOCK_RATE);
}
return FALSE;
}
//-----------------------------------------------------------------------------
// Procedure: StandBy
//
// Description: This routine lowers the EEPROM chip select (EECS) for a few
// microseconds.
//
// Arguments:
// Adapter - Ptr to this card's adapter data structure.
//
// Returns: (none)
//-----------------------------------------------------------------------------
static VOID
StandBy(
struct rtl8192cd_priv *priv)
{
UCHAR x;
x = RTL_R8(CSR_EEPROM_CONTROL_REG);
x &= ~(EECS | EESK);
RTL_W8(CSR_EEPROM_CONTROL_REG, x);
delay_us(CLOCK_RATE);
x |= EECS;
RTL_W8(CSR_EEPROM_CONTROL_REG, x);
delay_us(CLOCK_RATE);
}
//*****************************************************************************
//
// Main routines to read and write EEPROM
//
//*****************************************************************************
#define NUM_11A_CHANNEL 46
const UCHAR ChannelNumberListOf11a[] = {
26, 28, 30, 32,
34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64,
66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86,
100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
149, 153, 157, 161
};
#define READ_EEPROM(addr) ReadEEprom(priv, EepromAddressSize, addr)
#define WRITE_EEPROM(a,d) WriteEEprom(priv, EepromAddressSize, a, d)
int ReadAdapterInfo(struct rtl8192cd_priv *priv, int entry_id, void *data)
{
USHORT Index;
USHORT usValue;
ULONG curRCR;
UCHAR EepromAddressSize;
UCHAR TxPowerLevel[64];
if (!priv->EE_Cached)
{
curRCR = RTL_R32(_RCR_);
EepromAddressSize = (curRCR & _9356SEL_)? 8 : 6;
// ID
priv->EE_ID = (unsigned int)READ_EEPROM(EEPROM_ID);
DEBUG_INFO("ID 0x%04X\n", (USHORT)priv->EE_ID);
if (priv->EE_ID != RTL8180_EEPROM_ID) {
DEBUG_INFO("ID is invalid\n");
priv->EE_AutoloadFail = TRUE;
}
else
priv->EE_AutoloadFail = FALSE;
// Version
// priv->EE_Version = (unsigned int)READ_EEPROM((USHORT)(EEPROM_VERSION >> 1));
usValue = READ_EEPROM(0x7C >> 1);
priv->EE_Version = ((usValue&0xff00)>>8);
DEBUG_INFO("Version 0x%x\n", (USHORT)priv->EE_Version);
// MAC address
for (Index = 0; Index < 6; Index += 2) {
usValue = READ_EEPROM((USHORT)((EEPROM_NODE_ADDRESS_BYTE_0 + Index)>>1));
priv->EE_Mac[Index] = usValue & 0xff;
priv->EE_Mac[Index+1] = ((usValue&0xff00) >> 8);
}
DEBUG_INFO("Mac %02X-%02X-%02X-%02X-%02X-%02X\n",
priv->EE_Mac[0], priv->EE_Mac[1], priv->EE_Mac[2], priv->EE_Mac[3],
priv->EE_Mac[4], priv->EE_Mac[5]);
// for identifying empty EEPROM
if (!priv->EE_AutoloadFail)
{
// Tx Power Level
memset(priv->EE_TxPower_CCK, 0, sizeof(priv->EE_TxPower_CCK));
for (Index = 0; Index < MAX_CCK_CHANNEL_NUM; Index += 2) {
usValue = READ_EEPROM((USHORT)((EEPROM_TX_POWER_LEVEL_0 + Index) >> 1));
*((USHORT *)(&priv->EE_TxPower_CCK[Index])) = usValue;
}
memset(priv->EE_TxPower_OFDM, 0, sizeof(priv->EE_TxPower_OFDM));
for (Index = 0; Index < NUM_11A_CHANNEL; Index += 2) {
usValue = READ_EEPROM((USHORT)((EEPROM_11A_CHANNEL_TX_POWER_LEVEL_OFFSET + Index) >> 1));
*((USHORT *)(&TxPowerLevel[Index])) = usValue;
}
for (Index = 0; Index < NUM_11A_CHANNEL; Index++)
priv->EE_TxPower_OFDM[ChannelNumberListOf11a[Index] - 1] = TxPowerLevel[Index];
for (Index = 0; Index < MAX_CCK_CHANNEL_NUM; Index += 2) {
usValue = READ_EEPROM((USHORT)((EEPROM_11G_CHANNEL_OFDM_TX_POWER_LEVEL_OFFSET + Index) >> 1));
*((USHORT *)(&TxPowerLevel[Index])) = usValue;
}
for (Index = 0; Index < MAX_CCK_CHANNEL_NUM; Index++)
priv->EE_TxPower_OFDM[Index] = TxPowerLevel[Index];
#ifdef _DEBUG_RTL8192CD_
if (rtl8192cd_debug_info & _MODULE_DEFINE) {
extern void debug_out(char *label, unsigned char *data, int data_length);
debug_out("EEProm CCK TxPower", priv->EE_TxPower_CCK, MAX_CCK_CHANNEL_NUM);
debug_out("EEProm OFDM TxPower", priv->EE_TxPower_OFDM, MAX_OFDM_CHANNEL_NUM);
}
#endif
// RF chip id
// priv->EE_RFTypeID = (unsigned int)(READ_EEPROM((USHORT)(EEPROM_RF_CHIP_ID >> 1)) & 0x00f);
priv->EE_RFTypeID = (unsigned int)(READ_EEPROM((USHORT)(0x28 >> 1)) & 0x80 ) >> 7;
DEBUG_INFO("RF ID 0x%02X\n", (UCHAR)priv->EE_RFTypeID);
// AnaParm
usValue = READ_EEPROM((USHORT)((EEPROM_ANA_PARM + 2) >> 1));
priv->EE_AnaParm = (unsigned int)(usValue << 16);
usValue = READ_EEPROM((USHORT)(EEPROM_ANA_PARM >> 1));
priv->EE_AnaParm |= usValue;
DEBUG_INFO("AnaParm 0x%08X\n", priv->EE_AnaParm);
usValue = READ_EEPROM((USHORT)((EEPROM_ANA_PARM2 + 2) >> 1));
priv->EE_AnaParm2 = (unsigned int)(usValue << 16);
usValue = READ_EEPROM((USHORT)(EEPROM_ANA_PARM2 >> 1));
priv->EE_AnaParm2 |= usValue;
DEBUG_INFO("AnaParm2 0x%08X\n", priv->EE_AnaParm2);
//add CrystalCap, joshua 20080502
priv->EE_CrystalCap = (((unsigned int) READ_EEPROM( 0x2A >> 1)) & 0xf000) >> 12;
priv->pmib->dot11RFEntry.crystalCap = priv->EE_CrystalCap;
DEBUG_INFO("CrystalCap 0x%08X\n", priv->EE_CrystalCap);
}
priv->EE_Cached = 1;
}
if ((data != NULL) && (!priv->EE_AutoloadFail))
{
switch(entry_id)
{
case EEPROM_RF_CHIP_ID:
*((UCHAR *)data) = (UCHAR)priv->EE_RFTypeID;
break;
case EEPROM_NODE_ADDRESS_BYTE_0:
memcpy(data, priv->EE_Mac, MACADDRLEN);
break;
case EEPROM_TX_POWER_LEVEL_0:
memcpy(data, priv->EE_TxPower_CCK, MAX_CCK_CHANNEL_NUM);
break;
case EEPROM_11G_CHANNEL_OFDM_TX_POWER_LEVEL_OFFSET:
memcpy(data, priv->EE_TxPower_OFDM, MAX_OFDM_CHANNEL_NUM);
break;
default:
DEBUG_INFO("not support this id yet\n");
return 0;
}
return 1;
}
else
return 0;
}
int WriteAdapterInfo(struct rtl8192cd_priv *priv, int entry_id, void *data)
{
USHORT Index;
USHORT usValue;
ULONG curRCR;
UCHAR EepromAddressSize;
priv->EE_Cached = 0;
curRCR = RTL_R32(_RCR_);
EepromAddressSize = (curRCR & _9356SEL_)? 8 : 6;
switch(entry_id)
{
case EEPROM_TX_POWER_LEVEL_0:
Index = ((USHORT)((int)data)) & 0xfffe;
usValue = *((USHORT *)(&priv->EE_TxPower_CCK[Index]));
WRITE_EEPROM((USHORT)((EEPROM_TX_POWER_LEVEL_0 + Index) >> 1), usValue);
break;
case EEPROM_11G_CHANNEL_OFDM_TX_POWER_LEVEL_OFFSET:
Index = ((USHORT)((int)data)) & 0xfffe;
usValue = *((USHORT *)(&priv->EE_TxPower_OFDM[Index]));
WRITE_EEPROM((USHORT)((EEPROM_11G_CHANNEL_OFDM_TX_POWER_LEVEL_OFFSET + Index) >> 1), usValue);
break;
default:
return 0;
}
return 1;
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_headers.h
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_host.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_hw.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_hw.h
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_ioctl.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_led.c
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@@ -0,0 +1,646 @@
/*
* Handling routines for LED lightening functions
*
* $Id: 8192cd_led.c,v 1.1 2012/05/04 12:49:07 jimmylin Exp $
*
* Copyright (c) 2012 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define _8192CD_LED_C_
#include "./8192cd_cfg.h"
#include "./8192cd.h"
#include "./8192cd_headers.h"
#include "./8192cd_debug.h"
// for SW LED ----------------------------------------------------
#ifdef RTL8190_SWGPIO_LED
static void set_swGpio_LED(struct rtl8192cd_priv *priv, unsigned int ledNum, int flag)
{
unsigned int ledItem; /* parameter to decode GPIO item */
if (ledNum >= SWLED_GPIORT_CNT)
return;
ledItem = SWLED_GPIORT_ITEM(LED_ROUTE, ledNum);
if (ledItem & SWLED_GPIORT_ENABLEMSK)
{
/* get the corresponding information (GPIO number/Active high or low) of LED */
int gpio;
int activeMode; /* !=0 : Active High, ==0 : Active Low */
gpio = ledItem & SWLED_GPIORT_RTBITMSK;
activeMode = ledItem & SWLED_GPIORT_HLMSK;
if (flag) { /* Turn ON LED */
if (activeMode) /* Active High */
RTL_W8(0x90, RTL_R8(0x90) | BIT(gpio));
else /* Active Low */
RTL_W8(0x90, RTL_R8(0x90) &~ BIT(gpio));
}
else { /* Turn OFF LED */
if (activeMode) /* Active High */
RTL_W8(0x90, RTL_R8(0x90) &~ BIT(gpio));
else /* Active Low */
RTL_W8(0x90, RTL_R8(0x90) | BIT(gpio));
}
}
}
#endif // RTL8190_SWGPIO_LED
static void set_sw_LED0(struct rtl8192cd_priv *priv, int flag)
{
#ifdef RTL8190_SWGPIO_LED
if (LED_ROUTE)
set_swGpio_LED(priv, 0, flag);
#elif defined(CONFIG_RTL8672) || defined(NOT_RTK_BSP)
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffffff0) | LED0SV);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffffff0);
#else
if ((GET_CHIP_VER(priv) == VERSION_8188E)||(GET_CHIP_VER(priv) == VERSION_8192E)) {
#ifdef RTLWIFINIC_GPIO_CONTROL
if (flag)
RTLWIFINIC_GPIO_write(5, 0);
else
RTLWIFINIC_GPIO_write(5, 1);
#endif
}
else if ((GET_CHIP_VER(priv) == VERSION_8812E)) {
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff);
}
else if (GET_CHIP_VER(priv) == VERSION_8881A) {
if (flag)
writel(readl(IO_TYPE_CAST(0xb800350c)) | BIT(24), IO_TYPE_CAST(0xb800350c));
else
writel(readl(IO_TYPE_CAST(0xb800350c)) & ~BIT(24), IO_TYPE_CAST(0xb800350c));
}
else {
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffffff0) | LED0SV);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffffff0);
}
#endif
}
static void set_sw_LED1(struct rtl8192cd_priv *priv, int flag)
{
#ifdef RTL8190_SWGPIO_LED
if (LED_ROUTE)
set_swGpio_LED(priv, 1, flag);
#elif defined(CONFIG_RTL8672) || defined(NOT_RTK_BSP)
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff);
#else
if ((GET_CHIP_VER(priv) == VERSION_8188E)||(GET_CHIP_VER(priv) == VERSION_8192E)) {
#ifdef RTLWIFINIC_GPIO_CONTROL
if (flag)
RTLWIFINIC_GPIO_write(5, 0);
else
RTLWIFINIC_GPIO_write(5, 1);
#endif
}
#if defined(CONFIG_RTL_92D_SUPPORT)
else if (GET_CHIP_VER(priv) == VERSION_8192D) {
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV_92D);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff);
}
#endif
else if (GET_CHIP_VER(priv) == VERSION_8192C){
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff);
}
#endif
}
static void set_sw_LED2(struct rtl8192cd_priv *priv, int flag)
{
#ifdef RTL8190_SWGPIO_LED
if (LED_ROUTE)
set_swGpio_LED(priv, 2, flag);
#elif defined(CONFIG_RTL8672) || defined(NOT_RTK_BSP)
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfff0ffff) | LED2SV);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfff0ffff);
#else
if ((GET_CHIP_VER(priv) == VERSION_8188E)||(GET_CHIP_VER(priv) == VERSION_8192E)) {
#ifdef RTLWIFINIC_GPIO_CONTROL
if (flag)
RTLWIFINIC_GPIO_write(5, 0);
else
RTLWIFINIC_GPIO_write(5, 1);
#endif
}
#if defined(CONFIG_RTL_92D_SUPPORT)
else if (GET_CHIP_VER(priv) == VERSION_8192D) {
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfff0ffff) | LED2SV_92D);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfff0ffff);
}
#endif
else if (GET_CHIP_VER(priv) == VERSION_8192C){
if (flag)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfff0ffff) | LED2SV);
else
RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfff0ffff);
}
#endif
}
static void LED_Interval_timeout(unsigned long task_priv)
{
struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv;
int led_on_time= LED_ON_TIME;
if (!(priv->drv_state & DRV_STATE_OPEN))
return;
#ifdef PCIE_POWER_SAVING
if ((priv->pwr_state != L1) && (priv->pwr_state != L2))
#endif
{
if (!priv->pshare->set_led_in_progress) {
#if defined(CONFIG_RTL8672) || defined(NOT_RTK_BSP)
#ifdef CONFIG_RTL_88E_SUPPORT
if (GET_CHIP_VER(priv) == VERSION_8188E)
set_sw_LED2(priv, priv->pshare->LED_Toggle);
else
#endif
#ifdef CONFIG_WLAN_HAL_8192EE
if (GET_CHIP_VER(priv) == VERSION_8192E)
set_sw_LED0(priv, priv->pshare->LED_Toggle);
else
#endif
#ifdef CONFIG_RTL_8812_SUPPORT
if (GET_CHIP_VER(priv) == VERSION_8812E)
set_sw_LED1(priv, priv->pshare->LED_Toggle);
else
#endif
#endif // CONFIG_RTL8672 || NOT_RTK_BSP
if ((LED_TYPE == LEDTYPE_SW_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LINKTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA) ||
((LED_TYPE == LEDTYPE_SW_ADATA_GDATA) && (priv->pshare->curr_band == BAND_5G)) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA_92D) ||
(LED_TYPE == LEDTYPE_SW_LED1_GPIO9_LINKTXRX_92D) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX_92D))
{
if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA_92D) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX_92D))
set_sw_LED2(priv, priv->pshare->LED_Toggle);
else if (LED_TYPE == LEDTYPE_SW_LED1_GPIO9_LINKTXRX_92D)
set_sw_LED1(priv, priv->pshare->LED_Toggle);
else
set_sw_LED0(priv, priv->pshare->LED_Toggle);
} else {
set_sw_LED1(priv, priv->pshare->LED_Toggle);
}
}
}
if( (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) &&
(!(OPMODE & WIFI_ASOC_STATE))) //client not assco , mark_led
{
led_on_time = LED_NOBLINK_TIME;
}
if ( priv->pshare->LED_Toggle == priv->pshare->LED_ToggleStart) {
mod_timer(&priv->pshare->LED_Timer, jiffies + priv->pshare->LED_Interval);
} else {
if (LED_TYPE == LEDTYPE_SW_CUSTOM1)
mod_timer(&priv->pshare->LED_Timer, jiffies + priv->pshare->LED_Interval);
else
mod_timer(&priv->pshare->LED_Timer, jiffies + led_on_time);
}
priv->pshare->LED_Toggle = (priv->pshare->LED_Toggle + 1) % 2;
}
void enable_sw_LED(struct rtl8192cd_priv *priv, int init)
{
#if (defined(HW_ANT_SWITCH) || defined(SW_ANT_SWITCH))&&( defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT))
int b23 = RTL_R32(LEDCFG) & BIT(23);
#endif
if (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA)
if (!(OPMODE & WIFI_STATION_STATE)) // if it is not Client mode , then run orignal 12 type
LED_TYPE = LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA ;
// configure mac to use SW LED
#if defined(CONFIG_RTL8672) || defined(NOT_RTK_BSP)
#ifdef CONFIG_RTL_88E_SUPPORT
if (GET_CHIP_VER(priv) == VERSION_8188E)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | LED2EN | LED2SV);
else
#endif
#ifdef CONFIG_WLAN_HAL_8192EE
if (GET_CHIP_VER(priv) == VERSION_8192E)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFFFFFF00) | LED0SV);
else
#endif
#else // !CONFIG_RTL8672 && !NOT_RTK_BSP
#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE) //mark_ecos
if ((GET_CHIP_VER(priv) == VERSION_8188E)||(GET_CHIP_VER(priv) == VERSION_8192E))
{
#ifdef RTLWIFINIC_GPIO_CONTROL
RTLWIFINIC_GPIO_config(5, 0x10);
#endif
}
else
#endif
#endif // CONFIG_RTL8672 || NOT_RTK_BSP
if (GET_CHIP_VER(priv) == VERSION_8812E)
RTL_W32(LEDCFG, BIT(13) | LED1SV);
else
#ifdef CONFIG_WLAN_HAL_8881A
if (GET_CHIP_VER(priv) == VERSION_8881A) {
writel(readl(IO_TYPE_CAST(0xb8000044)) | BIT(15) | BIT(16), IO_TYPE_CAST(0xb8000044));
writel(readl(IO_TYPE_CAST(0xb8003500)) & ~BIT(24), IO_TYPE_CAST(0xb8003500));
writel(readl(IO_TYPE_CAST(0xb8003508)) | BIT(24), IO_TYPE_CAST(0xb8003508));
writel(readl(IO_TYPE_CAST(0xb800350c)) | BIT(24), IO_TYPE_CAST(0xb800350c));
} else
#endif
{
if (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | LED2EN | LED2SV);
else if (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | LED2EN | LED2SV);
#ifdef CONFIG_RTL_92D_SUPPORT
else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX_92D) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA_92D))
RTL_W32(LEDCFG,(RTL_R32(LEDCFG)&0xFF00FFFF)| LED2DIS_92D | LED2SV_92D);
else if (LED_TYPE == LEDTYPE_SW_LED1_GPIO9_LINKTXRX_92D)
RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFFFF00FF)|LED1DIS_92D | LED1SV_92D);
#endif
else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA))
RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | GP8_LED | LED2EN | LED2SV);
else
RTL_W32(LEDCFG, LED2SV | LED1SV | LED0SV);
}
priv->pshare->LED_Interval = LED_INTERVAL_TIME;
priv->pshare->LED_Toggle = 0;
priv->pshare->LED_ToggleStart = LED_OFF;
priv->pshare->LED_tx_cnt_log = 0;
priv->pshare->LED_rx_cnt_log = 0;
priv->pshare->LED_tx_cnt = 0;
priv->pshare->LED_rx_cnt = 0;
if ((LED_TYPE == LEDTYPE_SW_ENABLE_TXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA)) {
set_sw_LED0(priv, LED_ON);
set_sw_LED1(priv, LED_OFF);
if (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA)
priv->pshare->LED_ToggleStart = LED_ON;
} else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA_92D)) {
set_sw_LED2(priv, LED_ON);
priv->pshare->LED_ToggleStart = LED_ON;
} else if (LED_TYPE == LEDTYPE_SW_ADATA_GDATA) {
priv->pshare->LED_ToggleStart = LED_ON;
if (priv->pshare->curr_band == BAND_5G) {
set_sw_LED0(priv, LED_ON);
set_sw_LED1(priv, LED_OFF);
}
else { // 11G
set_sw_LED0(priv, LED_OFF);
set_sw_LED1(priv, LED_ON);
}
}
else if (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA_1) {
set_sw_LED0(priv, LED_OFF);
set_sw_LED1(priv, LED_ON);
priv->pshare->LED_ToggleStart = LED_ON;
}
else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) ) {
set_sw_LED2(priv, LED_ON);
priv->pshare->LED_ToggleStart = LED_ON;
}
else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA)) {
set_sw_LED2(priv, LED_OFF);
}
else {
set_sw_LED0(priv, LED_OFF);
set_sw_LED1(priv, LED_OFF);
set_sw_LED2(priv, LED_OFF);
}
#if (defined(HW_ANT_SWITCH) || defined(SW_ANT_SWITCH))&&( defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT))
RTL_W32(LEDCFG, b23 | RTL_R32(LEDCFG));
#endif
if (init) {
init_timer(&priv->pshare->LED_Timer);
#if defined(CONFIG_PCI_HCI)
priv->pshare->LED_Timer.data = (unsigned long) priv;
priv->pshare->LED_Timer.function = &LED_Interval_timeout;
#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
priv->pshare->LED_Timer.data = (unsigned long) &priv->pshare->LED_Timer_event;
priv->pshare->LED_Timer.function = timer_event_timer_fn;
INIT_TIMER_EVENT_ENTRY(&priv->pshare->LED_Timer_event,
LED_Interval_timeout, (unsigned long)priv);
#endif
mod_timer(&priv->pshare->LED_Timer, jiffies + priv->pshare->LED_Interval);
}
}
void disable_sw_LED(struct rtl8192cd_priv *priv)
{
if (timer_pending(&priv->pshare->LED_Timer))
del_timer_sync(&priv->pshare->LED_Timer);
if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA)) {
set_sw_LED2(priv, LED_OFF);
} else {
set_sw_LED0(priv, LED_OFF);
set_sw_LED1(priv, LED_OFF);
set_sw_LED2(priv, LED_OFF);
}
}
void calculate_sw_LED_interval(struct rtl8192cd_priv *priv)
{
unsigned int delta = 0;
int i, scale_num=0;
if (priv->pshare->set_led_in_progress)
return;
if( (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) &&
(!(OPMODE & WIFI_ASOC_STATE))) //client not assco , mark_led
{
priv->pshare->LED_Interval = LED_NOBLINK_TIME; // force one second
priv->pshare->LED_tx_cnt_log = priv->pshare->LED_tx_cnt; // sync tx/rx cnt
priv->pshare->LED_rx_cnt_log = priv->pshare->LED_rx_cnt;
return ;
}
// calculate counter delta
delta += UINT32_DIFF(priv->pshare->LED_tx_cnt, priv->pshare->LED_tx_cnt_log);
delta += UINT32_DIFF(priv->pshare->LED_rx_cnt, priv->pshare->LED_rx_cnt_log);
priv->pshare->LED_tx_cnt_log = priv->pshare->LED_tx_cnt;
priv->pshare->LED_rx_cnt_log = priv->pshare->LED_rx_cnt;
// update interval according to delta
if (delta == 0) {
if (LED_TYPE == LEDTYPE_SW_CUSTOM1) {
if (priv->pshare->LED_Interval != RTL_SECONDS_TO_JIFFIES(1)) {
priv->pshare->LED_Interval = RTL_SECONDS_TO_JIFFIES(1);
mod_timer(&priv->pshare->LED_Timer, jiffies + priv->pshare->LED_Interval);
}
} else {
if (priv->pshare->LED_Interval == LED_NOBLINK_TIME)
mod_timer(&priv->pshare->LED_Timer, jiffies + priv->pshare->LED_Interval);
else {
priv->pshare->LED_Interval = LED_NOBLINK_TIME;
if (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA)
priv->pshare->LED_Toggle = LED_ON;
}
}
} else {
if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) ||
(priv->pmib->dot11BssType.net_work_type & WIRELESS_11A))
scale_num = LED_MAX_PACKET_CNT_AG / LED_MAX_SCALE;
else
scale_num = LED_MAX_PACKET_CNT_B / LED_MAX_SCALE;
if ((LED_TYPE == LEDTYPE_SW_LINK_TXRX) ||
(LED_TYPE == LEDTYPE_SW_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED1_GPIO9_LINKTXRX_92D) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX_92D) ||
(LED_TYPE == LEDTYPE_SW_CUSTOM1))
scale_num = scale_num*2;
for (i=1; i<=LED_MAX_SCALE; i++) {
if (delta < i*scale_num)
break;
}
if (priv->pshare->rf_ft_var.ledBlinkingFreq > 1) {
i = i*priv->pshare->rf_ft_var.ledBlinkingFreq;
if (i > LED_MAX_SCALE)
i = LED_MAX_SCALE;
}
priv->pshare->LED_Interval = ((LED_MAX_SCALE-i+1)*LED_INTERVAL_TIME)/LED_MAX_SCALE;
if (priv->pshare->LED_Interval < LED_ON_TIME)
priv->pshare->LED_Interval = LED_ON_TIME;
}
if ((LED_TYPE == LEDTYPE_SW_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LINKTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA) ||
(LED_TYPE == LEDTYPE_SW_LED1_GPIO9_LINKTXRX_92D) ||
(LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX_92D)) {
if (priv->link_status)
priv->pshare->LED_ToggleStart = LED_ON;
else
priv->pshare->LED_ToggleStart = LED_OFF;
} else {
if (priv->pshare->set_led_in_progress)
return;
if ((LED_TYPE == LEDTYPE_SW_LINK_TXRX) ||
(LED_TYPE == LEDTYPE_SW_LINK_TXRXDATA)) {
if (priv->link_status)
set_sw_LED0(priv, LED_ON);
else
set_sw_LED0(priv, LED_OFF);
} else if (LED_TYPE == LEDTYPE_SW_ADATA_GDATA) {
if (priv->pshare->curr_band == BAND_5G) {
set_sw_LED0(priv, LED_ON);
set_sw_LED1(priv, LED_OFF);
} else { // 11A
set_sw_LED0(priv, LED_OFF);
set_sw_LED1(priv, LED_ON);
}
}
}
}
#if 0
void set_wireless_LED_steady_on(int led_num, struct net_device *dev)
{
struct rtl8192cd_priv *priv;
if (led_num != LED_0 && led_num != LED_1 && led_num != LED_2)
return;
#ifdef NETDEV_NO_PRIV
if (dev == NULL || netdev_priv(dev) == NULL)
return;
priv = ((struct rtl8192cd_priv *)netdev_priv(dev))->wlan_priv;
#else
if (dev == NULL || dev->priv == NULL)
return;
priv = (struct rtl8192cd_priv *)dev->priv;
#endif
if (priv->pshare == NULL)
return;
priv->pshare->set_led_in_progress = 1;
if ((LED_TYPE >= LEDTYPE_HW_TX_RX) && (LED_TYPE <= LEDTYPE_HW_LINKACT_INFRA)) {
enable_sw_LED(priv, 0);
}
else if ((LED_TYPE >= LEDTYPE_SW_LINK_TXRX) && (LED_TYPE < LEDTYPE_SW_MAX)) {
if (timer_pending(&priv->pshare->LED_Timer))
del_timer_sync(&priv->pshare->LED_Timer);
}
if (led_num == LED_0)
set_sw_LED0(priv, LED_ON);
else if (led_num == LED_1)
set_sw_LED1(priv, LED_ON);
else
set_sw_LED2(priv, LED_ON);
}
void recover_wireless_LED(struct net_device *dev)
{
struct rtl8192cd_priv *priv;
#ifdef NETDEV_NO_PRIV
if (dev == NULL || netdev_priv(dev) == NULL)
return;
priv = ((struct rtl8192cd_priv *)netdev_priv(dev))->wlan_priv;
#else
if (dev == NULL || dev->priv == NULL)
return;
priv = (struct rtl8192cd_priv *)dev->priv;
#endif
if (!priv->pshare->set_led_in_progress)
return;
// for HW/SW LED
if ((LED_TYPE >= LEDTYPE_HW_TX_RX) && (LED_TYPE <= LEDTYPE_HW_LINKACT_INFRA)) {
set_sw_LED0(priv, LED_OFF);
set_sw_LED1(priv, LED_OFF);
set_sw_LED2(priv, LED_OFF);
enable_hw_LED(priv, LED_TYPE);
}
else if ((LED_TYPE >= LEDTYPE_SW_LINK_TXRX) && (LED_TYPE < LEDTYPE_SW_MAX)) {
enable_sw_LED(priv, 0);
mod_timer(&priv->pshare->LED_Timer, jiffies + priv->pshare->LED_Interval);
}
priv->pshare->set_led_in_progress = 0;
}
#endif
void control_wireless_led(struct rtl8192cd_priv *priv, int enable)
{
if (enable == 0) {
priv->pshare->set_led_in_progress = 1;
set_sw_LED0(priv, LED_OFF);
set_sw_LED1(priv, LED_OFF);
set_sw_LED2(priv, LED_OFF);
}
else if (enable == 1) {
priv->pshare->set_led_in_progress = 1;
set_sw_LED0(priv, LED_ON);
set_sw_LED1(priv, LED_ON);
set_sw_LED2(priv, LED_ON);
}
else if (enable == 2) {
set_sw_LED0(priv, priv->pshare->LED_ToggleStart);
set_sw_LED1(priv, priv->pshare->LED_ToggleStart);
set_sw_LED2(priv, priv->pshare->LED_ToggleStart);
priv->pshare->set_led_in_progress = 0;
}
}
#ifdef CONFIG_RTL_ULINKER
static struct rtl8192cd_priv *root_priv = NULL;
void enable_sys_LED(struct rtl8192cd_priv *priv)
{
#ifdef RTLWIFINIC_GPIO_CONTROL
RTLWIFINIC_GPIO_config(4, 0x10);
#endif
root_priv = priv;
}
void renable_sw_LED(void)
{
struct rtl8192cd_priv *priv = root_priv;
if ((LED_TYPE >= LEDTYPE_SW_LINK_TXRX) && (LED_TYPE < LEDTYPE_SW_MAX)) {
priv->pshare->set_led_in_progress = 1;
disable_sw_LED(priv);
priv->pshare->set_led_in_progress = 0;
enable_sw_LED(priv, 1);
}
}
#endif /* #ifdef CONFIG_RTL_ULINKER */
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_log.h
Executable
+45
View File
@@ -0,0 +1,45 @@
#ifndef 8192CD_LOG_H
#define 8192CD_LOG_H
#if defined(CONFIG_RTL_LOG_DEBUG)
#if defined(LOG_ERROR)
#undef LOG_ERROR
#define LOG_ERROR(fmt, args...) do{ \
if(RTL_LogTypeMask.ERROR&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-ERROR:"fmt, ## args); \
}while(0)
#endif
#if defined(LOG_MEM_ERROR)
#undef LOG_MEM_ERROR
#define LOG_MEM_ERROR(fmt, args...) do{ \
if(RTL_LogTypeMask.ERROR&&RTL_LogErrorMask.MEM&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-MEM-ERROR:"fmt, ## args); \
}while(0)
#endif
#if defined(LOG_SKB_ERROR)
#undef LOG_SKB_ERROR
#define LOG_SKB_ERROR(fmt, args...) do{ \
if(RTL_LogTypeMask.ERROR&&RTL_LogErrorMask.SKB&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-SKB-ERROR:"fmt, ## args); \
}while(0)
#endif
#if defined(LOG_WARN)
#undef LOG_WARN
#define LOG_WARN(fmt, args...) do{ \
if(RTL_LogTypeMask.WARN&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-WARN:"fmt, ## args); \
}while(0)
#endif
#if defined(LOG_INFO)
#undef LOG_INFO
#define LOG_INFO(fmt, args...) do{ \
if(RTL_LogTypeMask.INFO&&RTL_LogModuleMask.WIRELESS&&LOG_LIMIT)scrlog_printk("WLS-INFO:"fmt, ## args); \
}while(0)
#endif
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_mib.c
Executable
+555
View File
@@ -0,0 +1,555 @@
/*
* SNMP MIB module
*
* $Id: 8192cd_mib.c,v 1.1 2009/11/06 12:26:48 victoryman Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define _8192CD_MIB_C_
#ifdef __KERNEL__
#include <linux/module.h>
#elif defined(__ECOS)
#include <cyg/io/eth/rltk/819x/wrapper/sys_support.h>
#include <cyg/io/eth/rltk/819x/wrapper/skbuff.h>
#include <cyg/io/eth/rltk/819x/wrapper/timer.h>
#include <cyg/io/eth/rltk/819x/wrapper/wrapper.h>
#endif
#include "./8192cd_cfg.h"
#ifdef SUPPORT_SNMP_MIB
#ifdef __KERNEL__
#include "./ieee802_mib.h"
#elif defined(__ECOS)
#include <cyg/io/eth/rltk/819x/wlan/ieee802_mib.h>
#endif
#include "./8192cd_headers.h"
#include "./8192cd_debug.h"
#include "./8192cd_mib.h"
extern int _convert_2_pwr_dot(char *s, int base);
extern int _atoi(char *s, int base);
struct mib_val dot11_mib_table[]={
//dot11StationConfigTable
{ {1, 1, 1, 1, 1, -1}, "dot11StationID", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.hwaddr), PRIV_SIZE(dot11OperationEntry.hwaddr)},
{ {1, 1, 1, 2, 1, -1}, "dot11MediumOccupancyLimit ", MIB_TYPE_VAL, 100, 1},
{ {1, 1, 1, 3, 1, -1}, "dot11CFPollable", MIB_TYPE_VAL, 0, 1},
{ {1, 1, 1, 4, 1, -1}, "dot11CFPPeriod", MIB_TYPE_VAL, 0, 1},
{ {1, 1, 1, 5, 1, -1}, "dot11CFPMaxDuration", MIB_TYPE_VAL, 0, 1},
{ {1, 1, 1, 6, 1, -1}, "dot11AuthenticationResponseTimeOut", MIB_TYPE_VAL, REAUTH_TO*10, 4},
{ {1, 1, 1, 7, 1, -1}, "dot11PrivacyOptionImplemented", MIB_TYPE_VAL, 1, 1},
{ {1, 1, 1, 8, 1, -1}, "dot11PowerManagementMode", MIB_TYPE_VAL, 1, 1},
{ {1, 1, 1, 9, 1, -1}, "dot11DesiredSSID", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11DesiredSSID), 0},
{ {1, 1, 1, 10, 1, -1}, "dot11DesiredBSSType", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DesiredBSSType), SNMP_SIZE(dot11DesiredBSSType)},
{ {1, 1, 1, 11, 1, -1}, "dot11OperationalRateSet", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11OperationalRateSet), SNMP_OFFSET(dot11SupportedDataRatesNum)},
{ {1, 1, 1, 12, 1, -1}, "dot11BeaconPeriod", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11BeaconPeriod), PRIV_SIZE(dot11StationConfigEntry.dot11BeaconPeriod)},
{ {1, 1, 1, 13, 1, -1}, "dot11DTIMPeriod", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11DTIMPeriod), PRIV_SIZE(dot11StationConfigEntry.dot11DTIMPeriod)},
{ {1, 1, 1, 14, 1, -1}, "dot11AssociationResponseTimeOut", MIB_TYPE_VAL, REASSOC_TO*10, 4},
{ {1, 1, 1, 15, 1, -1}, "dot11DisassociateReason", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DisassociateReason), SNMP_SIZE(dot11DisassociateReason)},
{ {1, 1, 1, 16, 1, -1}, "dot11DisassociateStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DisassociateStation), SNMP_SIZE(dot11DisassociateStation)},
{ {1, 1, 1, 17, 1, -1}, "dot11DeauthenticateReason", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DeauthenticateReason), SNMP_SIZE(dot11DeauthenticateReason)},
{ {1, 1, 1, 18, 1, -1}, "dot11DeauthenticateStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DeauthenticateStation), SNMP_SIZE(dot11DeauthenticateStation)},
{ {1, 1, 1, 19, 1, -1}, "dot11AuthenticateFailStatus", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticateFailStatus), SNMP_SIZE(dot11AuthenticateFailStatus)},
{ {1, 1, 1, 20, 1, -1}, "dot11AuthenticateFailStation", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticateFailStation), SNMP_SIZE(dot11AuthenticateFailStation)},
{ {1, 1, 1, 24, 1, -1}, "dot11RegDomain", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.dot11RegDomain), PRIV_SIZE(dot11StationConfigEntry.dot11RegDomain)},
{ {1, 1, 1, 25, 1, -1}, "dot11DataRate", MIB_TYPE_SNMP, SNMP_OFFSET(dot11DataRate), SNMP_SIZE(dot11DataRate)},
{ {1, 1, 1, 26, 1, -1}, "dot11ProtectionDisabled", MIB_TYPE_PRIV, PRIV_OFFSET(dot11StationConfigEntry.protectionDisabled), PRIV_SIZE(dot11StationConfigEntry.protectionDisabled)},
{ {1, 1, 1, 27, 1, -1}, "dot11nSTBC", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nSTBC), PRIV_SIZE(dot11nConfigEntry.dot11nSTBC)},
{ {1, 1, 1, 28, 1, -1}, "dot11nCoexist", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nCoexist), PRIV_SIZE(dot11nConfigEntry.dot11nCoexist)},
{ {1, 1, 1, 29, 1, -1}, "dot11nUse40M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nUse40M), PRIV_SIZE(dot11nConfigEntry.dot11nUse40M)},
{ {1, 1, 1, 30, 1, -1}, "dot11n2ndChOffset", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11n2ndChOffset), PRIV_SIZE(dot11nConfigEntry.dot11n2ndChOffset)},
{ {1, 1, 1, 31, 1, -1}, "dot11nShortGIfor20M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nShortGIfor20M), PRIV_SIZE(dot11nConfigEntry.dot11nShortGIfor20M)},
{ {1, 1, 1, 32, 1, -1}, "dot11nShortGIfor40M", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nShortGIfor40M), PRIV_SIZE(dot11nConfigEntry.dot11nShortGIfor40M)},
{ {1, 1, 1, 33, 1, -1}, "dot11nAMPDU", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nAMPDU), PRIV_SIZE(dot11nConfigEntry.dot11nAMPDU)},
{ {1, 1, 1, 34, 1, -1}, "dot11nAMSDU", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nAMSDU), PRIV_SIZE(dot11nConfigEntry.dot11nAMSDU)},
{ {1, 1, 1, 35, 1, -1}, "dot11nLDPC", MIB_TYPE_PRIV, PRIV_OFFSET(dot11nConfigEntry.dot11nLDPC), PRIV_SIZE(dot11nConfigEntry.dot11nLDPC)},
//dot11AuthenticationAlgorithmsTable
{ {1, 2, 1, 1, 1, -1}, "dot11AuthenticationAlgorithmsIndex", MIB_TYPE_VAL, 1, 1},
{ {1, 2, 1, 2, 1, -1}, "dot11AuthenticationAlgorithm", MIB_TYPE_VAL, 1, 1},
{ {1, 2, 1, 3, 1, -1}, "dot11AuthenticationAlgorithmsEnable", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticationAlgorithmsEnableOpen), SNMP_SIZE(dot11AuthenticationAlgorithmsEnableOpen)},
{ {1, 2, 1, 1, 2, -1}, "dot11AuthenticationAlgorithmsIndex", MIB_TYPE_VAL, 2, 1},
{ {1, 2, 1, 2, 2, -1}, "dot11AuthenticationAlgorithm", MIB_TYPE_VAL, 2, 1},
{ {1, 2, 1, 3, 2, -1}, "dot11AuthenticationAlgorithmsEnable", MIB_TYPE_SNMP, SNMP_OFFSET(dot11AuthenticationAlgorithmsEnableShared), SNMP_SIZE(dot11AuthenticationAlgorithmsEnableShared)},
//dot11WEPDefaultKeysTable
{ {1, 3, 1, 1, 1, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 1, 1},
{ {1, 3, 1, 2, 1, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey1), SNMP_SIZE(dot11WEPDefaultKeyLen)},
{ {1, 3, 1, 1, 2, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 2, 1},
{ {1, 3, 1, 2, 2, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey2), SNMP_SIZE(dot11WEPDefaultKeyLen)},
{ {1, 3, 1, 1, 3, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 3, 1},
{ {1, 3, 1, 2, 3, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey3), SNMP_SIZE(dot11WEPDefaultKeyLen)},
{ {1, 3, 1, 1, 4, -1}, "dot11WEPDefaultKeyIndex", MIB_TYPE_VAL, 4, 1},
{ {1, 3, 1, 2, 4, -1}, "dot11WEPDefaultKeyValue", MIB_TYPE_SNMP1, SNMP_OFFSET(dot11WEPDefaultKey4), SNMP_SIZE(dot11WEPDefaultKeyLen)},
//dot11WEPKeyMappingsTable
{ {1, 4, 1, 1, 1, -1}, "dot11WEPKeyMappingIndex", MIB_TYPE_VAL, 1, 1},
{ {1, 4, 1, 2, 1, -1}, "dot11WEPKeyMappingAddress", 0},
{ {1, 4, 1, 3, 1, -1}, "dot11WEPKeyMappingWEPOn", 0},
{ {1, 4, 1, 4, 1, -1}, "dot11WEPKeyMappingValue", 0},
{ {1, 4, 1, 5, 1, -1}, "dot11WEPKeyMappingStatus", 0},
//dot11PrivacyTable
{ {1, 5, 1, 1, 1, -1}, "dot11PrivacyInvoked", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PrivacyInvoked), SNMP_SIZE(dot11PrivacyInvoked)},
{ {1, 5, 1, 2, 1, -1}, "dot11WEPDefaultKeyID", MIB_TYPE_PRIV, PRIV_OFFSET(dot1180211AuthEntry.dot11PrivacyKeyIndex), PRIV_SIZE(dot1180211AuthEntry.dot11PrivacyKeyIndex)},
{ {1, 5, 1, 3, 1, -1}, "dot11WEPKeyMappingLength", MIB_TYPE_VAL, 10, 1},
{ {1, 5, 1, 4, 1, -1}, "dot11ExcludeUnencrypted", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PrivacyInvoked), SNMP_SIZE(dot11PrivacyInvoked)},
{ {1, 5, 1, 5, 1, -1}, "dot11WEPICVErrorCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPICVErrorCount), SNMP_SIZE(dot11WEPICVErrorCount)},
{ {1, 5, 1, 6, 1, -1}, "dot11WEPExcludedCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPExcludedCount), SNMP_SIZE(dot11WEPExcludedCount)},
{ {1, 8, 1, 1, 1, -1}, "dot11WPAKeyIndex", MIB_TYPE_VAL, 1, 1},
{ {1, 8, 1, 2, 1, -1}, "dot11WPAKeyFormat", MIB_TYPE_VAL, 1, 1},
{ {1, 8, 1, 3, 1, -1}, "dot11WPAKeyValue", MIB_TYPE_VAL, 1, 1},
{ {1, 9, 1, 1, 1, -1}, "dot11WPA2KeyIndex", MIB_TYPE_VAL, 1, 1},
{ {1, 9, 1, 2, 1, -1}, "dot11WPA2KeyFormat", MIB_TYPE_VAL, 1, 1},
{ {1, 9, 1, 3, 1, -1}, "dot11WPA2KeyValue", MIB_TYPE_VAL, 1, 1},
{ {1, 10, 1, 1, 1, -1}, "dot11RadiusServerIPAddress", MIB_TYPE_VAL, 1, 1},
{ {1, 10, 1, 2, 1, -1}, "dot11RadiusServerPort", MIB_TYPE_VAL, 1, 1},
{ {1, 10, 1, 3, 1, -1}, "dot11RadiusServerPassword", MIB_TYPE_VAL, 1, 1},
{ {1, 10, 1, 4, 1, -1}, "dot11RadiusServerEnable", MIB_TYPE_VAL, 1, 1},
//dot11OperationTable
{ {2, 1, 1, 1, 1, -1}, "dot11MACAddress", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.hwaddr), PRIV_SIZE(dot11OperationEntry.hwaddr)},
{ {2, 1, 1, 2, 1, -1}, "dot11RTSThreshold", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11RTSThreshold), PRIV_SIZE(dot11OperationEntry.dot11RTSThreshold)},
{ {2, 1, 1, 3, 1, -1}, "dot11ShortRetryLimit", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11ShortRetryLimit), PRIV_SIZE(dot11OperationEntry.dot11ShortRetryLimit)},
{ {2, 1, 1, 4, 1, -1}, "dot11LongRetryLimit", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11LongRetryLimit), PRIV_SIZE(dot11OperationEntry.dot11LongRetryLimit)},
{ {2, 1, 1, 5, 1, -1}, "dot11FragmentationThreshold", MIB_TYPE_PRIV, PRIV_OFFSET(dot11OperationEntry.dot11FragmentationThreshold), PRIV_SIZE(dot11OperationEntry.dot11FragmentationThreshold)},
{ {2, 1, 1, 6, 1, -1}, "dot11MaxTransmitMSDULifetime", MIB_TYPE_VAL, 512, 1},
{ {2, 1, 1, 7, 1, -1}, "dot11MaxReceiveLifetime", MIB_TYPE_VAL, FRAG_TO*10, 4},
{ {2, 1, 1, 8, 1, -1}, "dot11ManufacturerID", MIB_TYPE_VAL, (int)"Realtek", 0},
{ {2, 1, 1, 9, 1, -1}, "dot11ProductID", MIB_TYPE_VAL, (int)"RTL8185/RTL8186", 0},
{ {2, 1, 1, 10, 1, -1}, "dot11IappEnable", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.iapp_enable), PRIV_SIZE(dot11OperationEntry.iapp_enable)},
{ {2, 1, 1, 11, 1, -1}, "dot11BlockRelay", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.block_relay), PRIV_SIZE(dot11OperationEntry.block_relay)},
{ {2, 1, 1, 12, 1, -1}, "dot11WIFISpecific", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.wifi_specific), PRIV_SIZE(dot11OperationEntry.wifi_specific)},
{ {2, 1, 1, 13, 1, -1}, "dot11QosEnable", MIB_TYPE_PRIV,PRIV_OFFSET(dot11QosEntry.dot11QosEnable), PRIV_SIZE(dot11QosEntry.dot11QosEnable)},
{ {2, 1, 1, 14, 1, -1}, "dot11NetworkType", MIB_TYPE_PRIV,PRIV_OFFSET(dot11BssType.net_work_type), PRIV_SIZE(dot11BssType.net_work_type)},
{ {2, 1, 1, 15, 1, -1}, "dot11LedType", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.ledtype), PRIV_SIZE(dot11OperationEntry.ledtype)},
{ {2, 1, 1, 16, 1, -1}, "dot11OperationMode", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.opmode), PRIV_SIZE(dot11OperationEntry.opmode)},
{ {2, 1, 1, 17, 1, -1}, "dot11BroadCastSSID", MIB_TYPE_PRIV,PRIV_OFFSET(miscEntry.show_hidden_bss), PRIV_SIZE(miscEntry.show_hidden_bss)},
{ {2, 1, 1, 18, 1, -1}, "dot11GuestAccess", MIB_TYPE_PRIV,PRIV_OFFSET(dot11OperationEntry.guest_access), PRIV_SIZE(dot11OperationEntry.guest_access)},
//dot11CountersTable
{ {2, 2, 1, 1, 1, -1}, "dot11TransmittedFragmentCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11TransmittedFragmentCount), SNMP_SIZE(dot11TransmittedFragmentCount)},
{ {2, 2, 1, 2, 1, -1}, "dot11MulticastTransmittedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MulticastTransmittedFrameCount), SNMP_SIZE(dot11MulticastTransmittedFrameCount)},
{ {2, 2, 1, 3, 1, -1}, "dot11FailedCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FailedCount), SNMP_SIZE(dot11FailedCount)},
{ {2, 2, 1, 4, 1, -1}, "dot11RetryCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RetryCount), SNMP_SIZE(dot11RetryCount)},
{ {2, 2, 1, 5, 1, -1}, "dot11MultipleRetryCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MultipleRetryCount), SNMP_SIZE(dot11MultipleRetryCount)},
{ {2, 2, 1, 6, 1, -1}, "dot11FrameDuplicateCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FrameDuplicateCount), SNMP_SIZE(dot11FrameDuplicateCount)},
{ {2, 2, 1, 7, 1, -1}, "dot11RTSSuccessCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RTSSuccessCount), SNMP_SIZE(dot11RTSSuccessCount)},
{ {2, 2, 1, 8, 1, -1}, "dot11RTSFailureCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11RTSFailureCount), SNMP_SIZE(dot11RTSFailureCount)},
{ {2, 2, 1, 9, 1, -1}, "dot11ACKFailureCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11ACKFailureCount), SNMP_SIZE(dot11ACKFailureCount)},
{ {2, 2, 1, 10, 1, -1}, "dot11ReceivedFragmentCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11ReceivedFragmentCount), SNMP_SIZE(dot11ReceivedFragmentCount)},
{ {2, 2, 1, 11, 1, -1}, "dot11MulticastReceivedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11MulticastReceivedFrameCount), SNMP_SIZE(dot11MulticastReceivedFrameCount)},
{ {2, 2, 1, 12, 1, -1}, "dot11FCSErrorCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11FCSErrorCount), SNMP_SIZE(dot11FCSErrorCount)},
{ {2, 2, 1, 13, 1, -1}, "dot11TransmittedFrameCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11TransmittedFrameCount), SNMP_SIZE(dot11TransmittedFrameCount)},
{ {2, 2, 1, 14, 1, -1}, "dot11WEPUndecryptableCount", MIB_TYPE_SNMP, SNMP_OFFSET(dot11WEPUndecryptableCount), SNMP_SIZE(dot11WEPUndecryptableCount)},
//dot11GroupAddressesTable
{ {2, 3, 1, 1, 1, -1}, "dot11GroupAddressesIndex", MIB_TYPE_VAL, 1, 1},
{ {2, 3, 1, 2, 1, -1}, "dot11Address", 0},
{ {2, 3, 1, 3, 1, -1}, "dot11GroupAddressesStatus", 0},
{ {3, 1, 1, 0, -1}, "dot11ResourceTypeIDName", MIB_TYPE_VAL, (int)"8185", 0},
//dot11ResourceInfoTable
{ {3, 1, 2, 1, 1, 1, -1}, "dot11manufacturerOUI", MIB_TYPE_VAL, (int)"\x00\xE0\x4C", 3},
{ {3, 1, 2, 1, 2, 1, -1}, "dot11manufacturerName", MIB_TYPE_VAL, (int)"Realtek", 0},
{ {3, 1, 2, 1, 3, 1, -1}, "dot11manufacturerProductName", MIB_TYPE_VAL, (int)"Wireless 802.11 b/g", 0},
{ {3, 1, 2, 1, 4, 1, -1}, "dot11manufacturerProductVersion", MIB_TYPE_VAL, (int)"v1.00", 0},
//dot11PhyOperationTable
{ {4, 1, 1, 1, 1, -1}, "dot11PHYType", MIB_TYPE_VAL, 2, 1},
{ {4, 1, 1, 2, 1, -1}, "dot11CurrentRegDomain", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentRegDomain), SNMP_SIZE(dot11CurrentRegDomain)},
{ {4, 1, 1, 3, 1, -1}, "dot11TempType", MIB_TYPE_VAL, 1, 1},
{ {4, 1, 1, 4, 1, -1}, "dot11ShortPreamble",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.shortpreamble), PRIV_SIZE(dot11RFEntry.shortpreamble)},
{ {4, 1, 1, 5, 1, -1}, "dot11PhyBandSelect",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.phyBandSelect), PRIV_SIZE(dot11RFEntry.phyBandSelect)},
{ {4, 1, 1, 6, 1, -1}, "dot11TrSwitch",MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.trswitch), PRIV_SIZE(dot11RFEntry.trswitch)},
{ {4, 1, 1, 7, 1, -1}, "dot11PowerScale", MIB_TYPE_SNMP, SNMP_OFFSET(dot11PowerScale), SNMP_SIZE(dot11PowerScale)},
//dot11PhyAntennaTable
{ {4, 2, 1, 1, 1, -1}, "dot11CurrentTxAntenna", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentTxAntenna), SNMP_SIZE(dot11CurrentTxAntenna)},
{ {4, 2, 1, 2, 1, -1}, "dot11DiversitySupport", MIB_TYPE_VAL, 2, 1},
{ {4, 2, 1, 3, 1, -1}, "dot11CurrentRxAntenna", MIB_TYPE_SNMP, SNMP_OFFSET(dot11CurrentTxAntenna), SNMP_SIZE(dot11CurrentTxAntenna)},
//dot11PhyTxPowerTable
{ {4, 3, 1, 1, 1, -1}, "dot11NumberSupportedPowerLevels", MIB_TYPE_VAL, 4, 1},
{ {4, 3, 1, 2, 1, -1}, "dot11TxPowerLevel1", MIB_TYPE_VAL, 25, 1},
{ {4, 3, 1, 3, 1, -1}, "dot11TxPowerLevel2", MIB_TYPE_VAL, 12, 1},
{ {4, 3, 1, 4, 1, -1}, "dot11TxPowerLevel3", MIB_TYPE_VAL, 6, 1},
{ {4, 3, 1, 5, 1, -1}, "dot11TxPowerLevel4", MIB_TYPE_VAL, 3, 1},
{ {4, 3, 1, 6, 1, -1}, "dot11TxPowerLevel5", MIB_TYPE_VAL, 0, 1},
{ {4, 3, 1, 7, 1, -1}, "dot11TxPowerLevel6", MIB_TYPE_VAL, 0, 1},
{ {4, 3, 1, 8, 1, -1}, "dot11TxPowerLevel7", MIB_TYPE_VAL, 0, 1},
{ {4, 3, 1, 9, 1, -1}, "dot11TxPowerLevel8", MIB_TYPE_VAL, 0, 1},
{ {4, 3, 1, 10, 1, -1}, "dot11CurrentTxPowerLevel", 0}, // NCTU
//dot11PhyDSSSTable
{ {4, 5, 1, 1, 1, -1}, "dot11CurrentChannel", MIB_TYPE_PRIV, PRIV_OFFSET(dot11RFEntry.dot11channel), PRIV_SIZE(dot11RFEntry.dot11channel)},
{ {4, 5, 1, 2, 1, -1}, "dot11CCAModeSupported", MIB_TYPE_VAL, 4, 1},
{ {4, 5, 1, 3, 1, -1}, "dot11CurrentCCAMode", MIB_TYPE_VAL, 4, 1},
{ {4, 5, 1, 4, 1, -1}, "dot11EDThreshold", MIB_TYPE_VAL, 0, 1},
//dot11RegDomainsSupportedTable
{ {4, 7, 1, 1, 1, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 1, 1},
{ {4, 7, 1, 2, 1, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 16, 1},
{ {4, 7, 1, 1, 2, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 2, 1},
{ {4, 7, 1, 2, 2, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 32, 1},
{ {4, 7, 1, 1, 3, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 3, 1},
{ {4, 7, 1, 2, 3, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 48, 1},
{ {4, 7, 1, 1, 4, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 4, 1},
{ {4, 7, 1, 2, 4, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 49, 1},
{ {4, 7, 1, 1, 5, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 5, 1},
{ {4, 7, 1, 2, 5, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 50, 1},
{ {4, 7, 1, 1, 6, -1}, "dot11RegDomainsSupportIndex", MIB_TYPE_VAL, 6, 1},
{ {4, 7, 1, 2, 6, -1}, "dot11RegDomainsSupportValue", MIB_TYPE_VAL, 64, 1},
//dot11AntennasListTable
{ {4, 8, 1, 1, 1, -1}, "dot11AntennaListIndex", MIB_TYPE_VAL, 1, 1},
{ {4, 8, 1, 2, 1, -1}, "dot11SupportedTxAntenna", MIB_TYPE_VAL, 1, 1},
{ {4, 8, 1, 3, 1, -1}, "dot11SupportedRxAntenna", MIB_TYPE_VAL, 1, 1},
{ {4, 8, 1, 4, 1, -1}, "dot11DiversitySelectionRx", MIB_TYPE_VAL, 1, 1},
//dot11SupportedDataRatesTxTable
{ {4, 9, 1, 1, 1, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 1, 1},
{ {4, 9, 1, 2, 1, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[0]), 4},
{ {4, 9, 1, 1, 2, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 2, 1},
{ {4, 9, 1, 2, 2, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[1]), 4},
{ {4, 9, 1, 1, 3, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 3, 1},
{ {4, 9, 1, 2, 3, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[2]), 4},
{ {4, 9, 1, 1, 4, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 4, 1},
{ {4, 9, 1, 2, 4, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[3]), 4},
{ {4, 9, 1, 1, 5, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 5, 1},
{ {4, 9, 1, 2, 5, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[4]), 4},
{ {4, 9, 1, 1, 6, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 6, 1},
{ {4, 9, 1, 2, 6, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[5]), 4},
{ {4, 9, 1, 1, 7, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 7, 1},
{ {4, 9, 1, 2, 7, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[6]), 4},
{ {4, 9, 1, 1, 8, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 8, 1},
{ {4, 9, 1, 2, 8, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[7]), 4},
{ {4, 9, 1, 1, 9, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 9, 1},
{ {4, 9, 1, 2, 9, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[8]), 4},
{ {4, 9, 1, 1, 10, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 10, 1},
{ {4, 9, 1, 2, 10, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[9]), 4},
{ {4, 9, 1, 1, 11, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 11, 1},
{ {4, 9, 1, 2, 11, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[10]), 4},
{ {4, 9, 1, 1, 12, -1}, "dot11SupportedDataRatesTxIndex", MIB_TYPE_VAL, 12, 1},
{ {4, 9, 1, 2, 12, -1}, "dot11SupportedDataRatesTxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[11]), 4},
//dot11SupportedDataRatesRxTable
{ {4, 10, 1, 1, 1, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 1, 1},
{ {4, 10, 1, 2, 1, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[0]), 4},
{ {4, 10, 1, 1, 2, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 2, 1},
{ {4, 10, 1, 2, 2, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[1]), 4},
{ {4, 10, 1, 1, 3, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 3, 1},
{ {4, 10, 1, 2, 3, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[2]), 4},
{ {4, 10, 1, 1, 4, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 4, 1},
{ {4, 10, 1, 2, 4, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[3]), 4},
{ {4, 10, 1, 1, 5, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 5, 1},
{ {4, 10, 1, 2, 5, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[4]), 4},
{ {4, 10, 1, 1, 6, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 6, 1},
{ {4, 10, 1, 2, 6, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[5]), 4},
{ {4, 10, 1, 1, 7, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 7, 1},
{ {4, 10, 1, 2, 7, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[6]), 4},
{ {4, 10, 1, 1, 8, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 8, 1},
{ {4, 10, 1, 2, 8, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[7]), 4},
{ {4, 10, 1, 1, 9, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 9, 1},
{ {4, 10, 1, 2, 9, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[8]), 4},
{ {4, 10, 1, 1, 10, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 10, 1},
{ {4, 10, 1, 2, 10, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[9]), 4},
{ {4, 10, 1, 1, 11, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 11, 1},
{ {4, 10, 1, 2, 11, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[10]), 4},
{ {4, 10, 1, 1, 12, -1}, "dot11SupportedDataRatesRxIndex", MIB_TYPE_VAL, 12, 1},
{ {4, 10, 1, 2, 12, -1}, "dot11SupportedDataRatesRxValue", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesSet[11]), 4},
// Number of table entry, Realtek proprietary
{ {6, 1, -1}, "dot11StationConfigEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 2, -1}, "dot11AuthenticationAlgorithmsEntryNum", MIB_TYPE_VAL, 2, 1},
{ {6, 3, -1}, "dot11WEPDefaultKeysEntryNum", MIB_TYPE_VAL, 4, 1},
{ {6, 4, -1}, "dot11WEPKeyMappingsEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 5, -1}, "dot11PrivacyEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 6, -1}, "dot11OperationEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 7, -1}, "dot11CountersEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 8, -1}, "dot11GroupAddressesEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 9, -1}, "dot11ResourceInfoTableNum", MIB_TYPE_VAL, 1, 1},
{ {6, 10, -1}, "dot11PhyOperationEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 11, -1}, "dot11PhyAntennaEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 12, -1}, "dot11PhyTxPowerEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 13, -1}, "dot11PhyDSSSEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 14, -1}, "dot11RegDomainsSupportEntryNum", MIB_TYPE_VAL, 6, 1},
{ {6, 15, -1}, "dot11AntennasListEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 16, -1}, "dot11AntennasListEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 17, -1}, "dot11SupportedDataRatesTxEntryNum", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesNum), SNMP_SIZE(dot11SupportedDataRatesNum)},
{ {6, 18, -1}, "dot11SupportedDataRatesRxEntryNum", MIB_TYPE_SNMP, SNMP_OFFSET(dot11SupportedDataRatesNum), SNMP_SIZE(dot11SupportedDataRatesNum)},
{ {6, 19, -1}, "dot11MultiDomainCapabilityEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 20, -1}, "dot11WPAKeysEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 21, -1}, "dot11WPA2KeysEntryNum", MIB_TYPE_VAL, 1, 1},
{ {6, 22, -1}, "dot11RadiusServerNum", MIB_TYPE_VAL, 1, 1},
{ {-1}, NULL, 0}
};
static int add_mib_entry(struct rtl8192cd_priv *priv, struct mib_val *ent)
{
int i=0;
struct mib_entry **mib=&priv->snmp_mib.mib_tree, *pre_mib=NULL;
while(1) {
if (ent->oid[i] == -1)
break;
if (*mib == NULL) {
if (priv->snmp_mib.tree_used_index == MAX_MIB_TREE_NUM) {
printk("Exceed max mib tree number\n");
return -1;
}
*mib = &priv->snmp_mib.mib_list[priv->snmp_mib.tree_used_index++];
}
if ((*mib)->id == -1 || ent->oid[i] == (*mib)->id) {
if ((*mib)->id == -1)
(*mib)->id = ent->oid[i];
i++;
pre_mib = *mib;
mib = &((*mib)->next_level);
}
else
mib = &((*mib)->next_node);
}
if (pre_mib == NULL) {
printk("build mib tree error, no parent mib found!\n");
return -1;
}
if (pre_mib->val) {
printk("build mib tree error, mib value has been assigned!\n");
return -1;
}
pre_mib->val = ent;
return 0;
}
static void name2oid(char *name, int *oid)
{
int i=0;
char *src=name, *ptr;
while (*src) {
ptr = strstr(src, ".");
if (ptr)
*ptr = '\0';
oid[i++] = _atoi(src, 10);
if (ptr==NULL)
break;
src = ++ptr;
}
oid[i] = -1;
}
static struct mib_val *search_mib(struct rtl8192cd_priv *priv, char *id)
{
int i=0;
struct mib_entry *mib=priv->snmp_mib.mib_tree, *pre_mib=NULL;
int oid[100];
name2oid(id, oid);
while (oid[i] != -1) {
if (mib == NULL || mib->id == -1)
return NULL;
if (mib->id == oid[i]) {
pre_mib = mib;
mib = mib->next_level;
i++;
}
else {
pre_mib = NULL;
mib = mib->next_node;
}
}
if (pre_mib && pre_mib->val)
return pre_mib->val;
else
return NULL;
}
static void build_tree(struct rtl8192cd_priv *priv)
{
int i=0;
struct mib_val *tbl = dot11_mib_table;
for (i=0; i<MAX_MIB_TREE_NUM; i++)
priv->snmp_mib.mib_list[i].id = -1;
i=0;
while (tbl[i].name) {
if (add_mib_entry(priv, &tbl[i]) < 0) {
printk("Add mib entry failed [%s]!\n", tbl[i].name);
return;
}
i++;
}
// printk("used mib num = %d\n", priv->snmp_mib.tree_used_index);
}
int mib_get(struct rtl8192cd_priv *priv, char *oid, unsigned char *data, int *pLen)
{
int iVal;
unsigned char bVal, *pVal, *pVal_type=data++;
struct mib_val *mib;
mib = search_mib(priv, oid);
if (mib == NULL) {
printk("search mib failed [oid=%s]!\n", oid);
return 0;
}
*pVal_type = VAL_OCTET;
switch (mib->type) {
case MIB_TYPE_PRIV:
if (mib->size)
*pLen = mib->size;
else {
*pLen = strlen(((unsigned char *)priv->pmib)+mib->offset)+1;
*pVal_type = VAL_STR;
}
memcpy(data, ((unsigned char *)priv->pmib)+mib->offset, *pLen);
break;
case MIB_TYPE_SNMP:
case MIB_TYPE_SNMP1:
if (mib->type == MIB_TYPE_SNMP1) {
bVal = *(((unsigned char *)&priv->snmp_mib)+mib->size);
*pLen = (int)bVal;
}
else if (mib->size > 0)
*pLen = mib->size;
else if (mib->size == 0) {
*pLen = strlen(((unsigned char *)&priv->snmp_mib)+mib->offset) + 1;
*pVal_type = VAL_STR;
}
memcpy(data, ((unsigned char *)&priv->snmp_mib)+mib->offset, *pLen);
break;
case MIB_TYPE_VAL:
if (mib->size == 0) {
pVal = (unsigned char *)mib->offset;
*pLen = strlen(pVal) + 1;
memcpy(data, pVal, *pLen);
*pVal_type = VAL_STR;
} else if (mib->size == 1) {
bVal = (unsigned char)mib->offset;
pVal = &bVal;
*pLen = sizeof(bVal);
}
else {
iVal = mib->offset;
pVal = (unsigned char *)&iVal;
*pLen = sizeof(iVal);
}
memcpy(data, pVal, *pLen);
break;
default:
// printk("Invalid mib type [%d, %s]\n", mib->type, mib->name);
*pVal_type = VAL_NULL;
*pLen = 0;
break;
}
#if 0
{
int i;
printk("name=%s, val_type=%d, len=%d", mib->name, *pVal_type, *pLen);
if (*pVal_type == VAL_STR)
printk(", val=%s\n", data);
else {
printk(", val=");
for (i=0; i<*pLen; i++) {
printk("%02x ", data[i]);
}
printk("\n");
}
}
#endif
*pLen += 1;
return 1;
}
// build tree and mapping mib value from priv to dot11
void mib_init(struct rtl8192cd_priv *priv)
{
int val;
memset(&priv->snmp_mib, '\0', sizeof(struct mib_snmp));
build_tree(priv);
if ((OPMODE & WIFI_AP_STATE) || (OPMODE & WIFI_STATION_STATE))
SNMP_MIB_ASSIGN(dot11DesiredBSSType, 1); // infra
else
SNMP_MIB_ASSIGN(dot11DesiredBSSType, 2); // ad-hoc
if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm > 0)
SNMP_MIB_ASSIGN(dot11PrivacyInvoked, 1);
if (priv->pmib->dot1180211AuthEntry.dot11AuthAlgrthm == 1) // shared key
SNMP_MIB_ASSIGN(dot11AuthenticationAlgorithmsEnableShared, 1);
else
SNMP_MIB_ASSIGN(dot11AuthenticationAlgorithmsEnableOpen, 1);
if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_40_PRIVACY_) {
SNMP_MIB_COPY(dot11WEPDefaultKey1, &priv->pmib->dot11DefaultKeysTable.keytype[0].skey[0], 5);
SNMP_MIB_COPY(dot11WEPDefaultKey2, &priv->pmib->dot11DefaultKeysTable.keytype[1].skey[0], 5);
SNMP_MIB_COPY(dot11WEPDefaultKey3, &priv->pmib->dot11DefaultKeysTable.keytype[2].skey[0], 5);
SNMP_MIB_COPY(dot11WEPDefaultKey4, &priv->pmib->dot11DefaultKeysTable.keytype[3].skey[0], 5);
SNMP_MIB_ASSIGN(dot11WEPDefaultKeyLen, 5);
}
else if (priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm == _WEP_104_PRIVACY_) {
SNMP_MIB_COPY(dot11WEPDefaultKey1, &priv->pmib->dot11DefaultKeysTable.keytype[0].skey[0], 13);
SNMP_MIB_COPY(dot11WEPDefaultKey2, &priv->pmib->dot11DefaultKeysTable.keytype[1].skey[0], 13);
SNMP_MIB_COPY(dot11WEPDefaultKey3, &priv->pmib->dot11DefaultKeysTable.keytype[2].skey[0], 13);
SNMP_MIB_COPY(dot11WEPDefaultKey4, &priv->pmib->dot11DefaultKeysTable.keytype[3].skey[0], 13);
SNMP_MIB_ASSIGN(dot11WEPDefaultKeyLen, 13);
}
get_oper_rate(priv);
switch(priv->pmib->dot11StationConfigEntry.dot11RegDomain) {
case DOMAIN_FCC:
val = 16;
break;
case DOMAIN_IC:
val = 32;
break;
case DOMAIN_ETSI:
val = 48;
break;
case DOMAIN_SPAIN:
val = 49;
break;
case DOMAIN_FRANCE:
val = 50;
break;
case DOMAIN_MKK:
case DOMAIN_MKK1:
case DOMAIN_MKK2:
case DOMAIN_MKK3:
val = 64;
break;
default:
printk("Invalid dot11RegDomain [%d]!\n", priv->pmib->dot11StationConfigEntry.dot11RegDomain);
val = 16;
break;
}
SNMP_MIB_ASSIGN(dot11CurrentRegDomain, val);
SNMP_MIB_ASSIGN(dot11CurrentTxAntenna, priv->pmib->dot11RFEntry.defaultAntennaB+1);
}
#endif // SUPPORT_SNMP_MIB
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_mib.h
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/*
* Header files of SNMP MIB module
*
* $Id: 8192cd_mib.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_MIB_H_
#define _8192CD_MIB_H_
#define MAX_MIB_TREE_NUM 580
#define MAX_OID_LEVEL 10
#define PRIV_OFFSET(field) ((int)(long *)&(((struct wifi_mib *)0)->field))
#define PRIV_SIZE(field) sizeof(((struct wifi_mib *)0)->field)
#define SNMP_OFFSET(field) ((int)(long *)&(((struct mib_snmp *)0)->field))
#define SNMP_SIZE(field) sizeof(((struct mib_snmp *)0)->field)
enum { MIB_TYPE_VAL=1, MIB_TYPE_PRIV, MIB_TYPE_SNMP, MIB_TYPE_SNMP1 };
enum { VAL_OCTET, VAL_STR, VAL_NULL };
struct mib_entry {
int id;
struct mib_entry *next_level;
struct mib_entry *next_node;
struct mib_val *val;
};
struct mib_val {
int oid[MAX_OID_LEVEL];
char *name;
int type;
int offset;
int size;
};
struct mib_snmp {
unsigned char dot11AuthenticationAlgorithmsEnableOpen;
unsigned char dot11AuthenticationAlgorithmsEnableShared;
unsigned char dot11WEPDefaultKey1[13];
unsigned char dot11WEPDefaultKey2[13];
unsigned char dot11WEPDefaultKey3[13];
unsigned char dot11WEPDefaultKey4[13];
unsigned char dot11WEPDefaultKeyLen;
unsigned char dot11SupportedDataRatesNum;
unsigned int dot11SupportedDataRatesSet[12];
unsigned char dot11OperationalRateSet[12];
int dot11DesiredBSSType;
int dot11DisassociateReason;
unsigned char dot11DisassociateStation[6];
int dot11DeauthenticateReason;
unsigned char dot11DeauthenticateStation[6];
int dot11AuthenticateFailStatus;
unsigned char dot11AuthenticateFailStation[6];
int dot11PrivacyInvoked;
int dot11WEPICVErrorCount;
int dot11WEPExcludedCount;
int dot11TransmittedFragmentCount;
int dot11MulticastTransmittedFrameCount;
int dot11FailedCount;
int dot11RetryCount;
int dot11MultipleRetryCount;
int dot11FrameDuplicateCount;
int dot11RTSSuccessCount;
int dot11RTSFailureCount;
int dot11ACKFailureCount;
int dot11ReceivedFragmentCount;
int dot11MulticastReceivedFrameCount;
int dot11FCSErrorCount;
int dot11TransmittedFrameCount;
int dot11WEPUndecryptableCount;
int dot11CurrentRegDomain;
int dot11CurrentTxAntenna;
int dot11DataRate;
int dot11PowerScale;
struct mib_entry mib_list[MAX_MIB_TREE_NUM];
int tree_used_index;
struct mib_entry *mib_tree;
};
#endif // _8192CD_MIB_H_
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_mp.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_net80211.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_net80211.h
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/*
* Header file for Net80211-compatible handling routines
*
*
*
* Copyright (c) 2010 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_NET80211_H_
#define _8192CD_NET80211_H_
#include <net/iw_handler.h>
#define MAX_CONFIG_FILE_SIZE (20*1024) // for 8192, added to 20k
#define MAX_PARAM_BUF_SIZE (1024) // for 8192, added to 20k
#ifdef RTK_NL80211
#define RTK_CIPHER_PTK 1
#define RTK_CIPHER_GTK 2
#define RTK_CIPHER_IGTK 4
#endif
int rtl_net80211_setparam(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
int rtl_net80211_setappiebuf(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
int rtl_net80211_setmlme(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
int rtl_net80211_setkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
int rtl_net80211_delkey(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
int rtl_net80211_wdsaddmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
int rtl_net80211_wdsdelmac(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
int rtl_net80211_getwpaie(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
int rtl_hapd_config(struct net_device *dev, struct iw_request_info *info, union iwreq_data *wrqu, char *extra);
void rsn_init(struct rtl8192cd_priv *priv);
#if defined(RTK_NL80211)
int rtl_wpas_join(struct rtl8192cd_priv *priv, int bss_num);
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_osdep.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_p2p.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_p2p.h
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/*
* Header file define some p2p struct define inline functions
*
* $Id: 8192cd_p2p.h,v 1.2 2010/12/21
*
* Copyright (c) 2010 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_P2P_H_
#define _8192CD_P2P_H_
#include "./8192cd_cfg.h"
#include "./8192cd.h"
//#include "./wps/wsc.h"
/*============== will redeclare with wsc.h ==================*/
#define P2P_WILDCARD_SSID_LEN 7
#define P2P_IE_ID 221
#define MAC_LEN 6
#define UUID_LEN 16
#define MAX_MANUFACT_LEN 64
#define MAX_MODEL_NAME_LEN 32
#define MAX_MODEL_NUM_LEN 32
#define MAX_SERIAL_NUM_LEN 32
#define MAX_DEVICE_NAME_LEN 32
#define WSC_IE_ID 221
#define WSC_VER 0x10
#define TAG_SIMPLE_CONFIG_STATE 0x1044
#define TAG_RESPONSE_TYPE2 0x103B
#define TAG_UUID_E 0x1047
#define TAG_MANUFACTURER 0x1021
#define TAG_MODEL_NAME 0x1023
#define TAG_MODEL_NUMBER 0x1024
#define TAG_SERIAL_NUM 0x1042
#define TAG_PRIMARY_DEVICE_TYPE 0x1054
#define TAG_DEVICE_NAME 0x1011
#define TAG_CONFIG_METHODS 0x1008
#define TAG_VERSION 0x104A
#define TAG_DEVICE_PASSWORD_ID 0x1012
#define TAG_SEC_DEVICE_TYPE_LIST 0x1055
#define WFA_OUI_LEN 3
#define WFA_OUI_PLUS_TYPE_LEN 4
#define MAX_NOA_DESC_MUN 6
#define MAX_P2P_CLIENT_MUN 5
#define CLIENT_MODE_WAIT_TIME 30
#define WSC_MODE_WAIT_TIME 60*2
#define P2P_CLIENT_ASSOC_EXPIRE 120
#define P2P_device_category_id_AP 6
#define P2P_device_category_id_STA 1
#define P2P_device_sub_category_id 1
/*for P2P IE attribute ID0 use*/
enum p2p_status_code {
P2P_SC_SUCCESS = 0,
P2P_SC_FAIL_INFO_CURRENTLY_UNAVAILABLE = 1,
P2P_SC_FAIL_INCOMPATIBLE_PARAMS = 2,
P2P_SC_FAIL_LIMIT_REACHED = 3,
P2P_SC_FAIL_INVALID_PARAMS = 4,
P2P_SC_FAIL_UNABLE_TO_ACCOMMODATE = 5,
P2P_SC_FAIL_PREV_PROTOCOL_ERROR = 6,
P2P_SC_FAIL_NO_COMMON_CHANNELS = 7,
P2P_SC_FAIL_UNKNOWN_GROUP = 8,
P2P_SC_FAIL_BOTH_GO_INTENT_15 = 9,
P2P_SC_FAIL_INCOMPATIBLE_PROV_METHOD = 10,
P2P_SC_FAIL_REJECTED_BY_USER = 11,
};
/*for P2P IE attribute ID1 use*/
enum p2p_minor_reason{
minor_case1 =1,
minor_case2 =2,
minor_case3 =3,
minor_case4 =4
};
/* P2P public action frames ;
these type frames no need assoc we must process*/
enum p2p_public_action_frame {
P2P_GO_NEG_REQ = 0,
P2P_GO_NEG_RESP = 1,
P2P_GO_NEG_CONF = 2,
P2P_INVITATION_REQ = 3,
P2P_INVITATION_RESP = 4,
P2P_DEV_DISC_REQ = 5,
P2P_DEV_DISC_RESP = 6,
P2P_PROV_DISC_REQ = 7,
P2P_PROV_DISC_RSP = 8
};
/* P2P action frames ,we process these type frames after assoc*/
enum p2p_action_frame{
P2P_NOA = 0,
P2P_PRESENCE_REQ = 1,
P2P_PRESENCE_RSP = 2,
P2P_GO_DISCOVERY = 3
/*4-255 reserved*/
};
enum {
RSP_TYPE_ENR,
RSP_TYPE_ENR_1X,
RSP_TYPE_REG,
RSP_TYPE_AP
};
// wsc passwd ID
enum {
PASS_ID_DEFAULT, // 0
PASS_ID_USER, // 1
PASS_ID_MACHINE, // 2
PASS_ID_REKEY, // 3
PASS_ID_PB, // 4
PASS_ID_REG, // 5
PASS_ID_RESERVED // 6
};
// need sync with wscd
enum {
GO_WPS_SUCCESS = 1,
GO_WPS_FAIL = 2
};
enum {
CONFIG_METHOD_ETH=0x2,
CONFIG_METHOD_PIN=0x4, // label(PIN)
CONFIG_METHOD_DISPLAY=0x8 ,// (PISPLAY)
CONFIG_METHOD_PBC=0x80,
CONFIG_METHOD_KEYPAD=0x100,
/*add for wps2.x*/
CONFIG_METHOD_VIRTUAL_PBC=0x280 ,
CONFIG_METHOD_PHYSICAL_PBC=0x480,
CONFIG_METHOD_VIRTUAL_PIN=0x2008,
CONFIG_METHOD_PHYSICAL_PIN=0x4008
};
enum p2p_role_s {
R_P2P_GO =1 ,
R_P2P_DEVICE = 2,
R_P2P_CLIENT =3
};
enum p2p_role_more{
P2P_DEVICE=1,
P2P_PRE_CLIENT=2,
P2P_CLIENT=3,
P2P_PRE_GO=4, // after GO nego , we are GO and proceed WSC exchange
P2P_TMP_GO=5 // after GO nego , we are GO and proceed WSC exchange is done
};
// need sync with web server utility.h
enum {
P2P_S_IDLE = 0, /* between state and state */
P2P_S_LISTEN , /*1 listen state */
P2P_S_SCAN , /*2 Scan state */
P2P_S_SEARCH , /*3 Search state*/
// 4~14 ; show status 4 in web page
P2P_S_PROVI_TX_REQ , /*4 send provision req*/
P2P_S_PROVI_WAIT_RSP , /*5 wait provision rsp*/
P2P_S_PROVI_RX_RSP , /*6 rx provision rsp*/
P2P_S_PROVI_RX_REQ , /*7 received provision req*/
P2P_S_PROVI_TX_RSP , /*8 send provision rsp*/
P2P_S_NEGO_TX_REQ , /*9 send NEGO req*/
P2P_S_NEGO_WAIT_RSP , /*10 waiting for NEGO rsp*/
P2P_S_NEGO_TX_CONF , /*11 send NEGO confirm*/
P2P_S_NEGO_RX_REQ , /*12 rx NEGO req */
P2P_S_NEGO_TX_RSP , /*13 send NEGO rsp */
P2P_S_NEGO_WAIT_CONF , /*14 wait NEGO conf */
// 15~16 ; show status 5 in web page
P2P_S_CLIENT_CONNECTED_DHCPC , /*15 p2p client Rdy connected */
P2P_S_CLIENT_CONNECTED_DHCPC_done, /*16 p2p client Rdy connected */
// 17~18 ; show status 6 in web page
P2P_S_preGO2GO_DHCPD , /*17 GO not start dhcpd yet */
P2P_S_preGO2GO_DHCPD_done, /*18 GO rdy start dhcpd*/
P2P_S_back2dev /*exceed 20 seconds p2p client can't connected*/
};
enum {
P2P_EVENT_RX_PROVI_REQ = 1 /* received provision req*/
};
enum {
WPS_MODE_NO_CHANGE=0,
MODE_AP_UNCONFIG=1, // AP unconfigured (enrollee)
MODE_CLIENT_UNCONFIG=2, // client unconfigured (enrollee)
MODE_CLIENT_CONFIG=3, // client configured (registrar)
MODE_AP_PROXY=4, // AP configured (proxy)
MODE_AP_PROXY_REGISTRAR=5, // AP configured (proxy and registrar)
MODE_CLIENT_UNCONFIG_REGISTRAR=6 // client unconfigured (registrar)
};
enum {
P2P_PIN_METHOD = 1,
P2P_PBC_METHOD = 2
};
enum {
USE_TARGET_PIN = 1,
USE_MY_PIN = 2
};
enum {
P2P_GO_PS_NONE,
P2P_GO_PS_OPPPS,
P2P_GO_PS_NP_NOA,
P2P_GO_PS_CONT_NOA,
P2P_GO_PS_NOA
};
/*==================================================================*/
/*=====================commu with web UI start===========================*/
/* Any changed here MUST sync with web server utility.h */
struct p2p_state_event{
unsigned char p2p_status;
unsigned char p2p_event;
unsigned short p2p_wsc_method;
unsigned char p2p_role;
};
struct __p2p_wsc_confirm
{
unsigned char dev_address[MAC_LEN];
unsigned short wsc_config_method;
unsigned char pincode[9];
};
/*=====================commu with web UI end===========================*/
/*reg_class - Regulatory class (IEEE 802.11-2007, Annex J)
P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */
#define P2P_MAX_REG_CLASSES 10
/*P2P_MAX_REG_CLASS_CHANNELS -
Maximum number of channels per regulatory class */
#define P2P_MAX_REG_CLASS_CHANNELS 20
struct p2p_reg_class {
/*reg_class - Regulatory class (IEEE 802.11-2007, Annex J)*/
unsigned char reg_class;
/* channels - Number of channel entries in use */
unsigned char channel_mun;
/* channel - Supported channels */
unsigned char channel[P2P_MAX_REG_CLASS_CHANNELS];
};
/* struct p2p_channels - List of supported channels */
struct p2p_channels {
unsigned short Id11_len;
char country[3];
/* reg_classes - Number of reg_class entries in use
corresponding to table 25(page 89) number of channels*/
unsigned char reg_class_mun;
/* struct p2p_reg_class - Supported regulatory class*/
struct p2p_reg_class reg_class[P2P_MAX_REG_CLASSES];
};
/*============== will redeclare with wsc.h ==================*/
/*P2P TAG*/
#define TAG_STATUE 0
#define TAG_MINOR_RES_CODE 1
#define TAG_P2P_CAPABILITY 2
#define TAG_DEVICE_ID 3
#define TAG_GROUP_OWNER_INTENT 4
#define TAG_CONFIG_TIMEOUT 5
#define TAG_LISTEN_CHANNEL 6
#define TAG_P2P_GROUP_BSSID 7
#define TAG_EXT_LISTEN_TIMING 8
#define TAG_INTEN_P2P_INTERFACE_ADDR 9
#define TAG_P2P_MANAGEABILITY 10
#define TAG_CHANNEL_LIST 11
#define TAG_NOTICE_OF_ABSENCE 12
#define TAG_P2P_DEVICE_INFO 13
#define TAG_P2P_GROUP_INFO 14
#define TAG_P2P_GROUP_ID 15
#define TAG_P2P_INTERFACE 16
#define TAG_OPERATION_CHANNEL 17
#define TAG_INVITATION_FLAGS 18
/* for P2P Capability attr*/
/*dev cap*/
#define SUPPORT_P2P_INVITATION (BIT(5))
#define CLIENT_DISCOVERY (BIT(1))
/*group cap*/
#define GCAP_GO (BIT(0))
#define GCAP_PRESISTENT_GO (BIT(1))
#define GCAP_GROUP_LIMIT (BIT(2))
#define GCAP_IBSS_DIST (BIT(3))
#define GCAP_GO_FORMATION (BIT(6))
struct provision_comm
{
unsigned char dev_address[MAC_LEN];
unsigned short wsc_config_method;
unsigned char channel;
};
#define MAX_SEC_DEV_TYPE 3
struct device_info_s
{
unsigned char dev_address[6] ; //
unsigned short config_method; /*which wsc config method can provided*/
unsigned char pri_dev_type[8]; /*primary device type*/
unsigned char sdv_mun;
unsigned char sec_dev_type[MAX_SEC_DEV_TYPE][8]; /*we keep 3 sets (second device type)*/
char devname[33];
};
/* need sync with wsc.h */
typedef struct _DOT11_P2P_INDICATE_WSC{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char modeSwitch ;
unsigned char network_key[65] ;
unsigned char gossid[33] ;
unsigned char trigger_method ;
unsigned char whosPINuse ;
unsigned char PINCode[9] ;
unsigned char requestor;
}DOT11_P2P_INDICATE_WSC;
typedef struct p2p_device_peer {
unsigned char inuse;
unsigned char dev_addr[6];
unsigned char dialog_token;
int role; /* p2p is which role */
/*attribute ID 0 Status*/
int status; /* enum p2p_status_code */
/*attribute ID 2*/
unsigned char dev_capab; /* device capability*/
unsigned char group_capab; /* group capability*/
/*attribute ID3 device ID*/
//unsigned char device_address_to_find[6] ;
/*attribute ID4 GO intent value*/
unsigned char intent_value;
unsigned char TieBreak;
/*attribute ID5 configure timeout*/
unsigned char go_config_timeout;
unsigned char client_config_timeout;
/*attribute ID6 configure timeout*/
int operating_class; // frequency band
int listen_channle; //
/*attribute ID7 group BSSID*/
unsigned char go_bssid[6];
/*attribute ID8 extended listen timing*/
unsigned short avail_period;
unsigned short avail_interval;
/*attribute ID9 intented p2p interface address*/
unsigned char p2p_interface_address[6] ;
/*attribute ID10 manageability*/
unsigned char manageability ; // bit(0)|bit(1)|bit(2)|
/*attribute ID11 channel list*/
/* Country code to use in P2P operations */
struct p2p_channels channels_list;
/*attribute ID 12 Notice of Absence*/
unsigned char noa_index ; /* noa index */
unsigned char noa_ct_oops ; /* noa ctwindows and oops */
unsigned char noa_desc_count ; /* noa count of noa descriptor*/
unsigned char noa_desc[2][13] ; /* noa descriptor ; a go max has two desc simultaneously*/
/*attribute ID 13 device info*/
struct device_info_s peer_device_info;
/*attribute ID 14 group info ; more Id14's attr can represent at ID13 */
//unsigned short p2p_interface_address[6] ; // represent at ID9
/*attribute ID 15 group ID */
unsigned char group_bssid[6];
unsigned char group_ssid[33];
unsigned char group_ssid_len;
/*attribute ID 16 group ID */
unsigned char interface_addr_num;
unsigned char p2p_interface_add_list[2][6] ;
/*attribute ID 17 operating channel */
unsigned char op_country[4];
unsigned char op_class;
unsigned char op_channel;
/*attribute ID 18 invitation flags*/
unsigned char invitation_flag;
/*wsc IE */
unsigned short wsc_config_method;
unsigned short device_pass_id;
}P2P_DEV_T, *P2P_DEV_Tp;
/*
in discovery phase , we can just recored the necessity info
*/
struct assoc_peer
{
unsigned char inuse;
// ID2
unsigned char dev_cap;
unsigned char group_cap;
// ID13
struct device_info_s devInfo;
unsigned char if_addr[6];
};
struct noa_desc
{
unsigned char count;
unsigned int duration;
unsigned int interval;
unsigned int starttime;
};
// ID12
struct noa_list
{
unsigned char index;
unsigned char CTWindow_OppPs; /*bit7 OppPS bit(0-6) CTWindows*/
struct noa_desc noa_descs;
unsigned int go_ps_type;
unsigned int noa_counter;
unsigned int p2p_txpause_flag;
};
struct p2p_context {
#ifdef RTK_NL80211
/*=========remain on channel related========*/
struct timer_list remain_on_ch_timer;
u8 restore_channel;
struct ieee80211_channel remain_on_ch_channel;
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)
enum nl80211_channel_type remain_on_ch_type;
#endif
u64 remain_on_ch_cookie;
/*=========remain on channel related========*/
struct timer_list scan_deny_timer;
u64 send_action_id;
//struct cfg80211_wifidirect_info cfg80211_wdinfo;
#endif
unsigned int Status;
unsigned char wsc_ie_rsp[200]; // full size maybe 32 + 8 + 8
unsigned char wsc_ie_rsp_mun; // use for action frame (eg nego rsp)
unsigned char wsc_ie_req[200]; // full size maybe 32 + 8 + 8
unsigned char wsc_ie_req_mun; // use for action frame (eg nego rsp)
unsigned char p2p_probe_req_ie[256];
unsigned int p2p_probe_req_ie_len;
unsigned char p2p_probe_rsp_ie[256];
unsigned int p2p_probe_rsp_ie_len;
unsigned char p2p_beacon_ie[64];
unsigned int p2p_beacon_ie_len;
unsigned char p2p_assocReq_ie[128];
unsigned int p2p_assocReq_ie_len;
unsigned char p2p_assoc_RspIe[32];
unsigned int p2p_assoc_RspIe_len;
unsigned char p2p_disass_ie[64];
unsigned int p2p_disass_ie_len;
int wait2listenState;
unsigned int collect_type; // 1:from beacon ; 2:from probe_rsp
unsigned int rdyinit;
/*when i am GO and some p2p client assoc to me ; recored here*/
struct assoc_peer assocPeers[MAX_P2P_CLIENT_MUN];
/*when i am GO and some p2p dev probe_req me */
unsigned char probe_rps_to_p2p_dev;
/*when i am client record noa from beacon */
struct noa_list noa_list_t;
int pre_client_timeout;
int pre_go_timeout;
/*for handle client discovery req/rsp , GO discovery req related */
unsigned char dev_dis_req_dialog_token;
unsigned char dev_dis_rsp_dialog_token;
// unsigned char provision_rx_dialog_token;
/*for handle provision discovery related process*/
unsigned char presence_tx_dialog_token;
unsigned char presence_rx_dialog_token;
/*for handle provision discovery related process*/
unsigned char provision_tx_dialog_token;
unsigned char provision_rx_dialog_token;
/*for handle active send provision req and Nego Req*/
unsigned char target_device_role;
unsigned char target_device_ssid[33];
unsigned char target_device_addr[MAC_LEN];
unsigned char target_device_channel;
unsigned short wsc_method_to_target_dev;
unsigned short dev_passwd_to_tar_dev;
unsigned char target_dev_pin_code[9];
unsigned char wsc_method_match;
/* when receive provision req , record target dev wsc method*/
unsigned short wsc_method_from_target_dev;
unsigned char passivemode_pbc_trigger_flag;
/*for handle action frames*/
unsigned char provision_req_timeout;
unsigned char requestor; // i am requestor or not
/*for handle go-nego related process*/
unsigned char go_nego_tx_dialog_token; // my req token
unsigned char go_nego_rx_dialog_token; // target dev's req token
unsigned char go_nego_on_going; // for lock this GO nego process
unsigned char go_nego_on_going_timeout; // for lock this GO nego process
/*for handle action packets ; when receive go-nego req*/
int wait_nego_conf_timeout;
/*my GO Negotiation data */
unsigned char my_GO_ssid[33]; /*should be DRIECT-xy+(0~23 assic)*/
unsigned char my_GO_ssid_len;
unsigned char ssid_random[6]; // DIRETC-xy ; the xy
unsigned char go_PSK[65];
struct p2p_channels my_channel_list;
/*my P2P capability*/
/*device capa 0~5*/
unsigned char service_discover;
unsigned char p2p_client_discoverability;
unsigned char concurrent_operations;
unsigned char p2p_infrastructure_managed;
unsigned char p2p_device_limit;
unsigned char p2p_invitation;
/*group capa 0~6*/
unsigned char p2p_go_role;
unsigned char persistent_go;
unsigned char p2p_go_limit;
unsigned char intra_bss_distribution;
unsigned char cross_conect;
unsigned char persistent_reconnect;
unsigned char go_formation;
unsigned char wps_is_ongoing;
/*p2p discovery phase need related data ; no use now*/
unsigned char spec_find_dev_addr[6]; /*the assigned p2p device address be find in probe_req */
unsigned char spec_find_primary_dev_type; /*the assigned primary device type be find in probe_req*/
struct p2p_device_peer ongoing_nego_peer ;
/*when i am on going with someone , reject another one*/
struct p2p_device_peer others_nego_tar_device;
unsigned char clientmode_try_connect;
int backup_orig_use40M;
int backup_orig_2ndchoffset;
};
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_phyreg.h
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_proc.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_profile.h
Executable
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@@ -0,0 +1,30 @@
#define SC_ENABLED 1
#define SC_DURATION_TIME 2
#define SC_GET_SYNC_TIME 3
#define SC_GET_PROFILE_TIME 4
#define SC_VXD_RESCAN_TIME 5
#define SC_PIN_ENABLED 6
#define SC_STATUS 7
#define SC_DEBUG 8
#define SC_CHECK_LINK_TIME 9
#define SC_SYNC_VXD_TO_ROOT 10
#define SC_ACK_ROUND 11
#define SC_CONTROL_IP 12
#define SC_PRIV_STATUS 13
#define SC_CONFIG_TIME 14
#define SC_CHECK_LEVEL 16
#define SC_IGNORE_OVERLAP 17
#define SC_FIX_CHANNEL 18
#define SC_FROM_TO_DS 19
#define SC_PIN 20
#define SC_DEFAULT_PIN 21
#define SC_PASSWORD 22
#define SC_DEVICE_NAME 23
#define SC_DEVICE_TYPE 24
#define SC_SSID 25
#define SC_BSSID 26
#define SC_IF_NAME 27
#define SC_MAGIC_LEN 8
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_psk.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_psk.h
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/*
* Header files of WPA PSK module
*
* $Id: 8192cd_psk.h,v 1.1 2009/11/06 12:26:48 victoryman Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_PSK_H_
#define _8192CD_PSK_H_
#define GMK_LEN 32
#define GTK_LEN 32
#define PMK_LEN 32
#define PTK_LEN 32
#ifdef CONFIG_IEEE80211W
#define IGTK_LEN 16
#endif /* CONFIG_IEEE80211W */
#define KEY_NONCE_LEN 32
#define NumGroupKey 4
#define KEY_RC_LEN 8
#define KEY_NONCE_LEN 32
#define KEY_IV_LEN 16
#define KEY_RSC_LEN 8
#define KEY_ID_LEN 8
#define KEY_MIC_LEN 16
#define KEY_MATERIAL_LEN 2
#define PTK_LEN_EAPOLMIC 16
#define PTK_LEN_EAPOLENC 16
#define PTK_LEN_TKIP 64
#define PMKID_LEN 16
#define LIB1X_ETHER_EAPOL_TYPE 0x888E
#define DescTypePos 0
#define KeyInfoPos 1
#define KeyLenPos 3
#define ReplayCounterPos 5
#define KeyNoncePos 13
#define KeyIVPos 45
#define KeyRSCPos 61
#define KeyIDPos 69
#define KeyMICPos 77
#define KeyDataLenPos 93
#define KeyDataPos 95
#define LIB1X_EAPOL_VER 1 //00000001B
#define LIB1X_EAPOL_LOGOFF 2 //0000 0010B
#define LIB1X_EAPOL_EAPPKT 0 //0000 0000B
#define LIB1X_EAPOL_START 1 //0000 0001B
#define LIB1X_EAPOL_KEY 3 //0000 0011B
#define LIB1X_EAPOL_ENCASFALERT 4 //0000 0100B
#ifdef CONFIG_IEEE80211W_CLI
#define KeyAKMPos 16
#define KEY_AKM_LEN 4
#endif
#define RANDOM_EXPANSION_CONST "Init Counter"
#define RANDOM_EXPANSION_CONST_SIZE 12
#define A_SHA_DIGEST_LEN 20
#define ETHER_HDRLEN 14
#define LIB1X_EAPOL_HDRLEN 4
#define INFO_ELEMENT_SIZE 128
#define MAX_EAPOLMSG_LEN 512
#define MAX_EAPOLKEYMSG_LEN (MAX_EAPOLMSG_LEN-(ETHER_HDRLEN+LIB1X_EAPOL_HDRLEN))
#define EAPOLMSG_HDRLEN 95 //EAPOL-key payload length without KeyData
#define MAX_UNICAST_CIPHER 2
#define WPA_ELEMENT_ID 0xDD
#define WPA2_ELEMENT_ID 0x30
typedef enum { desc_type_WPA2 = 2, desc_type_RSN = 254 } DescTypeRSN;
typedef enum { type_Group = 0, type_Pairwise = 1 } KeyType;
typedef enum { key_desc_ver1 = 1, key_desc_ver2 = 2, key_desc_ver3 = 3 } KeyDescVer;
enum { PSK_WPA=1, PSK_WPA2=2};
#ifdef TLN_STATS
enum { STATS_AUTH_OPEN=0, STATS_AUTH_SHARE=1,
STATS_PSK_WPA=2, STATS_PSK_WPA2=3,
STATS_ETP_WPA=4, STATS_ETP_WPA2=5
};
#endif
enum {
PSK_STATE_IDLE,
PSK_STATE_PTKSTART,
PSK_STATE_PTKINITNEGOTIATING,
PSK_STATE_PTKINITDONE,
};
enum {
PSK_GSTATE_REKEYNEGOTIATING,
PSK_GSTATE_REKEYESTABLISHED,
PSK_GSTATE_KEYERROR,
};
#ifdef CONFIG_IEEE80211W
enum mfp_options {
NO_MGMT_FRAME_PROTECTION = 0,
MGMT_FRAME_PROTECTION_OPTIONAL = 1,
MGMT_FRAME_PROTECTION_REQUIRED = 2
};
#endif
/*
* Reason code for Disconnect
*/
typedef enum _ReasonCode{
unspec_reason = 0x01,
auth_not_valid = 0x02,
deauth_lv_ss = 0x03,
inactivity = 0x04,
ap_overload = 0x05,
class2_err = 0x06,
class3_err = 0x07,
disas_lv_ss = 0x08,
asoc_not_auth = 0x09,
RSN_invalid_info_element = 13,
RSN_MIC_failure = 14,
RSN_4_way_handshake_timeout = 15,
RSN_diff_info_element = 17,
RSN_multicast_cipher_not_valid = 18,
RSN_unicast_cipher_not_valid = 19,
RSN_AKMP_not_valid = 20,
RSN_unsupported_RSNE_version = 21,
RSN_invalid_RSNE_capabilities = 22,
RSN_ieee_802dot1x_failed = 23,
//belowing are Realtek definition
RSN_PMK_not_avaliable = 24,
expire = 30,
session_timeout = 31,
acct_idle_timeout = 32,
acct_user_request = 33
}ReasonCode;
typedef struct _OCTET_STRING {
unsigned char *Octet;
int Length;
} OCTET_STRING, *POCTET_STRING;
typedef union _LARGE_INTEGER {
unsigned char charData[8];
struct {
unsigned int HighPart;
unsigned int LowPart;
} field;
} LARGE_INTEGER, *PLARGE_INTEGER;
typedef union _OCTET16_INTEGER {
unsigned char charData[16];
struct {
LARGE_INTEGER HighPart;
LARGE_INTEGER LowPart;
} field;
} OCTET16_INTEGER;
typedef union _OCTET32_INTEGER {
unsigned char charData[32];
struct {
OCTET16_INTEGER HighPart;
OCTET16_INTEGER LowPart;
} field;
} OCTET32_INTEGER;
typedef struct _DOT11_WPA2_IE_HEADER {
unsigned char ElementID;
unsigned char Length;
unsigned short Version;
} DOT11_WPA2_IE_HEADER;
#if (defined(WIFI_HAPD) && !defined(HAPD_DRV_PSK_WPS)) || (defined(RTK_NL80211) && !defined(NON_NL80211_AP) && !defined(NON_NL80211_WPAS))
// group key info
typedef struct _wpa_global_info {
OCTET_STRING AuthInfoElement;
unsigned char AuthInfoBuf[INFO_ELEMENT_SIZE];
unsigned char MulticastCipher;
int NumOfUnicastCipher;
unsigned char UnicastCipher[MAX_UNICAST_CIPHER];
#ifdef RTL_WPA2
int NumOfUnicastCipherWPA2;
unsigned char UnicastCipherWPA2[MAX_UNICAST_CIPHER];
#endif
#ifdef CONFIG_IEEE80211W_CLI
unsigned short rsnie_cap;
#endif
} WPA_GLOBAL_INFO;
#else
// group key info
typedef struct _wpa_global_info {
OCTET32_INTEGER Counter;
unsigned char PSK[A_SHA_DIGEST_LEN*2];
unsigned char PSKGuest[A_SHA_DIGEST_LEN*2];
int GTKAuthenticator;
int GKeyDoneStations;
int GInitAKeys;
int GUpdateStationKeys;
int GkeyReady;
OCTET_STRING AuthInfoElement;
unsigned char AuthInfoBuf[INFO_ELEMENT_SIZE];
unsigned char MulticastCipher;
int NumOfUnicastCipher;
unsigned char UnicastCipher[MAX_UNICAST_CIPHER];
#ifdef RTL_WPA2
int NumOfUnicastCipherWPA2;
unsigned char UnicastCipherWPA2[MAX_UNICAST_CIPHER];
#endif
OCTET_STRING GNonce;
unsigned char GNonceBuf[KEY_NONCE_LEN];
unsigned char GTK[NumGroupKey][GTK_LEN];
unsigned char GMK[GMK_LEN];
int GN;
int GM;
#ifdef CONFIG_IEEE80211W
#ifdef CONFIG_IEEE80211W_CLI
unsigned short rsnie_cap;
#endif
unsigned char IGTK[2][IGTK_LEN];
int GN_igtk;
int GM_igtk;
union PN48 IGTK_PN;
#endif
int GRekeyCounts;
int GResetCounter;
int IntegrityFailed;
int GTKRekey;
int GKeyFailure;
struct timer_list GKRekeyTimer;
} WPA_GLOBAL_INFO;
#endif
#if (defined(WIFI_HAPD) && !defined(HAPD_DRV_PSK_WPS)) || (defined(RTK_NL80211) && !defined(NON_NL80211_AP) && !defined(NON_NL80211_WPAS))
// wpa sta info
typedef struct _wpa_sta_info {
int state;
int RSNEnabled; // bit0-WPA, bit1-WPA2
unsigned char UnicastCipher;
struct rtl8192cd_priv *priv;
#ifdef CONFIG_IEEE80211W
BOOLEAN mgmt_frame_prot;
#endif
} WPA_STA_INFO;
#else
// wpa sta info
typedef struct _wpa_sta_info {
int state;
int gstate;
int RSNEnabled; // bit0-WPA, bit1-WPA2
int PMKCached;
int PInitAKeys;
unsigned char UnicastCipher;
unsigned char NumOfRxTSC;
unsigned char AuthKeyMethod;
#ifdef CONFIG_IEEE80211W
enum mfp_options ieee80211w; /* dot11AssociationSAQueryMaximumTimeout (in TUs) */
unsigned int assoc_sa_query_max_timeout; /* dot11AssociationSAQueryRetryTimeout (in TUs) */
int assoc_sa_query_retry_timeout;
#endif /* CONFIG_IEEE80211W */
int isSuppSupportPreAuthentication;
int isSuppSupportPairwiseAsDefaultKey;
LARGE_INTEGER CurrentReplayCounter;
LARGE_INTEGER ReplayCounterStarted; // david+1-12-2007
OCTET_STRING ANonce;
OCTET_STRING SNonce;
unsigned char AnonceBuf[KEY_NONCE_LEN];
unsigned char SnonceBuf[KEY_NONCE_LEN];
unsigned char PMK[PMK_LEN];
unsigned char PTK[PTK_LEN_TKIP];
OCTET_STRING EAPOLMsgRecvd;
OCTET_STRING EAPOLMsgSend;
OCTET_STRING EapolKeyMsgRecvd;
OCTET_STRING EapolKeyMsgSend;
unsigned char eapSendBuf[MAX_EAPOLMSG_LEN];
unsigned char eapRecvdBuf[MAX_EAPOLMSG_LEN];
struct timer_list resendTimer;
struct rtl8192cd_priv *priv;
int resendCnt;
int isGuest;
int clientHndshkProcessing;
int clientHndshkDone;
int clientGkeyUpdate;
LARGE_INTEGER clientMICReportReplayCounter;
#ifdef CONFIG_IEEE80211W
BOOLEAN mgmt_frame_prot;
#endif
} WPA_STA_INFO;
#endif
#if defined(PACK_STRUCTURE) || defined(__ECOS)
#pragma pack(1)
#endif
__PACK typedef struct _LIB1X_EAPOL_KEY
{
unsigned char key_desc_ver;
unsigned char key_info[2];
unsigned char key_len[2];
unsigned char key_replay_counter[KEY_RC_LEN];
unsigned char key_nounce[KEY_NONCE_LEN];
unsigned char key_iv[KEY_IV_LEN];
unsigned char key_rsc[KEY_RSC_LEN];
unsigned char key_id[KEY_ID_LEN];
unsigned char key_mic[KEY_MIC_LEN];
unsigned char key_data_len[KEY_MATERIAL_LEN];
unsigned char *key_data;
}__WLAN_ATTRIB_PACK__ lib1x_eapol_key;
__PACK struct lib1x_eapol
{
unsigned char protocol_version;
unsigned char packet_type; // This makes it odd in number !
unsigned short packet_body_length;
}__WLAN_ATTRIB_PACK__;
#if defined(PACK_STRUCTURE) || defined(__ECOS)
#pragma pack()
#endif
#define SetSubStr(f,a,l) memcpy(f.Octet+l,a.Octet,a.Length)
#define GetKeyInfo0(f, mask) ((f.Octet[KeyInfoPos + 1] & mask) ? 1 :0)
#define SetKeyInfo0(f,mask,b) (f.Octet[KeyInfoPos + 1] = (f.Octet[KeyInfoPos + 1] & ~mask) | ( b?mask:0x0) )
#define GetKeyInfo1(f, mask) ((f.Octet[KeyInfoPos] & mask) ? 1 :0)
#define SetKeyInfo1(f,mask,b) (f.Octet[KeyInfoPos] = (f.Octet[KeyInfoPos] & ~mask) | ( b?mask:0x0) )
// EAPOLKey
#define Message_DescType(f) (f.Octet[DescTypePos])
#define Message_setDescType(f, type) (f.Octet[DescTypePos] = type)
// Key Information Filed
#define Message_KeyDescVer(f) (f.Octet[KeyInfoPos+1] & 0x07)//(f.Octet[KeyInfoPos+1] & 0x01) | (f.Octet[KeyInfoPos+1] & 0x02) <<1 | (f.Octet[KeyInfoPos+1] & 0x04) <<2
#define Message_setKeyDescVer(f, v) (f.Octet[KeyInfoPos+1] &= 0xf8) , f.Octet[KeyInfoPos+1] |= (v & 0x07)//(f.Octet[KeyInfoPos+1] |= ((v&0x01)<<7 | (v&0x02)<<6 | (v&0x04)<<5) )
#define Message_KeyType(f) GetKeyInfo0(f,0x08)
#define Message_setKeyType(f, b) SetKeyInfo0(f,0x08,b)
#define Message_KeyIndex(f) ((f.Octet[KeyInfoPos+1] & 0x30) >> 4) & 0x03//(f.Octet[KeyInfoPos+1] & 0x20) | (f.Octet[KeyInfoPos+1] & 0x10) <<1
#define Message_setKeyIndex(f, v) (f.Octet[KeyInfoPos+1] &= 0xcf), f.Octet[KeyInfoPos+1] |= ((v<<4) & 0x07)//(f.Octet[KeyInfoPos+1] |= ( (v&0x01)<<5 | (v&0x02)<<4) )
#define Message_Install(f) GetKeyInfo0(f,0x40)
#define Message_setInstall(f, b) SetKeyInfo0(f,0x40,b)
#define Message_KeyAck(f) GetKeyInfo0(f,0x80)
#define Message_setKeyAck(f, b) SetKeyInfo0(f,0x80,b)
#define Message_KeyMIC(f) GetKeyInfo1(f,0x01)
#define Message_setKeyMIC(f, b) SetKeyInfo1(f,0x01,b)
#define Message_Secure(f) GetKeyInfo1(f,0x02)
#define Message_setSecure(f, b) SetKeyInfo1(f,0x02,b)
#define Message_Error(f) GetKeyInfo1(f,0x04)
#define Message_setError(f, b) SetKeyInfo1(f,0x04,b)
#define Message_Request(f) GetKeyInfo1(f,0x08)
#define Message_setRequest(f, b) SetKeyInfo1(f,0x08,b)
#define Message_Reserved(f) (f.Octet[KeyInfoPos] & 0xf0)
#define Message_setReserved(f, v) (f.Octet[KeyInfoPos] |= (v<<4&0xff))
#define Message_KeyLength(f) ((unsigned short)(f.Octet[KeyLenPos] <<8) + (unsigned short)(f.Octet[KeyLenPos+1]))
#define Message_setKeyLength(f, v) (f.Octet[KeyLenPos] = (v&0xff00) >>8 , f.Octet[KeyLenPos+1] = (v&0x00ff))
#define Message_KeyNonce(f) SubStr(f,KeyNoncePos,KEY_NONCE_LEN)
#define Message_setKeyNonce(f, v) SetSubStr(f, v, KeyNoncePos)
#define Message_EqualKeyNonce(f1, f2) (memcmp(f1.Octet + KeyNoncePos, f2.Octet, KEY_NONCE_LEN)? 0:1)
#define Message_KeyIV(f) Substr(f, KeyIVPos, KEY_IV_LEN)
#define Message_setKeyIV(f, v) SetSubStr(f, v, KeyIVPos)
#define Message_KeyRSC(f) Substr(f, KeyRSCPos, KEY_RSC_LEN)
#define Message_setKeyRSC(f, v) SetSubStr(f, v, KeyRSCPos)
#define Message_KeyID(f) Substr(f, KeyIDPos, KEY_ID_LEN)
#define Message_setKeyID(f, v) SetSubStr(f, v, KeyIDPos)
#define Message_MIC(f) SubStr(f, KeyMICPos, KEY_MIC_LEN)
#define Message_setMIC(f, v) SetSubStr(f, v, KeyMICPos)
#define Message_clearMIC(f) memset(f.Octet+KeyMICPos, 0, KEY_MIC_LEN)
#define Message_KeyDataLength(f) ((unsigned short)(f.Octet[KeyDataLenPos] <<8) + (unsigned short)(f.Octet[KeyDataLenPos+1]))
#define Message_setKeyDataLength(f, v) (f.Octet[KeyDataLenPos] = (v&0xff00) >>8 , f.Octet[KeyDataLenPos+1] = (v&0x00ff))
#define Message_KeyData(f, l) SubStr(f, KeyDataPos, l)
#define Message_setKeyData(f, v) SetSubStr(f, v, KeyDataPos);
#define Message_EqualRSNIE(f1 , f2, l) (memcmp(f1.Octet, f2.Octet, l) ? 0:1)
#define Message_ReturnKeyDataLength(f) f.Length - (ETHER_HDRLEN + LIB1X_EAPOL_HDRLEN + EAPOLMSG_HDRLEN)
#define Message_CopyReplayCounter(f1, f2) memcpy(f1.Octet + ReplayCounterPos, f2.Octet + ReplayCounterPos, KEY_RC_LEN)
#define Message_DefaultReplayCounter(li) ((li.field.HighPart == 0xffffffff) && (li.field.LowPart == 0xffffffff) ) ?1:0
#ifdef CONFIG_IEEE80211W_CLI
#define Message_setSha256AKM(f, v) SetSubStr(f, v, KeyAKMPos)
#endif
#if defined(CONFIG_RTL8186_KB_N)
extern int authRes;//0: success; 1: fail
#endif
struct KDE {
unsigned char type;
unsigned char length;
unsigned char oui[3];
unsigned char data_type;
};
enum KDE_DATA_TYPE {
GTK_KDE = 1,
MAV_ADDRESS_KDE = 3,
PMKID_KDE = 4,
SMK_KDE = 5,
NONCE_KDE = 6,
LIFETIME_KDE = 7,
ERROR_KDE = 8,
IGTK_KDE = 9,
};
#endif // _8192CD_PSK_H_
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_psk_hapd.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_pwrctrl.c
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#ifdef CONFIG_POWER_SAVE
#define _8192CD_PWRCTRL_C_
#include <linux/irq.h>
#include <linux/gpio.h>
#ifdef CONFIG_WAKELOCK
#include <linux/wakelock.h>
#endif
#include "8192cd_headers.h"
#include "8192cd_debug.h"
#include "8192cd_pwrctrl.h"
#ifdef PLATFORM_ARM_BALONG
#include <linux/platform_device.h>
#endif
#ifdef USE_WAKELOCK_MECHANISM
static struct wakeup_source *ws_wifi;
#endif
u16 temp_608;
int rtw_sdio_prepare(struct device *dev)
{
struct sdio_func *func = dev_to_sdio_func(dev);
struct net_device *netdev = sdio_get_drvdata(func);
struct rtl8192cd_priv *priv = GET_DEV_PRIV(netdev);
struct priv_shared_info *pshare = priv->pshare;
if (!IS_DRV_OPEN(priv)) {
DEBUG_INFO("[%s] driver closed, return.\n", __FUNCTION__);
return 0;
}
// check tx pending queue is empty.
if (pshare->pending_xmitbuf_queue.qlen) {
DEBUG_INFO("[%s] tx pending queue not empty.\n", __FUNCTION__);
rtw_lock_suspend_timeout(priv, 2*priv->pmib->dot11OperationEntry.ps_timeout);
return -1;
}
if (GET_HAL_INTF_DATA(priv)->SdioTxIntStatus) {
DEBUG_INFO("[%s] SdioTxIntStatus is not idle.\n", __FUNCTION__);
rtw_lock_suspend_timeout(priv, 2*priv->pmib->dot11OperationEntry.ps_timeout);
return -1;
}
RTL_W8(0x286, RTL_R8(0x286)|BIT2);
if (RTL_R8(0x286) & BIT1) {
DEBUG_INFO("[%s] rx dma is idle.\n", __FUNCTION__);
} else {
DEBUG_INFO("[%s] rx dma is not idle.\n", __FUNCTION__);
}
pshare->ps_xfer_seq = pshare->xfer_seq;
return 0;
}
void rtw_sdio_complete(struct device *dev)
{
struct sdio_func *func = dev_to_sdio_func(dev);
struct net_device *netdev = sdio_get_drvdata(func);
struct rtl8192cd_priv *priv = GET_DEV_PRIV(netdev);
if (!IS_DRV_OPEN(priv)) {
DEBUG_INFO("[%s] driver closed, return.\n", __FUNCTION__);
return;
}
RTL_W8(0x286 , (RTL_R8(0x286) & (~BIT2)));
}
int rtw_sdio_suspend(struct device *dev)
{
struct sdio_func *func = dev_to_sdio_func(dev);
struct net_device *netdev = sdio_get_drvdata(func);
struct rtl8192cd_priv *priv = GET_DEV_PRIV(netdev);
struct priv_shared_info *pshare = priv->pshare;
struct ap_pwrctrl_priv *ps_handle = &pshare->ap_ps_handle;
unsigned char loc_bcn[3] = {0};
unsigned char loc_probe[3] = {0};
unsigned int i, hidden, wait_cnt = 0;
u1Byte IsLinked = 0;
int err = -1;
_irqL irqL;
if (!IS_DRV_OPEN(priv)) {
DEBUG_INFO("[%s] driver closed, return.\n", __FUNCTION__);
#ifdef USE_WAKELOCK_MECHANISM
mmc_pm_flag_t pm_flag = 0;
pm_flag = sdio_get_host_pm_caps(func);
pm_flag |= MMC_PM_KEEP_POWER;
sdio_set_host_pm_flags(func, pm_flag);
DEBUG_INFO("[%s] driver closed, but need keep wifi power.\n", __FUNCTION__);
#endif
return 0;
}
if (pshare->offload_prohibited) {
DEBUG_ERR("[%s] power save disabled ,return\n", __FUNCTION__);
pshare->offload_function_ctrl = RTW_PM_AWAKE;
#ifdef USE_WAKELOCK_MECHANISM
rtw_lock_suspend(priv);
RTL_W8(0x286 , (RTL_R8(0x286) & (~BIT2)));
#endif
return -1;
}
_enter_critical_mutex(&pshare->apps_lock, &irqL);
if (RTW_PM_SUSPEND == pshare->offload_function_ctrl) {
_exit_critical_mutex(&pshare->apps_lock, &irqL);
return 0;
}
DEBUG_INFO("%s ===>\n", __FUNCTION__);
DEBUG_INFO("[%s,%d] name = %s\n", __FUNCTION__, __LINE__, priv->dev->name);
DEBUG_INFO("[%s,%d] ps_level = %d\n", __FUNCTION__, __LINE__, priv->pmib->dot11OperationEntry.ps_level);
DEBUG_INFO("[%s,%d] ps_timeout = %d\n", __FUNCTION__, __LINE__, priv->pmib->dot11OperationEntry.ps_timeout);
DEBUG_INFO("[%s] total_assoc_num=%d\n", __FUNCTION__, pshare->total_assoc_num);
temp_608 = RTL_R16(0x608);
RTL_W16(0x608, ((temp_608|BIT7)&0xfcff));
#ifdef CONFIG_RTL_88E_SUPPORT
if (pshare->total_assoc_num)
RTL8188E_SuspendTxReport(priv);
#endif
if (timer_pending(&pshare->beacon_timer))
del_timer_sync(&pshare->beacon_timer);
if (timer_pending(&pshare->ps_timer))
del_timer_sync(&pshare->ps_timer);
if (timer_pending(&pshare->xmit_check_timer))
del_timer_sync(&pshare->xmit_check_timer);
pshare->ps_timer_expires = 0;
/* start beacon offload */
#ifdef USE_WAKELOCK_MECHANISM
if (pshare->offload_function_ctrl == RTW_PM_AWAKE)
{
pshare->offload_function_ctrl = RTW_PM_PREPROCESS;
pshare->ps_ctrl = RTW_ACT_POWERDOWN;
update_beacon(pshare->bcn_priv[0]);
pshare->ps_ctrl = RTW_ACT_POWERON;
}
#endif
#if defined(CONFIG_RTL_88E_SUPPORT)
loc_bcn[0] = TX_TOTAL_PAGE_NUMBER_88E + 1;
loc_probe[0] = loc_bcn[0] + pshare->ap_offload_res[0].probe_offset;
#elif defined(CONFIG_WLAN_HAL_8192EE)
loc_bcn[0] = 0xf6;
loc_probe[0] = loc_bcn[0] + pshare->ap_offload_res[0].probe_offset;
#endif
hidden = 0;
if (pshare->bcn_priv[0]->pmib->dot11OperationEntry.hiddenAP)
hidden |= BIT0;
#ifdef MBSSID
for (i = 1; i < pshare->nr_bcn; i++) {
loc_bcn[i] = loc_bcn[0] + pshare->ap_offload_res[i].beacon_offset;
loc_probe[i] = loc_bcn[0] + pshare->ap_offload_res[i].probe_offset;
if (pshare->bcn_priv[i]->pmib->dot11OperationEntry.hiddenAP)
hidden |= BIT(i);
}
DEBUG_INFO("clif loc: bcn[0]=%x probe[0]=%x bcn[1]=%x probe[1]=%x, hidden=%x\n",
loc_bcn[0], loc_probe[0], loc_bcn[1], loc_probe[1], hidden);
#else
DEBUG_INFO("clif loc: bcn[0]=%x probe[0]=%x, hidden=%x\n",
loc_bcn[0], loc_probe[0], hidden);
#endif
DEBUG_INFO("[%s] total tx bcn inrerface : %d\n", __FUNCTION__, pshare->nr_bcn);
#ifdef PLATFORM_ARM_BALONG
if (pshare->wake_irq > 0)
enable_irq_wake(pshare->wake_irq);
#endif
#ifdef CONFIG_WLAN_HAL_8192EE
RTL_W8(0x1c , (RTL_R8(0x1c) & (~(BIT1|BIT0))));
#endif
//stop rx
RTL_W8(0x286, RTL_R8(0x286)|BIT2);
//polling rx dma idle
while (!(RTL_R8(0x286) & BIT1)) {
if (++wait_cnt > 100 || pshare->ps_ctrl == RTW_ACT_POWERON)
{
DEBUG_INFO("[%s] rx dma is not idle.\n", __FUNCTION__);
goto fail;
}
msleep(1);
}
DEBUG_INFO("[%s] rx dma is idle.\n", __FUNCTION__);
DisableSdioInterrupt( priv);
ClearSdioInterrupt(priv);
ps_handle->suspend_processing = 1;
if (pshare->total_assoc_num > 0)
IsLinked = 1;
DEBUG_INFO("[%s,%d] IsLinked = %x, hidAP = %x\n", __FUNCTION__, __LINE__, IsLinked, hidden);
DEBUG_INFO("[%s,%d] offload duration = %d us\n", __FUNCTION__, __LINE__, OFFLOAD_DURATION);
DEBUG_INFO("[%s,%d] Repeat trigger duration = %d %s\n", __FUNCTION__, __LINE__,
REPEAT_TRIGGER_DURATION * ((REPEAT_TRIGGER_UNIT==TRIGGER_TIME_2SEC)?2:8),
(REPEAT_TRIGGER_UNIT==TRIGGER_TIME_2SEC)?"sec":"msec");
RTL_W8(0x1c7, 0x0); //check send pulse or not.
pshare->pwr_state = RTW_STS_SUSPEND;
pshare->offload_function_ctrl = RTW_PM_SUSPEND;
pshare->ap_ps_handle.en_32k = (priv->pmib->dot11OperationEntry.ps_32k_en ? 1:0);
rtw_ap_start_fw_ps(priv, pshare->ap_ps_handle.en_32k, 1);
delay_us(10);
#if defined(CONFIG_RTL_88E_SUPPORT)
set_wakeup_pin(priv, PULSE_DURATION, 1, 1, 1, 7);
delay_us(10);
//set_repeat_wake_pulse(priv, 1, REPEAT_TRIGGER_UNIT, REPEAT_TRIGGER_DURATION);
//delay_us(10);
set_bcn_resv_page(priv, loc_bcn[0], loc_bcn[1], loc_bcn[2]);
delay_us(10);
set_probe_res_resv_page(priv, loc_probe[0], loc_probe[1], loc_probe[2]);
delay_us(10);
set_ap_offload(priv, 0, hidden, 1, IsLinked);
#elif defined(CONFIG_WLAN_HAL_8192EE)
GET_HAL_INTERFACE(priv)->SetAPOffloadHandler(priv, 1, IsLinked,
pshare->nr_bcn, hidden, 0, loc_bcn, loc_probe);
#endif
delay_us(10);
ps_handle->h2c_done = 1;
wait_cnt = 0;
// check firmware is receive H2C command for AP offload
while (!(RTL_R8(0x130)&BIT3))
{
if (++wait_cnt > 20) {
DEBUG_ERR("[%s] firmware no receive H2C command or already leave AP offload mode! \n", __FUNCTION__);
goto fail;
}
delay_ms(1);
}
if (pshare->ap_ps_handle.en_32k)
set_ap_32k(priv, 1);
#ifdef USE_WAKELOCK_MECHANISM
mmc_pm_flag_t pm_flag = 0;
pm_flag = sdio_get_host_pm_caps(func);
if (!(pm_flag & MMC_PM_KEEP_POWER)) {
DEBUG_ERR("%s: cannot remain alive while host is suspended\n", sdio_func_id(func));
err = -ENOSYS;
goto fail;
}
DEBUG_INFO("cmd: suspend with MMC_PM_KEEP_POWER\n");
pm_flag |= MMC_PM_KEEP_POWER;
sdio_set_host_pm_flags(func, pm_flag);
#endif
if (pshare->ps_xfer_seq != pshare->xfer_seq) {
DEBUG_INFO("[%s] Detect traffic.\n", __FUNCTION__);
goto fail;
}
#ifdef PLATFORM_ARM_BALONG
extern int BSP_PWRCTRL_WIFI_LowPowerEnter(void);
BSP_PWRCTRL_WIFI_LowPowerEnter();
#endif
DEBUG_INFO("<=== %s\n", __FUNCTION__);
_exit_critical_mutex(&pshare->apps_lock, &irqL);
return 0;
fail:
pshare->offload_function_ctrl = RTW_PM_SUSPEND;
__rtw_sdio_resume(priv);
_exit_critical_mutex(&pshare->apps_lock, &irqL);
return err;
}
int __rtw_sdio_resume(struct rtl8192cd_priv *priv)
{
struct priv_shared_info *pshare = priv->pshare;
struct ap_pwrctrl_priv *ps_handle = &pshare->ap_ps_handle;
int i, wait_cnt = 0;
// Don't do AP offload exit when not in AP offload state. otherwise it may cause TXDMA error.
if (RTW_PM_SUSPEND != pshare->offload_function_ctrl)
return 0;
DEBUG_INFO("%s ===>\n", __FUNCTION__);
if (priv->pmib->dot11OperationEntry.ps_level < 2 && pshare->total_assoc_num > 0)
{
DEBUG_ERR("[%s] current power save not match linked ps!\n", __FUNCTION__);
}
#ifdef PLATFORM_ARM_BALONG
if (pshare->wake_irq > 0)
disable_irq_wake(pshare->wake_irq);
#endif
// Don't do H2C commands to exit AP offload during error recovery when H2C command which enable AP offload is not done.
// Otherwise it will cause TXDMA error 0x14.
if (ps_handle->h2c_done) {
ps_handle->h2c_done = 0;
if (pshare->ap_ps_handle.en_32k) {
set_ap_32k(priv, 0);
delay_ms(1);
}
#if defined(CONFIG_RTL_88E_SUPPORT)
set_ap_offload(priv, 0, 0, 0, 0);
#elif defined(CONFIG_WLAN_HAL_8192EE)
GET_HAL_INTERFACE(priv)->SetAPOffloadHandler(priv, 0, 0, 0, 0, 0, 0, 0);
#endif
delay_ms(1);
rtw_ap_stop_fw_ps(priv);
#ifdef CONFIG_RTL_88E_SUPPORT
RTL_W8(REG_MBID_NUM, RTL_R8(REG_MBID_NUM)& (~BIT(3)));
#endif
// check firmware is leave AP offload mode
while ((RTL_R8(0x130)&BIT3))
{
if (++wait_cnt > 20) {
DEBUG_ERR("[%s] firmware no leave AP offload mode! \n", __FUNCTION__);
break;
}
delay_ms(1);
}
}
RTL_W8(0x286 , (RTL_R8(0x286) & (~BIT2)));
for (i=0; i<10; i++)
{
if(RTL_R8(0x286)&BIT2)
{
DEBUG_ERR("[%s] resume 0x286 clear BIT2 fail\n", __FUNCTION__);
RTL_W8(0x286 , (RTL_R8(0x286) & (~BIT2)));
delay_ms(1);
}
else
break;
}
ps_handle->suspend_processing = 0;
RTL_W16(0x608,temp_608);
#ifdef CONFIG_RTL_88E_SUPPORT
if (pshare->total_assoc_num)
RTL8188E_ResumeTxReport(priv);
#endif
// Update current Tx FIFO page & Tx OQT space
WARN_ON(GET_HAL_INTF_DATA(priv)->SdioTxIntStatus);
sdio_query_txbuf_status(priv);
sdio_query_txoqt_status(priv);
pshare->offload_function_ctrl = RTW_PM_AWAKE;
pshare->pwr_state = RTW_STS_NORMAL;
pshare->ps_ctrl = RTW_ACT_IDLE;
if (priv->drv_state & DRV_STATE_OPEN) {
rtw_offload_reinit_timer(priv);
rtw_lock_suspend_timeout(priv, 2*priv->pmib->dot11OperationEntry.ps_timeout);
}
// Interrupt enable must be last step of the resume to avoid interfering with resume process.
EnableSdioInterrupt(priv);
DEBUG_INFO("<=== %s\n", __FUNCTION__);
return 0;
}
int rtw_sdio_resume(struct device *dev)
{
struct sdio_func *func = dev_to_sdio_func(dev);
struct net_device *netdev = sdio_get_drvdata(func);
struct rtl8192cd_priv *priv;
int err = 0;
_irqL irqL;
if (NULL == netdev)
return 0;
priv = GET_DEV_PRIV(netdev);
if (!IS_DRV_OPEN(priv)) {
DEBUG_INFO("[%s] driver closed, return.\n", __FUNCTION__);
return 0;
}
_enter_critical_mutex(&priv->pshare->apps_lock, &irqL);
err = __rtw_sdio_resume(priv);
_exit_critical_mutex(&priv->pshare->apps_lock, &irqL);
return err;
}
/********************************************************/
#ifdef PLATFORM_ARM_BALONG
#include <linux/irq.h>
enum {
GPIO_NORMAL=0,
GPIO_INTERRUPT=0,
};
#define GPIO_MAXIMUM (12)
#define GPIO_MAX_PINS (8)
#define BALONG_GPIO_0(_nr) (_nr)
#define BALONG_GPIO_1(_nr) (BALONG_GPIO_0(GPIO_MAX_PINS - 1) + (_nr) + 1 )
#define BALONG_GPIO_2(_nr) (BALONG_GPIO_1(GPIO_MAX_PINS - 1) + (_nr) + 1 )
#define BALONG_GPIO_3(_nr) (BALONG_GPIO_2(GPIO_MAX_PINS - 1) + (_nr) + 1 )
#define BALONG_GPIO_4(_nr) (BALONG_GPIO_3(GPIO_MAX_PINS - 1) + (_nr) + 1 )
#define BALONG_GPIO_5(_nr) (BALONG_GPIO_4(GPIO_MAX_PINS - 1) + (_nr) + 1 )
#define BALONG_GPIO_6(_nr) (BALONG_GPIO_5(GPIO_MAX_PINS - 1) + (_nr) + 1 )
#define BALONG_GPIO_7(_nr) (BALONG_GPIO_6(GPIO_MAX_PINS - 1) + (_nr) + 1 )
#define INT_GPIO_GP5 117
#define BALONG_GPIO_WIFI_WAKEUP_CHIP 5
//#define BALONG_GPIO_WIFI_WAKEUP_PIN 4
#define BALONG_GPIO_WIFI_WAKEUP_PIN 0
#define BALONG_GPIO_WIFI_WAKEUP BALONG_GPIO_5(BALONG_GPIO_WIFI_WAKEUP_PIN)
#define BALONG_GPIO_WIFI_PWR_PIN 2
#define BALONG_GPIO_WIFI_PWR BALONG_GPIO_5(BALONG_GPIO_WIFI_PWR_PIN)
/*defined in drivers/mmc/host/hisdio_sys_ctrl.h */
#define BALONG_GPIO_WIFI_RESET_PIN 6
#define BALONG_GPIO_WIFI_RESET BALONG_GPIO_5(BALONG_GPIO_WIFI_RESET_PIN)
extern int gpio_int_mask_set(unsigned int gpio);
extern int gpio_int_state_clear(unsigned int gpio);
extern int gpio_set_function(unsigned int gpio, unsigned function);
extern int gpio_int_trigger_set(unsigned int gpio, unsigned int trigger);
extern int gpio_int_unmask_set(unsigned int gpio);
extern int gpio_int_state_get(unsigned int gpio, unsigned *state);
extern int gpio_direction_input(unsigned int gpio);
extern int gpio_request(unsigned int gpio, const char *lebel);
extern void gpio_free(unsigned int gpio);
extern int gpio_direction_output(unsigned int gpio, int value);
extern void balong_wifi_vote(int element);
extern void balong_wifi_devote(int element);
#ifdef __LINUX_2_6__
irqreturn_t balong_gpio_wakeup_isr(int irq, void *dev_instance)
#else
void balong_gpio_wakeup_isr(int irq, void *dev_instance, struct pt_regs *regs)
#endif
{
struct net_device *dev = NULL;
struct rtl8192cd_priv *priv = NULL;
unsigned int ucData;
priv =(struct rtl8192cd_priv *) dev_instance;
gpio_int_state_get(BALONG_GPIO_WIFI_WAKEUP, (unsigned int*)&ucData);
printk("acli: get intr %d\n", ucData);
if ( !ucData )
return IRQ_NONE;
gpio_int_state_clear(BALONG_GPIO_WIFI_WAKEUP);
if ( priv->pshare->pwr_state == RTW_STS_SUSPEND ) {
DEBUG_INFO("[%s,%d] RTW_STS_SUSPEND\n", __FUNCTION__, __LINE__);
priv->pshare->pwr_state = RTW_STS_NORMAL;
priv->pshare->ps_ctrl = RTW_ACT_IDLE;
schedule_work(&priv->ap_cmd_queue);
}
return IRQ_HANDLED;
}
int set_balong_wakeup_pin(struct net_device *dev, struct rtl8192cd_priv *priv)
{
int rc;
int gpio_num =7;
RTL_W32(GPIO_PIN_CTRL, RTL_R32(GPIO_PIN_CTRL) & ~BIT(gpio_num+8));
msleep(10);
gpio_int_mask_set(BALONG_GPIO_WIFI_WAKEUP);
gpio_int_state_clear(BALONG_GPIO_WIFI_WAKEUP);
// gpio_set_function(BALONG_GPIO_WIFI_WAKEUP);
gpio_set_function(BALONG_GPIO_WIFI_WAKEUP, GPIO_INTERRUPT);
gpio_int_trigger_set(BALONG_GPIO_WIFI_WAKEUP, IRQ_TYPE_EDGE_RISING);
gpio_int_state_clear(BALONG_GPIO_WIFI_WAKEUP);
gpio_int_unmask_set(BALONG_GPIO_WIFI_WAKEUP);
dev->irq = INT_GPIO_GP5;
priv->pshare->wake_irq = dev->irq;
rc = request_irq(dev->irq, balong_gpio_wakeup_isr, IRQF_SHARED, dev->name, priv);
if ( rc )
{
printk("some issue in wake-up irq, rx=%d\n", rc);
return -1;
}
gpio_int_state_clear(BALONG_GPIO_WIFI_WAKEUP);
gpio_int_unmask_set(BALONG_GPIO_WIFI_WAKEUP);
return 0;
}
#endif // PLATFORM_ARM_BALONG
/********************************************************/
int init_wifi_wakeup_gpio(struct net_device *dev, struct rtl8192cd_priv *priv)
{
int err = 0;
DEBUG_INFO("[%s] ENTRY \n", __FUNCTION__);
#ifdef PLATFORM_ARM_BALONG
err = set_balong_wakeup_pin(dev, priv);
#endif
return err;
}
void free_wifi_wakeup_gpio(struct net_device *dev, struct rtl8192cd_priv *priv)
{
DEBUG_INFO("[%s] ENTRY \n", __FUNCTION__);
#ifdef PLATFORM_ARM_BALONG
gpio_free(BALONG_GPIO_WIFI_WAKEUP_PIN);
#endif
}
#define RTW_SUSPEND_LOCK_NAME "rtw_wifi"
#ifdef USE_WAKELOCK_MECHANISM
#ifdef CONFIG_WAKELOCK
static struct wake_lock rtw_suspend_lock;
#endif
#endif
void rtw_suspend_lock_init(void)
{
PRINT_INFO("[%s] ENTRY \n", __FUNCTION__);
#ifdef USE_WAKELOCK_MECHANISM
#ifdef CONFIG_WAKELOCK
wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME);
#elif defined(CONFIG_PM_WAKELOCKS)
ws_wifi = wakeup_source_register("rtl8192 wake");
#endif
#endif
}
void rtw_suspend_lock_deinit(void)
{
PRINT_INFO("[%s] ENTRY \n", __FUNCTION__);
#ifdef USE_WAKELOCK_MECHANISM
#ifdef CONFIG_WAKELOCK
wake_lock_destroy(&rtw_suspend_lock);
#elif defined(CONFIG_PM_WAKELOCKS)
wakeup_source_unregister(ws_wifi);
#endif
#endif
}
void rtw_lock_suspend(struct rtl8192cd_priv *priv)
{
PRINT_INFO("[%s] ENTRY \n", __FUNCTION__);
#ifdef USE_WAKELOCK_MECHANISM
#ifdef CONFIG_WAKELOCK
wake_lock(&rtw_suspend_lock);
#elif defined(CONFIG_PM_WAKELOCKS)
__pm_stay_awake(ws_wifi);
#endif
#endif
}
void rtw_unlock_suspend(struct rtl8192cd_priv *priv)
{
PRINT_INFO("[%s] ENTRY \n", __FUNCTION__);
#ifdef USE_WAKELOCK_MECHANISM
#ifdef CONFIG_WAKELOCK
wake_unlock(&rtw_suspend_lock);
#elif defined(CONFIG_PM_WAKELOCKS)
__pm_relax(ws_wifi);
#endif
#endif
}
void rtw_lock_suspend_timeout(struct rtl8192cd_priv *priv, unsigned int timeout)
{
unsigned long expires;
_irqL irqL;
if (priv->pshare->offload_prohibited)
return;
if (!IS_DRV_OPEN(GET_ROOT(priv)))
return;
PRINT_INFO("[%s] ENTRY TO %d\n" , __FUNCTION__, timeout);
#ifdef USE_WAKELOCK_MECHANISM
#ifdef CONFIG_WAKELOCK
wake_lock_timeout(&rtw_suspend_lock, timeout);
#elif defined(CONFIG_PM_WAKELOCKS)
__pm_wakeup_event(ws_wifi, timeout);
#endif
timeout = timeout + 1000;
#endif
_enter_critical(&priv->pshare->offload_lock, &irqL);
if (!timeout) {
del_timer(&priv->pshare->ps_timer);
priv->pshare->ps_timer_expires = 0;
goto unlock;
}
expires = jiffies + RTL_MILISECONDS_TO_JIFFIES(timeout);
if (!priv->pshare->ps_timer_expires || time_after(expires, priv->pshare->ps_timer_expires)) {
mod_timer(&priv->pshare->ps_timer, expires);
priv->pshare->ps_timer_expires = expires;
}
unlock:
_exit_critical(&priv->pshare->offload_lock, &irqL);
}
int rtw_ap_ps_xmit_monitor(struct rtl8192cd_priv *priv)
{
if (0 == priv->assoc_num) {
//printk("[%s,%d] Detects have traffic and no STA link, drop the packet.\n", __FUNCTION__, __LINE__);
return 1;
}
priv->pshare->xfer_seq++;
if (RTW_PM_SUSPEND == priv->pshare->offload_function_ctrl) {
if (RTW_STS_SUSPEND == priv->pshare->pwr_state) {
//printk("[%s,%d] Detects have traffic sent to STA.\n", __FUNCTION__, __LINE__);
priv->pshare->pwr_state = RTW_STS_NORMAL;
priv->pshare->ps_ctrl = RTW_ACT_IDLE;
schedule_work(&GET_ROOT(priv)->ap_cmd_queue);
}
//printk("[%s,%d] Entry queue.\n", __FUNCTION__, __LINE__);
} else {
rtw_lock_suspend_timeout(priv, 2*GET_ROOT(priv)->pmib->dot11OperationEntry.ps_timeout);
}
return 0;
}
void rtw_ap_ps_recv_monitor(struct rtl8192cd_priv *priv)
{
rtw_lock_suspend_timeout(priv, 2*GET_ROOT(priv)->pmib->dot11OperationEntry.ps_timeout);
}
void rtw_ap_ps_init(struct rtl8192cd_priv *priv)
{
DEBUG_INFO("[%s] ENTRY \n", __FUNCTION__);
priv->pshare->ap_ps_handle.h2c_done = 0;
priv->pshare->ap_ps_handle.sleep_time = 0;
priv->pshare->ap_ps_handle.suspend_processing = 0;
}
void rtw_ap_ps_deinit(struct rtl8192cd_priv *priv)
{
DEBUG_INFO("[%s] ENTRY \n", __FUNCTION__);
}
void rtw_ap_stop_fw_ps(struct rtl8192cd_priv *priv)
{
DEBUG_INFO("[%s] ENTRY \n", __FUNCTION__);
#if defined(CONFIG_RTL_88E_SUPPORT)
set_softap_ps(priv, 0, 0, 0, 0);
#elif defined(CONFIG_WLAN_HAL_8192EE)
/* Set H2C Cmd to FW To leave PS */
GET_HAL_INTERFACE(priv)->SetSAPPsHandler(priv, 0, 0, 0, 0); //zyj test
#endif
}
void rtw_ap_start_fw_ps(struct rtl8192cd_priv *priv, u4Byte en_32k, u4Byte reason)
{
u1Byte sleep_time;
u1Byte beaconInterval = priv->pmib->dot11StationConfigEntry.dot11BeaconPeriod;
int ps_sleep_time = priv->pmib->dot11OperationEntry.ps_sleep_time;
DEBUG_INFO("[%s] ENTRY \n", __FUNCTION__);
/* Set H2C Cmd to FW To enter PS */
switch (priv->pshare->nr_bcn) {
case 2:
sleep_time = 20;//35
break;
case 3:
sleep_time = 20;
break;
default:
sleep_time = 20;
break;
}
if (ps_sleep_time != 0)
sleep_time = ps_sleep_time;
priv->pshare->ap_ps_handle.sleep_time = sleep_time;
sleep_time = (sleep_time * beaconInterval) / 100;
DEBUG_INFO("[%s] sleep_time = %d\n", __FUNCTION__, sleep_time);
#if defined(CONFIG_RTL_88E_SUPPORT)
set_softap_ps(priv, 1, en_32k, 1, sleep_time);
#elif defined(CONFIG_WLAN_HAL_8192EE)
GET_HAL_INTERFACE(priv)->SetSAPPsHandler(priv, 1, en_32k, 1, sleep_time);
#endif
}
void sdio_power_save_timer(unsigned long task_priv)
{
struct rtl8192cd_priv *priv = (struct rtl8192cd_priv *)task_priv;
struct priv_shared_info *pshare = priv->pshare;
if (pshare->offload_prohibited)
return;
if (pshare->pending_xmitbuf_queue.qlen || (pshare->nr_bcn > 3)) {
rtw_lock_suspend_timeout(priv, 2*priv->pmib->dot11OperationEntry.ps_timeout);
return;
}
DEBUG_INFO("[%s] ENTRY \n", __FUNCTION__);
if (RTW_PM_AWAKE == pshare->offload_function_ctrl) {
pshare->offload_function_ctrl = RTW_PM_PREPROCESS;
pshare->ps_xfer_seq = pshare->xfer_seq;
}
}
#endif // CONFIG_POWER_SAVE
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_pwrctrl.h
Executable
+48
View File
@@ -0,0 +1,48 @@
#ifdef CONFIG_POWER_SAVE
#include "8192cd.h"
#define EXTERN extern
EXTERN int rtw_sdio_prepare(struct device *dev);
EXTERN void rtw_sdio_complete(struct device *dev);
EXTERN int rtw_sdio_suspend(struct device *dev);
EXTERN int __rtw_sdio_resume(struct rtl8192cd_priv *priv);
EXTERN int rtw_sdio_resume(struct device *dev);
EXTERN int init_wifi_wakeup_gpio(struct net_device *dev, struct rtl8192cd_priv *priv);
EXTERN void free_wifi_wakeup_gpio(struct net_device *dev, struct rtl8192cd_priv *priv);
EXTERN void rtw_ap_stop_fw_ps(struct rtl8192cd_priv *priv);
EXTERN void rtw_ap_start_fw_ps(struct rtl8192cd_priv *priv, u4Byte en_32k, u4Byte reason);
#ifdef CONFIG_RTL_88E_SUPPORT
EXTERN void set_ap_offload(struct rtl8192cd_priv *priv, unsigned int deny_ap, unsigned int hid_ap, int enable, unsigned int linked);
EXTERN void set_repeat_wake_pulse(struct rtl8192cd_priv *priv, unsigned char en, unsigned char triggerTime, unsigned char duration);
EXTERN void set_bcn_resv_page(struct rtl8192cd_priv *priv, unsigned int rootap, unsigned int vap1, unsigned int vap2);
EXTERN void set_probe_res_resv_page(struct rtl8192cd_priv *priv, unsigned int rootap, unsigned int vap1, unsigned int vap2);
EXTERN void set_wakeup_pin(struct rtl8192cd_priv *priv, unsigned char duration, unsigned char en, unsigned char pull_high, unsigned char pulse, unsigned char pin);
EXTERN void set_softap_ps(struct rtl8192cd_priv *priv, u8 enable, u8 en_32K, u8 lps, u8 duration);
#endif
EXTERN void rtw_suspend_lock_init(void);
EXTERN void rtw_suspend_lock_deinit(void);
EXTERN void rtw_lock_suspend(struct rtl8192cd_priv *priv);
EXTERN void rtw_unlock_suspend(struct rtl8192cd_priv *priv);
EXTERN void rtw_lock_suspend_timeout(struct rtl8192cd_priv *priv, unsigned int timeout);
//EXTERN void rtw_ap_set_wake_lock(struct rtl8192cd_priv *priv, u1Byte level, u4Byte time_ms);
EXTERN int rtw_ap_ps_xmit_monitor(struct rtl8192cd_priv *priv);
EXTERN void rtw_ap_ps_recv_monitor(struct rtl8192cd_priv *priv);
EXTERN void rtw_ap_ps_init(struct rtl8192cd_priv *priv);
EXTERN void rtw_ap_ps_deinit(struct rtl8192cd_priv *priv);
EXTERN void ClearSdioInterrupt(struct rtl8192cd_priv *priv);
EXTERN void set_ap_32k(struct rtl8192cd_priv *priv, BOOLEAN bRpwmCfg);
EXTERN void rtw_flush_xmit_pending_queue(struct rtl8192cd_priv *priv);
EXTERN void rtw_flush_all_tx_mgt_queue(struct rtl8192cd_priv *priv);
EXTERN void sdio_power_save_timer(unsigned long task_priv);
#undef EXTERN
#endif // CONFIG_POWER_SAVE
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_rx.c
Executable
+10233
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_rx.h
Executable
+289
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@@ -0,0 +1,289 @@
/*
* Header files defines some RX inline routines
*
* $Id: 8192cd_rx.h,v 1.4.4.5 2010/12/10 06:11:55 button Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_RX_H_
#define _8192CD_RX_H_
#include "./8192cd_cfg.h"
#include "./8192cd.h"
#include "./8192cd_util.h"
#if defined(CONFIG_RG_WLAN_HWNAT_ACCELERATION) && !defined(CONFIG_ARCH_LUNA_SLAVE)
int fwdEngine_rx_skb (struct re_private *cp, struct sk_buff *skb,struct rx_info *pRxInfo);
#endif
#define SN_NEXT(n) ((n + 1) & 0xfff)
#define SN_LESS(a, b) (((a - b) & 0x800) != 0)
#define SN_DIFF(a, b) ((a >= b)? (a - b):(0xfff - b + a + 1))
#define init_frinfo(pinfo) \
do { \
pinfo->pskb = pskb; \
pinfo->rssi = 0; \
INIT_LIST_HEAD(&(pinfo->mpdu_list)); \
INIT_LIST_HEAD(&(pinfo->rx_list)); \
} while(0)
#ifdef CONFIG_PCI_HCI
#ifdef CONFIG_WLAN_HAL
#define ALIGN_OFFSET_SKB_DATA 32 //It is necessary to be power of 2
#define GetOffsetStartToRXDESC(priv, pskb) (ALIGN_OFFSET_SKB_DATA - ((((unsigned long)pskb->data) + sizeof(struct rx_frinfo)) & (ALIGN_OFFSET_SKB_DATA-1)))
static __inline__
__MIPS16
__IRAM_IN_865X
void init_rxdesc_88XX(
struct rtl8192cd_priv *priv,
struct sk_buff *pskb,
u2Byte i,
pu4Byte pBufAddr, // output
pu4Byte pBufLen // output
)
{
struct rtl8192cd_hw *phw;
struct rx_frinfo *pfrinfo;
u4Byte offset;
phw = GET_HW(priv);
offset = GetOffsetStartToRXDESC(priv, pskb);
skb_reserve(pskb, sizeof(struct rx_frinfo) + offset);
pfrinfo = get_pfrinfo(pskb);
init_frinfo(pfrinfo);
#if defined(UNIVERSAL_REPEATER) || defined(MBSSID)
pfrinfo->is_br_mgnt = 0;
#endif
#ifdef RX_BUFFER_GATHER
pfrinfo->gather_flag = 0;
#endif
#ifdef __ECOS
#ifdef DELAY_REFILL_RX_BUF
pskb->priv = priv;
#endif
#endif
phw->rx_infoL[i].pbuf = (void *)pskb;
phw->rx_infoL[i].paddr = get_physical_addr(priv, pskb->data, (RX_BUF_LEN - sizeof(struct rx_frinfo) - offset), PCI_DMA_FROMDEVICE);
*pBufAddr = (u4Byte)pskb->data;
#if 0
*pBufLen = RX_BUF_LEN - sizeof(struct rx_frinfo) - offset;
#else
//3 this buf len must be 32 byte alignment in 8881A !!!!, If not, the fs/ls mechanism will be fail
*pBufLen = RX_BUF_LEN - sizeof(struct rx_frinfo) - 64;
#ifdef CONFIG_WLAN_HAL_8881A
if(GET_CHIP_VER(priv) == VERSION_8881A) {
if ((*pBufLen & 0x1f) != 0) {
*pBufLen = (((*pBufLen) >> 5) << 5); // *pBufLen = *pBufLen / 32 * 32;
//printk("%s(%d): RX_BUF_LEN(%d) must be 32 byte alignment !!! \n", __FUNCTION__, __LINE__, *pBufLen);
}
}
#endif
#endif
#if defined(CONFIG_NET_PCI) && !defined(USE_RTL8186_SDK)
// Remove it because pci_map_single() in get_physical_addr() already performed memory sync.
//rtl_cache_sync_wback(priv, bus_to_virt(phw->rx_infoL[i].paddr), RX_BUF_LEN - sizeof(struct rx_frinfo) - offset, PCI_DMA_FROMDEVICE);
#else
#ifdef TRXBD_CACHABLE_REGION
memset(phw->rx_infoL[i].paddr, 0, RX_BUF_LEN - sizeof(struct rx_frinfo) - offset);
_dma_cache_wback((unsigned long)(bus_to_virt(phw->rx_infoL[i].paddr)-CONFIG_LUNA_SLAVE_PHYMEM_OFFSET),
RX_BUF_LEN - sizeof(struct rx_frinfo) - offset);
// _dma_cache_inv((unsigned long)(bus_to_virt(phw->rx_infoL[i].paddr)-CONFIG_LUNA_SLAVE_PHYMEM_OFFSET),
// RX_BUF_LEN - sizeof(struct rx_frinfo) - offset);
#else
rtl_cache_sync_wback(priv, bus_to_virt(phw->rx_infoL[i].paddr), RX_BUF_LEN - sizeof(struct rx_frinfo) - offset, PCI_DMA_FROMDEVICE);
#endif
#endif
}
#endif //CONFIG_WLAN_HAL
static __inline__ void init_rxdesc(struct sk_buff *pskb, int i, struct rtl8192cd_priv *priv)
{
struct rtl8192cd_hw *phw;
struct rx_frinfo *pfrinfo;
int offset;
phw = GET_HW(priv);
offset = 0x20 - ((((unsigned long)pskb->data) + sizeof(struct rx_frinfo)) & 0x1f); // need 32 byte aligned
skb_reserve(pskb, sizeof(struct rx_frinfo) + offset);
pfrinfo = get_pfrinfo(pskb);
init_frinfo(pfrinfo);
#if defined(UNIVERSAL_REPEATER) || defined(MBSSID)
pfrinfo->is_br_mgnt = 0;
#endif
#ifdef RX_BUFFER_GATHER
pfrinfo->gather_flag = 0;
#endif
#ifdef __ECOS
#ifdef DELAY_REFILL_RX_BUF
pskb->priv = priv;
#endif
#endif
phw->rx_infoL[i].pbuf = (void *)pskb;
phw->rx_infoL[i].paddr = get_physical_addr(priv, pskb->data, (RX_BUF_LEN - sizeof(struct rx_frinfo) - 64), PCI_DMA_FROMDEVICE);
phw->rx_descL[i].Dword6 = set_desc(phw->rx_infoL[i].paddr);
#if defined(CONFIG_NET_PCI) && !defined(USE_RTL8186_SDK)
// Remove it because pci_map_single() in get_physical_addr() already performed memory sync.
//rtl_cache_sync_wback(priv, (unsigned long)bus_to_virt(phw->rx_infoL[i].paddr), RX_BUF_LEN - sizeof(struct rx_frinfo)-64, PCI_DMA_FROMDEVICE);
#else
rtl_cache_sync_wback(priv, (unsigned long)(phw->rx_infoL[i].paddr), RX_BUF_LEN - sizeof(struct rx_frinfo)-64, PCI_DMA_FROMDEVICE);
#endif
phw->rx_descL[i].Dword0 = set_desc((i == (NUM_RX_DESC - 1)? RX_EOR : 0) | RX_OWN |((RX_BUF_LEN - sizeof(struct rx_frinfo)-64) & RX_PktLenMask)); //32 for alignment, 32 for TKIP MIC
}
#endif // CONFIG_PCI_HCI
static __inline__ unsigned char cal_rssi_avg_mp(struct rtl8192cd_priv *priv, unsigned int agv, unsigned int pkt_rssi)
{
unsigned int rssi;
rssi = ((agv * (100 - priv->pshare->mp_rssi_weight)) + (pkt_rssi*priv->pshare->mp_rssi_weight)) / 100;
if (pkt_rssi > agv)
rssi++;
return (unsigned char)rssi;
}
static __inline__ unsigned char cal_rssi_avg(unsigned int agv, unsigned int pkt_rssi)
{
unsigned int rssi;
rssi = ((agv * 19) + pkt_rssi) / 20;
if (pkt_rssi > agv)
rssi++;
return (unsigned char)rssi;
}
static __inline__ void update_sta_rssi(struct rtl8192cd_priv *priv,
struct stat_info *pstat, struct rx_frinfo *pfrinfo)
{
int i;
#ifdef SW_ANT_SWITCH
if(priv->pshare->RSSI_test == TRUE)
return;
#endif
#ifdef MP_TEST
if (OPMODE & WIFI_MP_STATE) {
//if (priv->pshare->rf_ft_var.rssi_dump) {
if (pfrinfo->physt && pfrinfo->rssi) {
priv->pshare->mp_rssi = cal_rssi_avg_mp(priv, priv->pshare->mp_rssi, pfrinfo->rssi);
priv->pshare->mp_sq = pfrinfo->sq;
priv->pshare->mp_rx_rate = pfrinfo->rx_rate;
#ifdef USE_OUT_SRC
#ifdef _OUTSRC_COEXIST
if(IS_OUTSRC_CHIP(priv))
#endif
{
for (i=0; i<2; i++)
priv->pshare->mp_rf_info.mimorssi[i] = cal_rssi_avg_mp(priv, priv->pshare->mp_rf_info.mimorssi[i], pfrinfo->rf_info.mimorssi[i]);
memcpy(&priv->pshare->mp_rf_info.mimosq[0], &pfrinfo->rf_info.mimosq[0], 2);
}
#endif
#if !defined(USE_OUT_SRC) || defined(_OUTSRC_COEXIST)
#ifdef _OUTSRC_COEXIST
if(!IS_OUTSRC_CHIP(priv))
#endif
{
for (i=0; i<2; i++)
priv->pshare->mp_rf_info.mimorssi[i] = cal_rssi_avg_mp(priv, priv->pshare->mp_rf_info.mimorssi[i], pfrinfo->rf_info.mimorssi[i]);
memcpy(&priv->pshare->mp_rf_info.mimosq[0], &pfrinfo->rf_info.mimosq[0], sizeof(struct rf_misc_info) - 2);
}
#endif
}
return;
}
#endif
if (pfrinfo->physt) {
if (pfrinfo->rssi) {
#if defined(HW_ANT_SWITCH)&& (defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT))
if (pfrinfo->driver_info_size > 0) {
unsigned char *phystatus = (unsigned char*)pfrinfo->driver_info;
int i = 1&(phystatus[27]>>7);
if (is_CCK_rate(pfrinfo->rx_rate))
++(pstat->cckPktCount[i]);
else
++(pstat->hwRxAntSel[i]);
if(!pstat->AntRSSI[i])
pstat->AntRSSI[i] = pfrinfo->rssi;
else
pstat->AntRSSI[i] = cal_rssi_avg(pstat->AntRSSI[i], pfrinfo->rssi);
if(priv->pshare->rf_ft_var.ant_dump&1) {
panic_printk("pkt--> cck:%d, B7=%d, B6=%d, R:(%d) Len:%d\n", is_CCK_rate(pfrinfo->rx_rate),
i, (1&(phystatus[27]>>6))
, pfrinfo->rssi, pfrinfo->pktlen);
}
}
#endif
pstat->rssi = cal_rssi_avg(pstat->rssi, pfrinfo->rssi);
pstat->sq = pfrinfo->sq;
pstat->rx_rate = pfrinfo->rx_rate;
pstat->rx_bw = pfrinfo->rx_bw;
pstat->rx_splcp = pfrinfo->rx_splcp;
#ifdef USE_OUT_SRC
#ifdef _OUTSRC_COEXIST
if(IS_OUTSRC_CHIP(priv))
#endif
{
if (pfrinfo->rf_info.mimorssi[0] != 0 || pfrinfo->rf_info.mimorssi[1] != 0)
for (i=0; i<2; i++)
pstat->rf_info.mimorssi[i] = cal_rssi_avg(pstat->rf_info.mimorssi[i], pfrinfo->rf_info.mimorssi[i]);
if (priv->pshare->rf_ft_var.rssi_dump)
memcpy(&pstat->rf_info.mimosq[0], &pfrinfo->rf_info.mimosq[0], sizeof(struct rf_misc_info) - 2);
}
#endif
#if !defined(USE_OUT_SRC) || defined(_OUTSRC_COEXIST)
#ifdef _OUTSRC_COEXIST
if(!IS_OUTSRC_CHIP(priv))
#endif
{
if (pfrinfo->rf_info.mimorssi[0] != 0 || pfrinfo->rf_info.mimorssi[1] != 0)
for (i=0; i<2; i++)
pstat->rf_info.mimorssi[i] = cal_rssi_avg(pstat->rf_info.mimorssi[i], pfrinfo->rf_info.mimorssi[i]);
if (priv->pshare->rf_ft_var.rssi_dump)
memcpy(&pstat->rf_info.mimosq[0], &pfrinfo->rf_info.mimosq[0], sizeof(struct rf_misc_info) - 2);
}
#endif
if (pstat->highest_rx_rate < pstat->rx_rate)
pstat->highest_rx_rate = pstat->rx_rate;
}
}
}
#endif // _8192CD_RX_H_
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_security.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_security.h
Executable
+831
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@@ -0,0 +1,831 @@
/*
* Header file defines the interface with AUTH daemon (802.1x authenticator)
*
* $Id: 8192cd_security.h,v 1.3.2.1 2010/12/01 13:38:00 button Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_SECURITY_H_
#define _8192CD_SECURITY_H_
#include "./8192cd_cfg.h"
#ifdef INCLUDE_WPS
#include "./wps/wsc.h"
#endif
typedef struct _DOT11_QUEUE_NODE
{
unsigned short ItemSize;
unsigned char Item[MAXDATALEN];
}DOT11_QUEUE_NODE;
typedef struct _DOT11_QUEUE
{
int Head;
int Tail;
int NumItem;
int MaxItem;
DOT11_QUEUE_NODE ItemArray[MAXQUEUESIZE];
}DOT11_QUEUE;
typedef unsigned char DOT11_KEY_RSC[8];
typedef enum{
DOT11_KeyType_Group = 0,
DOT11_KeyType_Pairwise = 1,
DOT11_KeyType_IGTK = 2
} DOT11_KEY_TYPE;
typedef enum{
DOT11_EAPOL_GROUP_INDEX = 0,
DOT11_EAPOL_PAIRWISE_INDEX = 3
} DOT11_EAPOL_KEY_INDEX;
typedef enum{
DOT11_KeyUsage_ENC,
DOT11_KeyUsage_MIC
} DOT11_KEY_USAGE;
typedef enum{
DOT11_Role_Auth,
DOT11_Role_Supp
} DOT11_ROLE;
typedef enum{
DOT11_VARIABLE_MACEnable,
DOT11_VARIABLE_SystemAuthControl,
DOT11_VARIABLE_AuthControlledPortStatus,
DOT11_VARIABLE_AuthControlledPortControl,
DOT11_VARIABLE_AuthenticationType,
DOT11_VARIABLE_KeyManagement,
DOT11_VARIABLE_MulticastCipher,
DOT11_VARIABLE_UnicastCipher
} DOT11_VARIABLE_TYPE;
typedef enum{
DOT11_SysAuthControl_Disabled,
DOT11_SysAuthControl_Enabled
} DOT11_SYSTEM_AUTHENTICATION_CONTROL;
typedef enum{
DOT11_PortControl_ForceUnauthorized,
DOT11_PortControl_ForceAuthorized,
DOT11_PortControl_Auto
} DOT11_PORT_CONTROL;
typedef enum{
DOT11_PortStatus_Unauthorized,
DOT11_PortStatus_Authorized,
DOT11_PortStatus_Guest
}DOT11_PORT_STATUS;
typedef enum{
DOT11_Association_Fail,
DOT11_Association_Success
}DOT11_ASSOCIATION_RESULT;
typedef enum{
DOT11_AuthKeyType_RSN = 1,
DOT11_AuthKeyType_PSK = 2,
DOT11_AuthKeyType_NonRSN802dot1x = 3,
DOT11_AuthKeyType_802_1X_SHA256 = 5, //CONFIG_IEEE80211W_CLI
DOT11_AuthKeyType_PSK_SHA256 = 6
} DOT11_AUTHKEY_TYPE;
typedef enum{
DOT11_AuthKeyType_RSN_MAP = 1,
DOT11_AuthKeyType_PSK_MAP = 2,
DOT11_AuthKeyType_NonRSN802dot1x_MAP = 4
} DOT11_AUTHKEY_TYPE_MAP;
typedef enum{
DOT11_Ioctl_Query = 0,
DOT11_Ioctl_Set = 1
} DOT11_Ioctl_Flag;
typedef enum{
DOT11_ENC_NONE = 0,
DOT11_ENC_WEP40 = 1,
DOT11_ENC_TKIP = 2,
DOT11_ENC_WRAP = 3,
DOT11_ENC_CCMP = 4,
DOT11_ENC_WEP104= 5,
DOT11_ENC_BIP = 6,
DOT11_ENC_WAPI = 6
} DOT11_ENC_ALGO;
typedef enum{
DOT11_ENC_NONE_MAP = 1,
DOT11_ENC_WEP40_MAP = 2,
DOT11_ENC_TKIP_MAP = 4,
DOT11_ENC_WRAP_MAP = 8,
DOT11_ENC_CCMP_MAP = 16,
DOT11_ENC_WEP104_MAP= 32
} DOT11_ENC_ALGO_MAP;
typedef enum{
DOT11_EVENT_NO_EVENT = 1,
DOT11_EVENT_REQUEST = 2,
DOT11_EVENT_ASSOCIATION_IND = 3,
DOT11_EVENT_ASSOCIATION_RSP = 4,
DOT11_EVENT_AUTHENTICATION_IND = 5,
DOT11_EVENT_REAUTHENTICATION_IND = 6,
DOT11_EVENT_DEAUTHENTICATION_IND = 7,
DOT11_EVENT_DISASSOCIATION_IND = 8,
DOT11_EVENT_DISCONNECT_REQ = 9,
DOT11_EVENT_SET_802DOT11 = 10,
DOT11_EVENT_SET_KEY = 11,
DOT11_EVENT_SET_PORT = 12,
DOT11_EVENT_DELETE_KEY = 13,
DOT11_EVENT_SET_RSNIE = 14,
DOT11_EVENT_GKEY_TSC = 15,
DOT11_EVENT_MIC_FAILURE = 16,
DOT11_EVENT_ASSOCIATION_INFO = 17,
DOT11_EVENT_INIT_QUEUE = 18,
DOT11_EVENT_EAPOLSTART = 19,
#ifdef CONFIG_IEEE80211W
DOT11_EVENT_SA_QUERY = 20,
DOT11_EVENT_SA_QUERY_RSP = 21,
#endif
DOT11_EVENT_ACC_SET_EXPIREDTIME = 31,
DOT11_EVENT_ACC_QUERY_STATS = 32,
DOT11_EVENT_ACC_QUERY_STATS_ALL = 33,
DOT11_EVENT_REASSOCIATION_IND = 34,
DOT11_EVENT_REASSOCIATION_RSP = 35,
DOT11_EVENT_STA_QUERY_BSSID = 36,
DOT11_EVENT_STA_QUERY_SSID = 37,
DOT11_EVENT_EAP_PACKET = 41,
#ifdef RTL_WPA2_PREAUTH
DOT11_EVENT_EAPOLSTART_PREAUTH = 45,
DOT11_EVENT_EAP_PACKET_PREAUTH = 46,
#endif
DOT11_EVENT_WPA2_MULTICAST_CIPHER = 47,
DOT11_EVENT_WPA_MULTICAST_CIPHER = 48,
#ifdef WIFI_SIMPLE_CONFIG
DOT11_EVENT_WSC_SET_IE = 55,
DOT11_EVENT_WSC_PROBE_REQ_IND = 56,
DOT11_EVENT_WSC_PIN_IND = 57,
DOT11_EVENT_WSC_ASSOC_REQ_IE_IND = 58,
#ifdef INCLUDE_WPS
DOT11_EVENT_WSC_SET_MIB=42,
DOT11_EVENT_WSC_GET_MIB=43,
DOT11_EVENT_REQUEST_F_INCLUDE_WPS=44,
DOT11_EVENT_WSC_INIT_IND = 70,
DOT11_EVENT_WSC_EXIT_IND = 71,
DOT11_EVENT_WSC_TERM_IND = 72,
DOT11_EVENT_WSC_GETCONF_IND = 73,
DOT11_EVENT_WSC_PUTCONF_IND = 74,
DOT11_EVENT_WSC_LEDCONTROL_IND = 75,
DOT11_EVENT_WSC_SENDMSG_IND = 76,
DOT11_EVENT_WSC_PUTCONF = 77,
DOT11_EVENT_WSC_SOAP = 78,
DOT11_EVENT_WSC_PIN = 79,
DOT11_EVENT_WSC_PBC = 80,
DOT11_EVENT_WSC_SYS = 81,
DOT11_EVENT_WSC_PUTWLANREQUEST_IND = 82,
DOT11_EVENT_WSC_PUTPKT = 83,
DOT11_EVENT_WSC_GETDEVINFO = 84,
DOT11_EVENT_WSC_M2M4M6M8 = 85,
DOT11_EVENT_WSC_PUTWLANRESPONSE = 86,
DOT11_EVENT_WSC_PUTMESSAGE = 87,
DOT11_EVENT_WSC_PUTWLREQ_PROBEIND = 88,
DOT11_EVENT_WSC_PUTWLREQ_STATUSIND = 89,
#endif
#ifdef P2P_SUPPORT
DOT11_EVENT_WSC_SWITCH_MODE = 100,
DOT11_EVENT_WSC_STOP = 101,
#endif
/* support Assigned MAC Addr,Assigned SSID,dymanic change STA's PIN code, 2011-0505 */
DOT11_EVENT_WSC_SET_MY_PIN = 102,
DOT11_EVENT_WSC_SPEC_SSID = 103,
DOT11_EVENT_WSC_SPEC_MAC_IND = 104,
/* support Assigned MAC Addr,Assigned SSID,dymanic change STA's PIN code, 2011-0505 */
#endif
#ifdef CONFIG_RTK_MESH
DOT11_EVENT_PATHSEL_GEN_RREQ = 59,
DOT11_EVENT_PATHSEL_GEN_RERR = 60,
DOT11_EVENT_PATHSEL_RECV_RREQ = 61,
DOT11_EVENT_PATHSEL_RECV_RREP = 62,
DOT11_EVENT_PATHSEL_RECV_RERR = 63,
DOT11_EVENT_PATHSEL_RECV_PANN = 65,
DOT11_EVENT_PATHSEL_RECV_RANN = 66,
#endif // CONFIG_RTK_MESH
#ifdef CONFIG_RTL_WAPI_SUPPORT
DOT11_EVENT_WAPI_INIT_QUEUE =67,
DOT11_EVENT_WAPI_READ_QUEUE = 68,
DOT11_EVENT_WAPI_WRITE_QUEUE =69,
#endif
#if defined(CONFIG_RTL_COMAPI_CFGFILE) && defined(WIFI_SIMPLE_CONFIG)
#ifdef INCLUDE_WPS
DOT11_EVENT_WSC_START_IND = 90,
//EV_MODE, EV_STATUS, EV_MEHOD, EV_STEP, EV_OOB
DOT11_EVENT_WSC_MODE_IND = 91,
DOT11_EVENT_WSC_STATUS_IND = 92,
DOT11_EVENT_WSC_METHOD_IND = 93,
DOT11_EVENT_WSC_STEP_IND = 94,
DOT11_EVENT_WSC_OOB_IND = 95,
#else
DOT11_EVENT_WSC_START_IND = 70,
//EV_MODE, EV_STATUS, EV_MEHOD, EV_STEP, EV_OOB
DOT11_EVENT_WSC_MODE_IND = 71,
DOT11_EVENT_WSC_STATUS_IND = 72,
DOT11_EVENT_WSC_METHOD_IND = 73,
DOT11_EVENT_WSC_STEP_IND = 74,
DOT11_EVENT_WSC_OOB_IND = 75,
#endif
#endif
DOT11_EVENT_WSC_RM_PBC_STA=106,
#ifdef HS2_SUPPORT
/* Hotspot 2.0 Release 1 */
DOT11_EVENT_GAS_INIT_REQ = 110,
DOT11_EVENT_GAS_COMEBACK_REQ = 111,
DOT11_EVENT_HS2_SET_IE = 112,
DOT11_EVENT_HS2_GAS_RSP = 113,
DOT11_EVENT_HS2_GET_TSF = 114,
DOT11_EVENT_HS2_TSM_REQ = 115,
DOT11_EVENT_HS2_GET_RSN = 116,
DOT11_EVENT_HS2_GET_MMPDULIMIT=117,
#endif
#ifdef USER_ADDIE
DOT11_EVENT_USER_SETIE = 118,
#endif
#ifdef CONFIG_IEEE80211W
DOT11_EVENT_SET_PMF = 120,
DOT11_EVENT_GET_IGTK_PN = 121,
DOT11_EVENT_INIT_PMF = 122, // HS2 R2 logo test
#endif
#ifdef INDICATE_LINK_CHANGE
DOT11_EVENT_LINK_CHANGE_IND = 123,
#endif
DOT11_EVENT_UNKNOWN = 124
} DOT11_EVENT;
#ifdef WIFI_SIMPLE_CONFIG
enum {SET_IE_FLAG_BEACON=1, SET_IE_FLAG_PROBE_RSP=2, SET_IE_FLAG_PROBE_REQ=3,
SET_IE_FLAG_ASSOC_RSP=4, SET_IE_FLAG_ASSOC_REQ=5};
#endif
#ifdef HS2_SUPPORT
/* Hotspot 2.0 Release 1 */
enum {SET_IE_FLAG_INTERWORKING=1, SET_IE_FLAG_ADVT_PROTO=2, SET_IE_FLAG_ROAMING=3,
SET_IE_FLAG_HS2=4, SET_IE_FLAG_TIMEADVT=5, SET_IE_FLAG_TIMEZONE=6, SET_IE_FLAG_PROXYARP=7,
SET_IE_FLAG_MMPDULIMIT=10, SET_IE_FLAG_ICMPv4ECHO=11};
#endif
#ifdef USER_ADDIE
enum {SET_IE_FLAG_INSERT=1, SET_IE_FLAG_DELETE=2};
#endif
typedef struct _DOT11_GENERAL{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char *Data;
}DOT11_GENERAL;
typedef struct _DOT11_NOEVENT{
unsigned char EventId;
unsigned char IsMoreEvent;
}DOT11_NO_EVENT;
typedef struct _DOT11_REQUEST{
unsigned char EventId;
}DOT11_REQUEST;
typedef struct _DOT11_WPA2_MULTICAST_CIPHER{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char MulticastCipher;
}DOT11_WPA2_MULTICAST_CIPHER;
typedef struct _DOT11_WPA_MULTICAST_CIPHER{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char MulticastCipher;
}DOT11_WPA_MULTICAST_CIPHER;
typedef struct _DOT11_ASSOCIATION_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned short RSNIELen;
char RSNIE[MAXRSNIELEN]; // include ID and Length by kenny
}DOT11_ASSOCIATION_IND;
typedef struct _DOT11_ASSOCIATION_RSP{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned char Status;
}DOT11_ASSOCIATIIN_RSP;
typedef struct _DOT11_REASSOCIATION_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned short RSNIELen;
char RSNIE[MAXRSNIELEN];
char OldAPaddr[MACADDRLEN];
}DOT11_REASSOCIATION_IND;
typedef struct _DOT11_REASSOCIATION_RSP{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned char Status;
char CurrAPaddr[MACADDRLEN];
}DOT11_REASSOCIATIIN_RSP;
typedef struct _DOT11_AUTHENTICATION_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
}DOT11_AUTHENTICATION_IND;
typedef struct _DOT11_REAUTHENTICATION_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
}DOT11_REAUTHENTICATION_IND;
#ifdef WIFI_SIMPLE_CONFIG
typedef struct _DOT11_PROBE_REQUEST_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned short ProbeIELen;
char ProbeIE[PROBEIELEN];
}DOT11_PROBE_REQUEST_IND;
typedef struct _DOT11_WSC_ASSOC_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned short AssocIELen;
char AssocIE[PROBEIELEN];
unsigned char wscIE_included;
}DOT11_WSC_ASSOC_IND;
typedef struct _DOT11_GETSET_MIB {
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char cmd[50];
}DOT11_GETSET_MIB;
#endif
typedef struct _DOT11_DEAUTHENTICATION_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned long tx_packets; // == transmited packets
unsigned long rx_packets; // == received packets
unsigned long tx_bytes; // == transmited bytes
unsigned long rx_bytes; // == received bytes
unsigned long Reason;
}DOT11_DEAUTHENTICATION_IND;
typedef struct _DOT11_DISASSOCIATION_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned long tx_packets; // == transmited packets
unsigned long rx_packets; // == received packets
unsigned long tx_bytes; // == transmited bytes
unsigned long rx_bytes; // == received bytes
unsigned long Reason;
}DOT11_DISASSOCIATION_IND;
typedef struct _DOT11_DISCONNECT_REQ{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned short Reason;
char MACAddr[MACADDRLEN];
}DOT11_DISCONNECT_REQ;
typedef struct _DOT11_SET_802DOT11{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char VariableType;
unsigned char VariableValue;
char MACAddr[MACADDRLEN];
}DOT11_SET_802DOT11;
typedef struct _DOT11_SET_KEY{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned long KeyIndex;
unsigned long KeyLen;
unsigned char KeyType;
unsigned char EncType;
unsigned char MACAddr[MACADDRLEN];
DOT11_KEY_RSC KeyRSC;
unsigned char KeyMaterial[64];
}DOT11_SET_KEY;
typedef struct _DOT11_DELETE_KEY{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned char KeyType;
}DOT11_DELETE_KEY;
typedef struct _DOT11_SET_RSNIE{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned short Flag;
unsigned short RSNIELen;
char RSNIE[MAXRSNIELEN];
char MACAddr[MACADDRLEN];
}DOT11_SET_RSNIE;
typedef struct _DOT11_SET_PORT{
unsigned char EventId;
unsigned char PortStatus;
unsigned char PortType;
unsigned char MACAddr[MACADDRLEN];
}DOT11_SET_PORT;
typedef struct _DOT11_GKEY_TSC{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char KeyTSC[8];
}DOT11_GKEY_TSC;
typedef struct _DOT11_MIC_FAILURE{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
}DOT11_MIC_FAILURE;
typedef struct _DOT11_STA_QUERY_BSSID{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned long IsValid;
char Bssid[MACADDRLEN];
}DOT11_STA_QUERY_BSSID;
typedef struct _DOT11_STA_QUERY_SSID{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned long IsValid;
char ssid[32];
int ssid_len;
}DOT11_STA_QUERY_SSID;
typedef struct _DOT11_EAPOL_START{
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
}DOT11_EAPOL_START;
typedef struct _DOT11_SET_EXPIREDTIME{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char MACAddr[MACADDRLEN];
unsigned long ExpireTime;
}DOT11_SET_EXPIREDTIME;
typedef struct _DOT11_QUERY_STATS{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char MACAddr[MACADDRLEN];
unsigned long IsSuccess;
unsigned long tx_packets; // == transmited packets
unsigned long rx_packets; // == received packets
unsigned long tx_bytes; // == transmited bytes
unsigned long rx_bytes; // == received bytes
}DOT11_QUERY_STATS;
typedef struct _DOT11_EAP_PACKET{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned short packet_len;
unsigned char packet[1550];
}DOT11_EAP_PACKET;
#ifdef INCLUDE_WPS
#ifndef CONFIG_MSC
typedef struct _DOT11_EVENT_PACKET{
unsigned char EventId;
unsigned char EventType;
unsigned short packet_len;
unsigned char packet[1550];
}DOT11_EVENT_PACKET;
#endif
#endif
typedef DOT11_ASSOCIATION_IND DOT11_AUTH_IND;
#ifdef WIFI_SIMPLE_CONFIG
typedef struct _DOT11_WSC_PIN_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char code[256];
} DOT11_WSC_PIN_IND;
#ifdef CONFIG_RTL_COMAPI_CFGFILE
typedef struct _DOT11_WSC_IND{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned int value;
} DOT11_WSC_IND;
#endif //CONFIG_RTL_COMAPI_CFGFILE
#endif
#define DOT11_AI_REQFI_CAPABILITIES 1
#define DOT11_AI_REQFI_LISTENINTERVAL 2
#define DOT11_AI_REQFI_CURRENTAPADDRESS 4
#define DOT11_AI_RESFI_CAPABILITIES 1
#define DOT11_AI_RESFI_STATUSCODE 2
#define DOT11_AI_RESFI_ASSOCIATIONID 4
typedef struct _DOT11_ASSOCIATION_INFO
{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char SupplicantAddress[MACADDRLEN];
UINT32 Length;
UINT16 AvailableRequestFixedIEs;
struct _DOT11_AI_REQFI {
UINT16 Capabilities;
UINT16 ListenInterval;
char CurrentAPAddress[MACADDRLEN];
} RequestFixedIEs;
UINT32 RequestIELength;
UINT32 OffsetRequestIEs;
UINT16 AvailableResponseFixedIEs;
struct _DOT11_AI_RESFI {
UINT16 Capabilities;
UINT16 StatusCode;
UINT16 AssociationId;
} ResponseFixedIEs;
UINT32 ResponseIELength;
UINT32 OffsetResponseIEs;
} DOT11_ASSOCIATION_INFO, *PDOT11_ASSOCIATION_INFO;
typedef struct _DOT11_INIT_QUEUE
{
unsigned char EventId;
unsigned char IsMoreEvent;
} DOT11_INIT_QUEUE, *PDOT11_INIT_QUEUE;
#ifdef USER_ADDIE
typedef struct _DOT11_SET_USERIE{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned short Flag;
unsigned short USERIELen;
char USERIE[256];
}DOT11_SET_USERIE;
#endif
//*------The following are defined to handle the event Queue for security event--------*/
// For Event Queue related function
void DOT11_InitQueue(DOT11_QUEUE *q);
#ifndef WITHOUT_ENQUEUE
int DOT11_EnQueue(unsigned long task_priv, DOT11_QUEUE *q, unsigned char *item, int itemsize);
int DOT11_DeQueue(unsigned long task_priv, DOT11_QUEUE *q, unsigned char *item, int *itemsize);
#endif
void DOT11_PrintQueue(DOT11_QUEUE *q);
char *DOT11_ErrMsgQueue(int err);
#define DOT11_IsEmptyQueue(q) (q->NumItem==0 ? 1:0)
#define DOT11_IsFullQueue(q) (q->NumItem==q->MaxItem? 1:0)
#define DOT11_NumItemQueue(q) q->NumItem
typedef enum{
ERROR_BUFFER_TOO_SMALL = -1,
ERROR_INVALID_PARA = -2,
ERROR_INVALID_RSNIE = -13,
ERROR_INVALID_MULTICASTCIPHER = -18,
ERROR_INVALID_UNICASTCIPHER = -19,
ERROR_INVALID_AUTHKEYMANAGE = -20,
ERROR_UNSUPPORTED_RSNEVERSION = -21,
ERROR_INVALID_CAPABILITIES = -22,
ERROR_MGMT_FRAME_PROTECTION_VIOLATION = -31
} INFO_ERROR;
#define RSN_STRERROR_BUFFER_TOO_SMALL "Input Buffer too small"
#define RSN_STRERROR_INVALID_PARAMETER "Invalid RSNIE Parameter"
#define RSN_STRERROR_INVALID_RSNIE "Invalid RSNIE"
#define RSN_STRERROR_INVALID_MULTICASTCIPHER "Multicast Cipher is not valid"
#define RSN_STRERROR_INVALID_UNICASTCIPHER "Unicast Cipher is not valid"
#define RSN_STRERROR_INVALID_AUTHKEYMANAGE "Authentication Key Management Protocol is not valid"
#define RSN_STRERROR_UNSUPPORTED_RSNEVERSION "Unsupported RSNE version"
#define RSN_STRERROR_INVALID_CAPABILITIES "Invalid RSNE Capabilities"
#define DOT11_s2n(s,c) (*((c))=(unsigned char)(((s)>> 8)&0xff), \
*((c)+1)=(unsigned char)(((s) )&0xff))
#define DOT11_n2s(c,s) (s =((unsigned short)(*((c))))<< 8, \
s|=((unsigned short)(*((c)+1))))
#define DOT11_lc2s(bc,s) (s = ((unsigned short)(*((bc)+1)))<< 8, \
s |= ((unsigned short)(*((bc)))))
void DOT11_Dump(char *fun, UINT8 *buf, int size, char *comment);
typedef enum _COUNTERMEASURE_TEST
{
TEST_TYPE_PAIRWISE_ERROR = 0,
TEST_TYPE_GROUP_ERROR = 1,
TEST_TYPE_SEND_BAD_UNICAST_PACKET = 2,
TEST_TYPE_SEND_BAD_BROADCAST_PACKET = 3
} COUNTERMEASURE_TEST;
#define MIC_TIMER_PERIOD RTL_SECONDS_TO_JIFFIES(60) //unit: 10 milli-seconds
#define REJECT_ASSOC_PERIOD RTL_SECONDS_TO_JIFFIES(60)
//*---------- The followings are for processing of RSN Information Element------------*/
#define RSN_ELEMENT_ID 0xDD
#define RSN_VER1 0x01
#define DOT11_MAX_CIPHER_ALGORITHMS 0x0a
#define DOT11_GROUPFLAG 0x02
#define DOT11_REPLAYBITSSHIFT 2
#define DOT11_REPLAYBITS 3
#define IsPairwiseUsingDefaultKey(Cap) ((Cap[0] & DOT11_GROUPFLAG)?TRUE:FALSE)
#define IsPreAuthentication(Cap) ((Cap[0] & 0x01)?TRUE:FALSE)
#define DOT11_GetNumOfRxTSC(Cap) (2<<((Cap[0] >> DOT11_REPLAYBITSSHIFT) & DOT11_REPLAYBITS))
#if defined(PACK_STRUCTURE) || defined(__ECOS)
#pragma pack(1)
#endif
typedef struct _DOT11_RSN_IE_HEADER {
UINT8 ElementID;
UINT8 Length;
UINT8 OUI[4];
UINT16 Version;
}DOT11_RSN_IE_HEADER;
typedef struct _DOT11_RSN_IE_SUITE{
UINT8 OUI[3];
UINT8 Type;
}DOT11_RSN_IE_SUITE;
typedef struct _DOT11_RSN_IE_COUNT_SUITE{
UINT16 SuiteCount;
DOT11_RSN_IE_SUITE dot11RSNIESuite[DOT11_MAX_CIPHER_ALGORITHMS];
} __WLAN_ATTRIB_PACK__ DOT11_RSN_IE_COUNT_SUITE, *PDOT11_RSN_IE_COUNT_SUITE;
typedef union _DOT11_RSN_CAPABILITY{
UINT16 shortData;
UINT8 charData[2];
#ifdef RTL_WPA2
struct
{
#ifdef _BIG_ENDIAN_
#ifdef CONFIG_IEEE80211W
unsigned short MFPC:1; // B7
unsigned short MFPR:1; // B6
#else
unsigned short Reserved1:2; // B7 B6
#endif
unsigned short GtksaReplayCounter:2; // B5 B4
unsigned short PtksaReplayCounter:2; // B3 B2
unsigned short NoPairwise:1; // B1
unsigned short PreAuthentication:1; // B0
unsigned short Reserved2:8;
#else
unsigned short PreAuthentication:1; // B0
unsigned short NoPairwise:1; // B1
unsigned short PtksaReplayCounter:2; // B3 B2
unsigned short GtksaReplayCounter:2; // B5 B4
#ifdef CONFIG_IEEE80211W
unsigned short MFPR:1; // B6
unsigned short MFPC:1; // B7
#else
unsigned short Reserved1:2; // B7 B6
#endif
unsigned short Reserved2:8;
#endif
} __WLAN_ATTRIB_PACK__ field;
#else
struct
{
#ifdef _BIG_ENDIAN_
unsigned short PreAuthentication:1;
unsigned short PairwiseAsDefaultKey:1;
unsigned short NumOfReplayCounter:2;
unsigned short Reserved:12;
#else
unsigned short Reserved1:4;
unsigned short NumOfReplayCounter:2;
unsigned short PairwiseAsDefaultKey:1;
unsigned short PreAuthentication:1;
unsigned short Reserved2:8;
#endif
} __WLAN_ATTRIB_PACK__ field;
#endif
} __WLAN_ATTRIB_PACK__ DOT11_RSN_CAPABILITY;
#ifdef HS2_SUPPORT
/* Hotspot 2.0 Release 1 */
#define MAX_GAS_CONTENTS_LEN PRE_ALLOCATED_BUFSIZE
typedef struct _DOT11_HS2_GAS_REQ{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char Dialog_token;
unsigned char MACAddr[MACADDRLEN];
unsigned char Advt_proto;
unsigned short Reqlen;
unsigned char Req[MAX_GAS_CONTENTS_LEN];
}DOT11_HS2_GAS_REQ;
typedef struct _DOT11_HS2_GAS_RSP{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char Dialog_token;
unsigned char Action;
unsigned char MACAddr[MACADDRLEN];
unsigned short StatusCode;
unsigned short Comeback_delay;
unsigned char Rsp_fragment_id;
unsigned char Advt_proto;
unsigned short Rsplen;
unsigned char Rsp[MAX_GAS_CONTENTS_LEN];
}DOT11_HS2_GAS_RSP;
typedef struct _DOT11_HS2_TSM_REQ{
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char Dialog_token;
unsigned char MACAddr[MACADDRLEN];
unsigned char Req_mode;
unsigned char Validity_intval;
unsigned short Disassoc_timer;
unsigned char term_len;
unsigned char url_len;
unsigned char list_len;
unsigned char terminal_dur[12];
unsigned char Session_url[50];
unsigned char Candidate_list[100];
}DOT11_HS2_TSM_REQ;
#endif
#ifdef CONFIG_IEEE80211W
/*HS2 R2 logo test*/
typedef struct _DOT11_INIT_11W_Flags {
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char dot11IEEE80211W;
unsigned char dot11EnableSHA256;
}DOT11_INIT_11W_Flags;
typedef struct _DOT11_SET_11W_Flags {
unsigned char EventId;
unsigned char IsMoreEvent;
unsigned char macAddr[MACADDRLEN];
unsigned char isPMF;
}DOT11_SET_11W_Flags;
typedef struct _DOT11_SA_QUERY_RSP {
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned char trans_id[2];
}DOT11_SA_QUERY_RSP;
#endif // CONFIG_IEEE80211W
#ifdef INDICATE_LINK_CHANGE
typedef struct _DOT11_LINK_CHANGE_IND {
unsigned char EventId;
unsigned char IsMoreEvent;
char MACAddr[MACADDRLEN];
unsigned char LinkStatus;
} DOT11_LINK_CHANGE_IND;
#endif
#if defined(PACK_STRUCTURE) || defined(__ECOS)
#pragma pack()
#endif
#endif // _8192CD_SECURITY_H_
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_sme.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_tkip.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_tx.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_tx.h
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/*
* Header file define some tx inline functions
*
* $Id: 8192cd_tx.h,v 1.2 2010/01/29 09:39:16 jimmylin Exp $
*
* Copyright (c) 2009 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192CD_TX_H_
#define _8192CD_TX_H_
#ifndef WLAN_HAL_INTERNAL_USED
#include "./8192cd_cfg.h"
#include "./8192cd.h"
#include "./8192cd_util.h"
#ifdef CONFIG_RTK_MESH
#define rtl8192cd_wlantx(p,t) rtl8192cd_firetx(p, t)
#endif
enum _TX_QUEUE_ {
MGNT_QUEUE = 0,
BK_QUEUE = 1,
BE_QUEUE = 2,
VI_QUEUE = 3,
VO_QUEUE = 4,
HIGH_QUEUE = 5,
#if defined(CONFIG_PCI_HCI)
#if defined(CONFIG_WLAN_HAL)
HIGH_QUEUE1 = 6,
HIGH_QUEUE2 = 7,
HIGH_QUEUE3 = 8,
HIGH_QUEUE4 = 9,
HIGH_QUEUE5 = 10,
HIGH_QUEUE6 = 11,
HIGH_QUEUE7 = 12,
BEACON_QUEUE = 13
#else
BEACON_QUEUE = 6,
#endif
#elif defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
BEACON_QUEUE = 6,
TXCMD_QUEUE = 7,
HW_QUEUE_ENTRY = 8
#endif
};
#define MCAST_QNUM HIGH_QUEUE
#if defined(CONFIG_NETDEV_MULTI_TX_QUEUE) || defined(CONFIG_SDIO_TX_FILTER_BY_PRI)
enum _NETDEV_TX_QUEUE_ {
_NETDEV_TX_QUEUE_VO = 0,
_NETDEV_TX_QUEUE_VI = 1,
_NETDEV_TX_QUEUE_BE = 2,
_NETDEV_TX_QUEUE_BK = 3,
_NETDEV_TX_QUEUE_ALL
};
#endif
#ifndef RTL_MANUAL_EDCA
#define PRI_TO_QNUM(priority, q_num, wifi_specific) { \
if ((priority == 0) || (priority == 3)) \
q_num = BE_QUEUE; \
else if ((priority == 7) || (priority == 6)) \
q_num = VO_QUEUE; \
else if ((priority == 5) || (priority == 4)) \
q_num = VI_QUEUE; \
else \
q_num = BK_QUEUE; \
}
#endif
static __inline__ unsigned int get_mpdu_len(struct tx_insn *txcfg, unsigned int fr_len)
{
return (txcfg->hdr_len + txcfg->llc + txcfg->iv + txcfg->icv + txcfg->mic + _CRCLNG_ + fr_len);
}
#ifdef CONFIG_PCI_HCI
// the purpose if actually just to link up all the desc in the same q
static __inline__ void init_txdesc(struct rtl8192cd_priv *priv, struct tx_desc *pdesc,
unsigned long ringaddr, unsigned int i)
{
#ifdef CONFIG_RTL_8812_SUPPORT
if(GET_CHIP_VER(priv)== VERSION_8812E){
if (i == (CURRENT_NUM_TX_DESC - 1))
(pdesc + i)->Dword12 = set_desc(ringaddr); // NextDescAddress
else
(pdesc + i)->Dword12 = set_desc(ringaddr + (i+1) * sizeof(struct tx_desc)); // NextDescAddress
} else
#endif
{
if (i == (CURRENT_NUM_TX_DESC - 1))
(pdesc + i)->Dword10 = set_desc(ringaddr); // NextDescAddress
else
(pdesc + i)->Dword10 = set_desc(ringaddr + (i+1) * sizeof(struct tx_desc)); // NextDescAddress
}
}
#define txdesc_rollover(ptxdesc, ptxhead) (*ptxhead = (*ptxhead + 1) % CURRENT_NUM_TX_DESC)
#define txdesc_rollback(ptxhead) (*ptxhead = (*ptxhead == 0)? (CURRENT_NUM_TX_DESC - 1) : (*ptxhead - 1))
static __inline__ void tx_poll(struct rtl8192cd_priv *priv, int q_num)
{
unsigned char val = 0;
#ifdef CONFIG_RTL8671
#ifdef CONFIG_CPU_RLX4181
r3k_flush_dcache_range(0,0);
#endif
#endif
switch (q_num) {
case MGNT_QUEUE:
val = MGQ_POLL;
break;
case BK_QUEUE:
val = BKQ_POLL;
break;
case BE_QUEUE:
val = BEQ_POLL;
break;
case VI_QUEUE:
val = VIQ_POLL;
break;
case VO_QUEUE:
val = VOQ_POLL;
break;
case HIGH_QUEUE:
val = HQ_POLL;
break;
default:
break;
}
RTL_W8(PCIE_CTRL_REG, val);
}
#endif // CONFIG_PCI_HCI
#ifdef CONFIG_PCI_HCI
#define desc_copy(dst, src) memcpy(dst, src, 32)
#define descinfo_copy(d, s) \
do { \
struct tx_desc_info *dst = (struct tx_desc_info *)d; \
struct tx_desc_info *src = (struct tx_desc_info *)s; \
dst->type = src->type; \
dst->len = src->len; \
dst->rate = src->rate; \
} while (0)
#endif
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
#define desc_copy(dst, src) memcpy(dst, src, TXDESC_SIZE)
#define descinfo_copy(d, s) \
do { \
struct tx_desc_info *dst = (struct tx_desc_info *)d; \
struct tx_desc_info *src = (struct tx_desc_info *)s; \
dst->type = src->type; \
dst->rate = src->rate; \
} while (0)
#endif
#ifdef WDS
#define DECLARE_TXINSN(A) struct tx_insn A; \
do { \
memset(&A, 0, sizeof(struct tx_insn)); \
A.wdsIdx = -1; \
} while (0)
#define DECLARE_TXCFG(P, TEMPLATE) struct tx_insn *P = &(TEMPLATE); \
do { \
memset(P, 0, sizeof(struct tx_insn)); \
P->wdsIdx = -1; \
} while (0)
#else
#define DECLARE_TXINSN(A) struct tx_insn A; \
do { \
memset(&A, 0, sizeof(struct tx_insn)); \
} while (0)
#define DECLARE_TXCFG(P, TEMPLATE) struct tx_insn* P = &(TEMPLATE); \
do { \
memset(P, 0, sizeof(struct tx_insn)); \
} while (0)
#endif // WDS
#endif //#ifndef WLAN_HAL_INTERNAL_USED
#endif // _8192CD_TX_H_
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_util.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192cd_util.h
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192d_hw.c
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#define _8192D_HW_C_
#ifdef __KERNEL__
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <asm/unistd.h>
#endif
#include "./8192cd_cfg.h"
#include "./8192cd.h"
#include "./8192cd_hw.h"
#include "./8192cd_headers.h"
#include "./8192cd_debug.h"
#ifdef CONFIG_RTL_92D_SUPPORT
#if defined(CONFIG_RTL_819X) && defined(USE_RLX_BSP)
#if defined(CONFIG_OPENWRT_SDK) && !defined(CONFIG_ARCH_CPU_RLX)
#include <asm/mach-realtek/bspchip.h>
#else
#include <bsp/bspchip.h>
#endif //CONFIG_OPENWRT_SDK
#endif
#ifndef USE_OUT_SRC
#define IQK_ADDA_REG_NUM 16
#endif
#ifdef CONFIG_RTL_92D_DMDP
extern u32 if_priv[];
__inline__ unsigned char DMDP_RTL_R8(unsigned int phy, unsigned int reg)
{
struct rtl8192cd_priv *priv;
//printk("++++++++++++++++++++++++++%s(%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return -1;
}
priv = (struct rtl8192cd_priv *)if_priv[phy];
return RTL_R8(reg);
}
__inline__ void DMDP_RTL_W8(unsigned int phy, unsigned int reg, unsigned char val8)
{
struct rtl8192cd_priv *priv;
//printk("++++++++++++++++++++++++++%s(%x,%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg, val8);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return;
}
priv = (struct rtl8192cd_priv *)if_priv[phy];
RTL_W8(reg, val8);
}
__inline__ unsigned short DMDP_RTL_R16(unsigned int phy, unsigned int reg)
{
struct rtl8192cd_priv *priv;
//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return -1;
}
priv = (struct rtl8192cd_priv *)if_priv[phy];
return RTL_R16(reg);
}
__inline__ void DMDP_RTL_W16(unsigned int phy, unsigned int reg, unsigned short val16)
{
struct rtl8192cd_priv *priv;
//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return;
}
priv = (struct rtl8192cd_priv *)if_priv[phy];
RTL_W16(reg, val16);
}
__inline__ unsigned int DMDP_RTL_R32(unsigned int phy, unsigned int reg)
{
struct rtl8192cd_priv *priv;
//printk("++++++++++++++++++++++++++%s(%x)++++++++++++++++++++++++++\n", __FUNCTION__, reg);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return -1;
}
priv = (struct rtl8192cd_priv *)if_priv[phy];
return RTL_R32(reg);
}
__inline__ void DMDP_RTL_W32(unsigned int phy, unsigned int reg, unsigned int val32)
{
struct rtl8192cd_priv *priv;
//printk("++++++++++++++++++++++++++%s(%x, %x)++++++++++++++++++++++++++\n", __FUNCTION__, reg, val32);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return;
}
priv = (struct rtl8192cd_priv *)if_priv[phy];
RTL_W32(reg, val32);
}
unsigned int DMDP_PHY_QueryBBReg(unsigned int phy, unsigned int RegAddr, unsigned int BitMask)
{
//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return -1;
}
return PHY_QueryBBReg((struct rtl8192cd_priv *)if_priv[phy], RegAddr, BitMask);
}
void DMDP_PHY_SetBBReg(unsigned int phy, unsigned int RegAddr, unsigned int BitMask, unsigned int Data)
{
//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return;
}
PHY_SetBBReg((struct rtl8192cd_priv *)if_priv[phy], RegAddr, BitMask, Data);
}
unsigned int DMDP_PHY_QueryRFReg(unsigned int phy, RF92CD_RADIO_PATH_E eRFPath,
unsigned int RegAddr, unsigned int BitMask, unsigned int dbg_avoid)
{
//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return -1;
}
return PHY_QueryRFReg((struct rtl8192cd_priv *)if_priv[phy], eRFPath, RegAddr, BitMask, dbg_avoid);
}
void DMDP_PHY_SetRFReg(unsigned int phy, RF92CD_RADIO_PATH_E eRFPath, unsigned int RegAddr,
unsigned int BitMask, unsigned int Data)
{
//printk("++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __FUNCTION__);
if (phy >= NUM_WLAN_IFACE || phy < 0) {
printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy);
return;
}
PHY_SetRFReg((struct rtl8192cd_priv *)if_priv[phy], eRFPath, RegAddr, BitMask, Data);
}
#endif //CONFIG_RTL_92D_DMDP
void SetSYN_para(struct rtl8192cd_priv *priv, unsigned char channel)
{
unsigned int eRFPath, tmp=0;
unsigned int idx=-1, i;
unsigned int SYN_PARA[8][8] = {
{0xe43be, 0xfc638, 0x77c0a, 0xde471, 0xd7110, 0x8cb04, 0x00000, 0x00000}, // CH36-140 20MHz
{0xe43be, 0xfc078, 0xf7c1a, 0xe0c71, 0xd7550, 0xacb04, 0x00000, 0x00000}, // CH36-140 40MHz
{0xe43bf, 0xff038, 0xf7c0a, 0xde471, 0xe5550, 0xacb04, 0x00000, 0x00000}, // CH149, 155, 161
{0xe43bf, 0xff079, 0xf7c1a, 0xde471, 0xe5550, 0xacb04, 0x00000, 0x00000}, // CH151, 153, 163, 165
{0xe43bf, 0xff038, 0xf7c1a, 0xde471, 0xd7550, 0xacb04, 0x00000, 0x00000}, // CH157, 159
#ifdef SW_LCK_92D
{0x643bc, 0xfc038, 0x77c1a, 0x00000, 0x00000, 0x00000, 0x61289, 0x01840}, // CH1,2,4,9,10,11,12
{0x643bc, 0xfc038, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x61289, 0x01840}, // CH3,13,14
{0x243bc, 0xfc438, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x6128b, 0x0fc41} // CH5-8
#else
{0x643bc, 0xfc038, 0x77c1a, 0x00000, 0x00000, 0x00000, 0x41289, 0x01840}, // CH1,2,4,9,10,11,12
{0x643bc, 0xfc038, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x41289, 0x01840}, // CH3,13,14
{0x243bc, 0xfc438, 0x07c1a, 0x00000, 0x00000, 0x00000, 0x4128b, 0x0fc41} // CH5-8
#endif
};
if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G)
eRFPath = RF92CD_PATH_B;
else
eRFPath = RF92CD_PATH_A;
if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){
if (channel >=36 && channel <=140){
if (!priv->pshare->CurrentChannelBW)
idx = 0;
else
idx = 1;
} else if (channel == 149 || channel == 155 || channel == 161)
idx = 2;
else if (channel==151 || channel==153 || channel==163 || channel==165)
idx = 3;
else if (channel==157 || channel==159)
idx = 4;
} else {
if (channel==1 || channel==2 || channel==4 || channel==9 || channel==10 || channel==11 || channel==12)
idx = 5;
else if (channel==3 || channel==13 || channel==14)
idx = 6;
else if (channel>=5 && channel<=8)
idx = 7;
}
if (idx==-1){
DEBUG_ERR("No suitable channel (%d) for setting synthersizer parameter!\n", channel);
return;
}
for (i=0;i<8;i++){
#ifdef CONFIG_RTL_92D_DMDP
if (i==0 && (idx>=0 && idx <=4) &&
(priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY))
tmp = 0xe439d;
else
#endif
tmp = SYN_PARA[idx][i];
if (tmp!=0) {
#ifdef CONFIG_RTL_92D_DMDP
if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY && eRFPath == RF92CD_PATH_B) {
DMDP_PHY_SetRFReg(1, RF92CD_PATH_A, (0x25+i), bMask20Bits, tmp);
//DEBUG_TRACE("DMDP_PHY_SetRFReg(1, %d, 0x%x, bMask20Bits, 0x%x)\n", eRFPath, (0x25+i), tmp);
} else
#endif
{
PHY_SetRFReg(priv, eRFPath, (0x25+i), bMask20Bits, tmp);
//DEBUG_TRACE("PHY_SetRFReg(priv, %d, 0x%x, bMask20Bits, 0x%x)\n", eRFPath, (0x25+i), tmp);
}
if (i==3)
priv->pshare->RegRF28[eRFPath] = tmp;
}
}
}
unsigned int IMR_SET_N[3][11] = {
{0x00ff0, 0x4400f, 0x00ff0, 0x00000, 0x00000, 0x00000, 0x00000, 0x00000, 0x64888, 0xe266c, 0x00090}, //G-mode
{0x22880, 0x4470f, 0x55880, 0x00070, 0x88000, 0x00000, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090}, //36-64
{0x44880, 0x4477f, 0x77880, 0x00070, 0x88000, 0x00000, 0x880b0, 0x00000, 0x64b82, 0xe466c, 0x00090}, // 100-165
};
void SetIMR_n(struct rtl8192cd_priv *priv, unsigned char channel)
{
unsigned int eRFPath, curMaxRFPath;
int imr_idx = -1;
unsigned char temp_800;
#ifdef CONFIG_RTL_92D_DMDP
if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)
curMaxRFPath = RF92CD_PATH_B;
else
#endif
curMaxRFPath = RF92CD_PATH_MAX;
if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G)
imr_idx = 0;
else {
if (channel>=36 && channel <=64)
imr_idx = 1;
else
imr_idx = 2;
}
PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
temp_800 = PHY_QueryBBReg(priv, rFPGA0_RFMOD, 0x0f000000);
PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, 0);
for(eRFPath = RF92CD_PATH_A; eRFPath < curMaxRFPath; eRFPath++) {
int i;
PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x70000);
//DEBUG_TRACE("IMR [0x00] %05x\n", PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits,1));
//delay_us(5);
for (i=0;i<11;i++) {
PHY_SetRFReg(priv, eRFPath, (0x2f+i), bMask20Bits, IMR_SET_N[imr_idx][i]);
//DEBUG_TRACE("IMR [0x%x] %05x\n", (0x2f+i), PHY_QueryRFReg(priv, eRFPath, (0x2f+i), bMask20Bits,1));
//delay_us(5);
}
if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_2G)
PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x32fff);
else
PHY_SetRFReg(priv, eRFPath, 0x00, bMask20Bits, 0x32c9a);
//DEBUG_TRACE("IMR [0x00] %05x\n", PHY_QueryRFReg(priv, eRFPath, 0x00, bMask20Bits,1));
//delay_us(5);
}
PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, temp_800);
PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
}
/*
* Follow WS-20101228-Willis-xxxx dynamic parameter-R00
*/
void Update92DRFbyChannel(struct rtl8192cd_priv *priv, unsigned char channel)
{
#ifdef RTL8192D_INT_PA
u8 eRFPath = 0, curMaxRFPath;
if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)
curMaxRFPath = RF92CD_PATH_B;
else
curMaxRFPath = RF92CD_PATH_MAX;
if (priv->pshare->rf_ft_var.use_intpa92d){
for(eRFPath = RF92CD_PATH_A; eRFPath <curMaxRFPath; eRFPath++) {
if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){
if (channel>=36 && channel<=64){
PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01a00);
PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0x40443);
PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00eb5);
//PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f);
PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x89bec);
//PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded);
PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a12);
delay_us(10);
PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a12);
PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a12);
}else if (channel>=100 && channel<=140){
PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01800);
PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0xc0443);
PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00730);
//PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f);
PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x896ee);
//PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded);
PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a52);
delay_us(10);
PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a52);
PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a52);
}else if (channel>=149 && channel<=165){
PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x01800);
PHY_SetRFReg(priv, eRFPath, 0x48, bMask20Bits, 0xc0443);
PHY_SetRFReg(priv, eRFPath, 0x49, bMask20Bits, 0x00730);
//PHY_SetRFReg(priv, eRFPath, 0x4a, bMask20Bits, 0x50f0f);
PHY_SetRFReg(priv, eRFPath, 0x4b, bMask20Bits, 0x896ee);
//PHY_SetRFReg(priv, eRFPath, 0x4c, bMask20Bits, 0x0dded);
PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x94a12);
delay_us(10);
PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x94a12);
PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x94a12);
}
}else{
PHY_SetRFReg(priv, eRFPath, 0x0b, bMask20Bits, 0x1c000);
PHY_SetRFReg(priv, eRFPath, 0x03, bMask20Bits, 0x18c63);
delay_us(10);
PHY_SetRFReg(priv, eRFPath, 0x04, bMask20Bits, 0x18c63);
PHY_SetRFReg(priv, eRFPath, 0x0e, bMask20Bits, 0x18c67);
}
}
}
#endif
if (priv->pmib->dot11RFEntry.phyBandSelect==PHY_BAND_5G){
//update fc_area
if (priv->pmib->dot11RFEntry.dot11channel<149)
PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 1);
else
PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 2);
// VCO_BF_LDO= 1.12V->1.27V for 40M spur issue
PHY_SetRFReg(priv, RF92CD_PATH_A, 0x2A, BIT(13)|BIT(12), 2);
// RX Ch36 40M spurs
if (channel==36){
priv->pshare->RegRF28[RF92CD_PATH_A] &= (~BIT(6));
priv->pshare->RegRF28[RF92CD_PATH_A] |= BIT(5);
PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, bMask20Bits, priv->pshare->RegRF28[RF92CD_PATH_A]);
//PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, BIT(6)|BIT(5), 0);
}
} else {
//update fc_area
PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 0);
}
}
int Load_92D_Firmware(struct rtl8192cd_priv *priv)
{
int fw_len, wait_cnt=0;
unsigned int CurPtr=0;
unsigned int WriteAddr;
unsigned int Temp;
unsigned char *ptmp;
#ifndef SMP_SYNC
unsigned long flags = 0;
#endif
#ifdef CONFIG_RTL8672
printk("val=%x\n",RTL_R8(0x80));
#endif
#ifdef MP_TEST
if (priv->pshare->rf_ft_var.mp_specific)
return TRUE;
#endif
printk("===> %s\n", __FUNCTION__);
SAVE_INT_AND_CLI(flags);
printk("Firmware check %x(%x)\n", RTL_R32(MCUFWDL), (RTL_R8(MCUFWDL) & MCUFWDL_RDY));
if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){
printk("<=== Firmware Downloaded\n");
goto check_fwdl_rdy;
}
wait_cnt=0;
while(RTL_R8(RF_CTRL) & FW_DL_INPROC){
wait_cnt++;
delay_ms(50);
}
#ifdef CONFIG_RTL_92D_DMDP
if (wait_cnt==0) {
if (priv->pshare->wlandev_idx == 0)
RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC);
else {
if (RTL_R8(RSV_MAC0_CTRL) & MAC0_EN)
goto check_fwdl_rdy;
else
RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC);
}
} else {
if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){
printk("<=== Firmware Downloaded\n");
RESTORE_INT(flags);
return TRUE;
}else{
RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC);
}
}
#else
if (wait_cnt==0) {
RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC);
} else {
if (RTL_R8(MCUFWDL) & MCUFWDL_RDY){
printk("<=== Firmware Downloaded\n");
RESTORE_INT(flags);
return TRUE;
}else{
RTL_W8(RF_CTRL, RTL_R8(RF_CTRL)|FW_DL_INPROC);
}
}
#endif
if ((priv->pshare->fw_signature & 0xfff0 ) == 0x92D0)
ptmp = data_rtl8192dfw_n_start + RT_8192CD_FIRMWARE_HDR_SIZE;
else
ptmp = data_rtl8192dfw_n_start;
fw_len = (int)(data_rtl8192dfw_n_end - ptmp);
printk("[%s][rtl8192dfw_n]\n",__FUNCTION__);
// Disable SIC
RTL_W16(GPIO_MUXCFG, (RTL_R16(GPIO_MUXCFG) & 0xff) | HTP_EN);
delay_ms(1);
// Enable MCU
RTL_W16(SYS_FUNC_EN, (RTL_R16(SYS_FUNC_EN) & 0x0ff) | FEN_MREGEN
| FEN_HWPDN | FEN_DIO_RF | FEN_ELDR | FEN_DCORE |FEN_CPUEN | FEN_PCIED);
delay_ms(1);
#ifdef CONFIG_RTL8672
RTL_W8(APS_FSMCO, RTL_R8(APS_FSMCO) | PFM_ALDN);
delay_ms(1); //czyao
#endif
// Load SRAM
WriteAddr = 0x1000;
RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) | MCUFWDL_EN);
delay_ms(1);
RTL_W32(MCUFWDL, RTL_R32(MCUFWDL) & 0xfff0ffff);
delay_ms(1);
while (CurPtr < fw_len) {
if ((CurPtr+4) > fw_len) {
// Reach the end of file.
while (CurPtr < fw_len) {
Temp = *(ptmp + CurPtr);
RTL_W8(WriteAddr, (unsigned char)Temp);
WriteAddr++;
CurPtr++;
}
} else {
// Write FW content to memory.
Temp = *((unsigned int *)(ptmp + CurPtr));
Temp = cpu_to_le32(Temp);
RTL_W32(WriteAddr, Temp);
WriteAddr += 4;
if(WriteAddr == 0x2000) {
unsigned char tmp = RTL_R8(MCUFWDL+2);
tmp += 1;
WriteAddr = 0x1000;
RTL_W8(MCUFWDL+2, tmp) ;
delay_ms(10);
// printk("\n[CurPtr=%x, 0x82=%x]\n", CurPtr, RTL_R8(0x82));
}
CurPtr += 4;
}
}
watchdog_kick();
RTL_W8(TCR+3, 0x7f);
RTL_W8(MCUFWDL, (RTL_R8(MCUFWDL) & 0xfe) | MCUFWDL_RDY);
delay_ms(1);
//RTL_W8(RF_CTRL, RTL_R8(RF_CTRL) | BIT(6));
RTL_W8(RF_CTRL, RTL_R8(RF_CTRL) & (~FW_DL_INPROC));
delay_ms(1);
check_fwdl_rdy:
printk("<=== %s\n", __FUNCTION__);
// check if firmware is ready
wait_cnt = 0;
#ifdef CONFIG_RTL_92D_DMDP
if (priv->pshare->wlandev_idx == 0)
#endif
{
while (!(RTL_R8(RSV_MAC0_FWCTRL) & MAC0_WINTINI_RDY)) {
if (++wait_cnt > 10) {
RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) & (~MCUFWDL_RDY));
RESTORE_INT(flags);
DEBUG_ERR("8192d mac0 firmware not ready\n");
return FALSE;
}
delay_ms(2*wait_cnt);
}
}
#ifdef CONFIG_RTL_92D_DMDP
else {
while (!(RTL_R8(RSV_MAC1_FWCTRL) & MAC1_WINTINI_RDY)) {
if (++wait_cnt > 10) {
RTL_W8(MCUFWDL, RTL_R8(MCUFWDL) & (~MCUFWDL_RDY));
RESTORE_INT(flags);
DEBUG_ERR("8192d mac1 firmware not ready\n");
return FALSE;
}
delay_ms(2*wait_cnt);
}
}
#endif
RESTORE_INT(flags);
#ifdef CONFIG_RTL8672
printk("val=%x\n",RTL_R8(MCUFWDL));
#endif
return TRUE;
}
/*
* 92DE Operation Mode
*/
void UpdateBBRFVal8192DE(struct rtl8192cd_priv *priv)
{
u8 eRFPath = 0, curMaxRFPath;
//u32 u4RegValue=0;
//Update BB
if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) {
/*
* 5G
*/
//r_select_5G for path_A/B
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(16), 0x1);
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(0), 0x1);
//rssi_table_select:index 0 for 2.4G.1~3 for 5G
PHY_SetBBReg(priv, rOFDM0_AGCRSSITable, BIT(7) | BIT(6), 0x01);
//5G PA power on
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(6))>>6);
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(4))>>4);
//TRSW.TRSWB and PAPE2G mode table
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY){
// TRSW_2, TRSWB_2
PHY_SetBBReg(priv, 0x870, BIT(22)|BIT(21), 0);
// PAPE2G_2
PHY_SetBBReg(priv, 0x870, BIT(26), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(7))>>7);
PHY_SetBBReg(priv, 0x864, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(6))>>6);
}
// TRSW_1, TRSWB_1
PHY_SetBBReg(priv, 0x870, BIT(6)|BIT(5), 0);
// PAPE2G_1
PHY_SetBBReg(priv, 0x870, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(5))>>5);
PHY_SetBBReg(priv, 0x860, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(4))>>4);
#ifdef RTL8192D_INT_PA
if (!priv->pshare->rf_ft_var.use_intpa92d)
#endif
{
//5G PA power on
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), 0x1);
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), 0x1);
}
// 5G LNA on
PHY_SetBBReg(priv, 0xb30, 0x00f00000, 0x0);
//fc_area
if (priv->pmib->dot11RFEntry.dot11channel<149)
PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 1);
else
PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 2);
//cck_disable
PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x0);
//TX BB gain shift
#ifdef RTL8192D_INT_PA
if (priv->pshare->rf_ft_var.use_intpa92d){
PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x2d4000b5);
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x2d4000b5);
} else
#endif
{
PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x20000080);
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x20000080);
}
// Reset IQC
PHY_SetBBReg(priv, 0xc94, 0xF0000000, 0);
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, 0xc9c, 0xF0000000, 0);
//BB/DP IQC
PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x010170b8);
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x010170b8);
} else {
/*
* 2.4G
*/
// r_select_5G for path_A/B
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(16), 0x0);
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(0), 0);
//rssi_table_select:index 0 for 2.4G.1~3 for 5G
PHY_SetBBReg(priv, rOFDM0_AGCRSSITable, BIT(7) | BIT(6), 0x00);
//5G PA power on
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(31), 0x0);
PHY_SetBBReg(priv, rFPGA0_XAB_RFParameter, BIT(15), 0x0);
//TRSW.TRSWB and PAPE2G mode table
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY){
// TRSW_2
PHY_SetBBReg(priv, 0x870, BIT(21), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(7))>>7);
PHY_SetBBReg(priv, 0x864, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(6))>>6);
// TRSWB_2
PHY_SetBBReg(priv, 0x870, BIT(22), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(5))>>5);
PHY_SetBBReg(priv, 0x864, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(4))>>4);
// PAPE2G_2
PHY_SetBBReg(priv, 0x870, BIT(26), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(3))>>3);
PHY_SetBBReg(priv, 0x864, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(2))>>2);
}
// TRSW_1
PHY_SetBBReg(priv, 0x870, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(3))>>3);
PHY_SetBBReg(priv, 0x860, BIT(5), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(2))>>2);
// TRSWB_1
PHY_SetBBReg(priv, 0x870, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(1))>>1);
PHY_SetBBReg(priv, 0x860, BIT(6), (priv->pmib->dot11RFEntry.trsw_pape_C9 & BIT(0))>>0);
// PAPE2G_1
PHY_SetBBReg(priv, 0x870, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(1))>>1);
PHY_SetBBReg(priv, 0x860, BIT(10), (priv->pmib->dot11RFEntry.trsw_pape_CC & BIT(0))>>0);
// 5G LNA on
PHY_SetBBReg(priv, 0xb30, 0x00f00000, 0xa);
//fc_area
PHY_SetBBReg(priv, rOFDM1_CFOTracking, BIT(14) | BIT(13), 0x00);
//cck_enable
PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x1);
//TX BB gain shift
PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, 0x40000100);
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, 0x40000100);
// Reset IQC
PHY_SetBBReg(priv, 0xc94, 0xF0000000, 0);
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, 0xc9c, 0xF0000000, 0);
//BB/DP IQC
PHY_SetBBReg(priv, 0xb00, bMaskDWord, 0x01017038);
if (priv->pmib->dot11RFEntry.macPhyMode != DUALMAC_DUALPHY)
PHY_SetBBReg(priv, 0xb70, bMaskDWord, 0x01017038);
}
//Update RF
if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY)
curMaxRFPath = RF92CD_PATH_B;
else
curMaxRFPath = RF92CD_PATH_MAX;
for(eRFPath = RF92CD_PATH_A; eRFPath <curMaxRFPath; eRFPath++) {
if(priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) {
/*
* 5G
*/
priv->pshare->RegRF18[eRFPath] &= 0xffffff00;
priv->pshare->RegRF18[eRFPath] |= (BIT(16)|BIT(8)|0x24); //set channel 36
PHY_SetRFReg(priv,eRFPath, rRfChannel,bMask20Bits, priv->pshare->RegRF18[eRFPath]);
delay_ms(1);
// LDO_DIV
priv->pshare->RegRF28[eRFPath] = RTL_SET_MASK(priv->pshare->RegRF28[eRFPath],BIT(7)|BIT(6),1,6);
//PHY_SetRFReg(priv,eRFPath, 0x28, BIT(7)|BIT(6), 0x01);
PHY_SetRFReg(priv,eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]);
delay_ms(30);
} else {
/*
* 2.4G
*/
priv->pshare->RegRF18[eRFPath] &= ~(BIT(16)|BIT(8)|0xFF);
priv->pshare->RegRF18[eRFPath] |= 1; //set channel 1.
PHY_SetRFReg(priv,eRFPath, rRfChannel,bMask20Bits, priv->pshare->RegRF18[eRFPath]);
delay_ms(1);
// LDO_DIV
priv->pshare->RegRF28[eRFPath] &= (~(BIT(7)|BIT(6)));
//PHY_SetRFReg(priv,eRFPath, 0x28, BIT(7)|BIT(6), 0x00);
PHY_SetRFReg(priv,eRFPath, 0x28, bMask20Bits, priv->pshare->RegRF28[eRFPath]);
delay_ms(30);
}
}
#ifdef CONFIG_RTL_92D_DMDP
if (priv->pmib->dot11RFEntry.macPhyMode == DUALMAC_DUALPHY) {
//Use antenna 0 & 1
PHY_SetBBReg(priv, rOFDM0_TRxPathEnable, bMaskByte0, 0x11);
PHY_SetBBReg(priv, rOFDM1_TRxPathEnable, bDWord, 0x1);
//disable ad/da clock1
if (!(DMDP_RTL_R8(0,SYS_FUNC_EN)&(FEN_BB_GLB_RST|FEN_BBRSTB))){
DMDP_RTL_W8(0, SYS_FUNC_EN, (DMDP_RTL_R8(0,SYS_FUNC_EN)|FEN_BB_GLB_RST|FEN_BBRSTB));
}
DMDP_PHY_SetBBReg(0, rFPGA0_AdDaClockEn, BIT(13)|BIT(12), 3);
} else
#endif
{
//Use antenna 0 & 1
PHY_SetBBReg(priv, rOFDM0_TRxPathEnable, bMaskByte0, 0x33);
PHY_SetBBReg(priv, rOFDM1_TRxPathEnable, bDWord, 0x3);
//disable ad/da clock1
PHY_SetBBReg(priv, rFPGA0_AdDaClockEn, BIT(13) | BIT(12), 0);
}
}
#if 0 //def CLIENT_MODE
void clnt_save_IQK_res(struct rtl8192cd_priv *priv)
{
priv->site_survey->bk_iqc[0] = PHY_QueryBBReg(priv,0xc80, bMaskDWord);
priv->site_survey->bk_iqc[1] = PHY_QueryBBReg(priv,0xc94, bMaskByte3);
priv->site_survey->bk_iqc[2] = PHY_QueryBBReg(priv,0xc4c, bMaskByte3);
priv->site_survey->bk_iqc[3] = PHY_QueryBBReg(priv,0xc88, bMaskDWord);
priv->site_survey->bk_iqc[4] = PHY_QueryBBReg(priv,0xc9c, bMaskByte3);
priv->site_survey->bk_iqc[5] = PHY_QueryBBReg(priv,0xc14, bMaskDWord);
priv->site_survey->bk_iqc[6] = PHY_QueryBBReg(priv,0xca0, bMaskByte3);
priv->site_survey->bk_iqc[7] = PHY_QueryBBReg(priv,0xc1c, bMaskDWord);
priv->site_survey->bk_iqc[8] = PHY_QueryBBReg(priv,0xc78, bMaskByte1);
priv->site_survey->bk_iqc[9] = PHY_QueryRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 1);
priv->site_survey->bk_iqc[10] = PHY_QueryRFReg(priv, RF92CD_PATH_B, 0x08, bMask20Bits, 1);
}
void clnt_load_IQK_res(struct rtl8192cd_priv *priv)
{
PHY_SetBBReg(priv,0xc80, bMaskDWord, priv->site_survey->bk_iqc[0]);
PHY_SetBBReg(priv,0xc94, bMaskByte3, priv->site_survey->bk_iqc[1]);
PHY_SetBBReg(priv,0xc4c, bMaskByte3, priv->site_survey->bk_iqc[2]);
PHY_SetBBReg(priv,0xc88, bMaskDWord, priv->site_survey->bk_iqc[3]);
PHY_SetBBReg(priv,0xc9c, bMaskByte3, priv->site_survey->bk_iqc[4]);
PHY_SetBBReg(priv,0xc14, bMaskDWord, priv->site_survey->bk_iqc[5]);
PHY_SetBBReg(priv,0xca0, bMaskByte3, priv->site_survey->bk_iqc[6]);
PHY_SetBBReg(priv,0xc1c, bMaskDWord, priv->site_survey->bk_iqc[7]);
PHY_SetBBReg(priv,0xc78, bMaskByte1, priv->site_survey->bk_iqc[8]);
PHY_SetRFReg(priv,RF92CD_PATH_A, 0x08, bMask20Bits, priv->site_survey->bk_iqc[9]);
PHY_SetRFReg(priv,RF92CD_PATH_B, 0x08, bMask20Bits, priv->site_survey->bk_iqc[10]);
}
#endif
#ifdef CONFIG_RTL_92D_DMDP
#if 0 //def CLIENT_MODE
void clnt_92D_2T_AGSwitch(struct rtl8192cd_priv * priv, int target)
{
unsigned int flags, i;
int rtStatus = 0;
unsigned char temp_0522, temp_0550, temp_0551, temp_0800;
unsigned char reg;
SAVE_INT_AND_CLI(flags);
/*
* Save MAC default value
*/
temp_0522 = RTL_R8(0x522);
temp_0550 = RTL_R8(0x550);
temp_0551 = RTL_R8(0x551);
/*
* MAC register setting
*/
RTL_W8(0x522, 0x3f);
RTL_W8(0x550, temp_0550& (~BIT(3)));
RTL_W8(0x551, temp_0551& (~BIT(3)));
// stop BB
PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0xf);
temp_0800 = PHY_QueryBBReg(priv, rFPGA0_RFMOD, 0x0f000000);
PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, 0);
// 5G_PAPE Select & external PA power on
PHY_SetBBReg(priv, 0x878, BIT(0), 0);
PHY_SetBBReg(priv, 0x878, BIT(16), 0);
PHY_SetBBReg(priv, 0x878, BIT(15), 0);
PHY_SetBBReg(priv, 0x878, BIT(31), 0);
// RSSI Table Select
PHY_SetBBReg(priv, 0xc78, BIT(7)|BIT(6), 0);
// fc_area
PHY_SetBBReg(priv, 0xd2c, BIT(14)|BIT(13), 0);
// cck_enable
PHY_SetBBReg(priv, rFPGA0_RFMOD, bCCKEn, 0x1);
// LDO_DIV
PHY_SetRFReg(priv, RF92CD_PATH_A, 0x28, BIT(7)|BIT(6), 0);
PHY_SetRFReg(priv, RF92CD_PATH_B, 0x28, BIT(7)|BIT(6), 0);
// MOD_AG // Set channel number
PHY_SetRFReg(priv, RF92CD_PATH_A, 0x18, BIT(16), 0);
PHY_SetRFReg(priv, RF92CD_PATH_A, 0x18, BIT(8), 0);
PHY_SetRFReg(priv, RF92CD_PATH_B, 0x18, BIT(16), 0);
PHY_SetRFReg(priv, RF92CD_PATH_B, 0x18, BIT(8), 0);
// CLOAD for path_A
PHY_SetRFReg(priv, RF92CD_PATH_A, 0xB, BIT(16)|BIT(15)|BIT(14), 0x7);
PHY_SetRFReg(priv, RF92CD_PATH_B, 0xB, BIT(16)|BIT(15)|BIT(14), 0x7);
// IMR
PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMask20Bits, 0x70000);
for (i=0;i<11;i++) {
PHY_SetRFReg(priv, RF92CD_PATH_A, (0x2f+i), bMask20Bits, IMR_SET_N[0][i]);
}
PHY_SetRFReg(priv, RF92CD_PATH_A, 0x00, bMask20Bits, 0x32fff);
// Enable BB
PHY_SetBBReg(priv, rFPGA0_RFMOD, 0x0f000000, temp_0800);
// IQK
PHY_SetBBReg(priv, 0xc80, bMaskDWord, 0x40000100);
PHY_SetBBReg(priv, 0xc94, bMaskByte3, 0);
PHY_SetBBReg(priv, 0xc4c, bMaskByte3, 0);
PHY_SetBBReg(priv, 0xc88, bMaskDWord, 0x40000100);
PHY_SetBBReg(priv, 0xc9c, bMaskByte3, 0);
PHY_SetBBReg(priv, 0xc14, bMaskDWord, 0x40000100);
PHY_SetBBReg(priv, 0xca0, bMaskByte3, 0);
PHY_SetBBReg(priv, 0xc1c, bMaskDWord, 0x40000100);
PHY_SetBBReg(priv, 0xc78, bMaskByte1, 0);
PHY_SetRFReg(priv, RF92CD_PATH_A, 0x08, bMask20Bits, 0x84000);
PHY_SetRFReg(priv, RF92CD_PATH_B, 0x08, bMask20Bits, 0x84000);
//Set related registers for BW config
PHY_SetBBReg(priv, rFPGA0_AnalogParameter4, 0x00f00000, 0x0);
/*
* Reload MAC default value
*/
RTL_W8(0x550, temp_0550);
RTL_W8(0x551, temp_0551);
RTL_W8(0x522, temp_0522);
RESTORE_INT(flags);
}
#endif
#endif //CONFIG_RTL_92D_DMDP
#endif // CONFIG_RTL_92D_SUPPORT
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192d_reg.h
Executable
+459
View File
@@ -0,0 +1,459 @@
/*
* Header file of 8192D register
*
* $Id: 8192d_reg.h,v 1.2 2010/05/07 14:29:47 victoryman Exp $
*
* Copyright (c) 2010 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192D_REG_H_
#define _8192D_REG_H_
//============================================================
// 8192D Regsiter offset definition
//============================================================
/*
* Project RTL8192d follows most of registers in Project RTL8192c
* This file includes additional registers for RTL8192d only
* Header file of RTL8192C registers should always be included
*/
/*
* Register 0x2C overlaps Project RTL8192c
*/
#define MAC_PHY_CTRL_T 0x2C // DMDP,SMSP,DMSP contrl
#define MAC_PHY_CTRL_MP 0xF8 // DMDP,SMSP,DMSP contrl
#define TXDMA_DBG 0x218 // TXDMA debug port
#define BIST_START_PAUSE 0x240
#define D_BIST_RDY 0x244
#define D_BIST_FAIL 0x248
#define D_BIST_RPT 0x24C // BIST Report
#define MAC_SEL 0x250 // Mac Select
#define RXDMA_DBG 0x28C // RXDMA debug port
#define BT_COEX_GLB_CTRL 0x2C0 // Bt-Coexistence Control
#define BT_COEX_TBL 0x2C4 // BT-Coexistence Arbiter Decision Table
#define BT_SSI 0x2D4 // Bt Signal Strength Index
#define BT_COEXT_CSR_ENH_INTF_CTRL 0x2D6 // Bt-Coexistence CSR Enhanced Interface Control
#define BT_ACT_STATS 0x2D8 // Bt Activity Statistics
#define BT_CMD_WLAN_RPT 0x2E0 // Bt Command Report from WLAN
#define BT_CMD_BT_RPT 0x2E1 // Bt Command Report from BT
#define BT_CMD_LATCH 0x2E2 // Bt Command Data Latched
#define EARLY_MODE_CTRL 0x4D0 // Early mode control
#define OTHERMAC_TBTTBK_CRTL 0x4D8 // Dis tbttbk othermac
#define PTCL_PKT_NUM 0x4E3 // Pkt nums in protocol function
#define PTCL_DBG 0x4E4 // Ptcl debug port
#define DROP_PKT_NUM 0x4E8 // Tx drop pkt num
#define LIFT_DROP_NUM 0x4EA // Lift drop pkt num
#define Pkt_Lifetime_CTRL 0x528 // Packet Lifetime Control
#define SCH_TXCMD_NOA 0x5CF // Tx_Cmd_Sel and Noa_Sel
#define SCH_DBG 0x5DC // Scheduler Debug Port
#define DMR 0x5F0 // Dual MAC Co-Existence
#define D_SCH_TXCMD 0x5F8 // TX_CMD Register
/*
* Register 0x6C0-6CF overlaps Project RTL8192c
*/
#define WL_PRI_MASK 0x6C0 // WLAN Activity Priority Mask
#define BT_COEX_CTRL 0x6C4 // BT-Coexistence Control
#define MACID1 0x700 // MAC ID1 Register (Offset 0700h~0705h)
#define SW_AES_REG 0x750 // Sw Access Aes Engine Data in/Data out/Security key Register
#define SW_AES_CONF 0x760 // Sw Access Aes Engine configure
#define WLAN_ACT_MSK_CTRL 0x768
#define WMAC_DBG 0x77C // WMAC DBG
//----------------------------------------------------------------------------
// 8192D DUALMAC_DUALPHY special bits
//----------------------------------------------------------------------------
#define RSV_MAC0_CTRL 0x081 // bit-7 for mac0 enable
#define RSV_MAC1_CTRL 0x053 // bit-0 for mac1 enable
#define MAC0_EN BIT(7) // 1 for MAC0 enable
#define BAND_STAT BIT(1) // 0:5G; 1:2G
#define MAC1_EN BIT(0) // 1 for MAC1 enable
#define RSV_MAC0_FWCTRL 0x018 // bit-0 for MAC0_WINTINI_RDY
#define RSV_MAC1_FWCTRL 0x01a // bit-0 for MAC1_WINTINI_RDY
#define MAC0_WINTINI_RDY BIT(0) // 1: init ready
#define MAC1_WINTINI_RDY BIT(0) // 1: init ready
//----------------------------------------------------------------------------
// 8192D RF_CTRL bits (Offset 0x1F, 8 bits)
//----------------------------------------------------------------------------
#define FW_DL_INPROC BIT(5) // 1 for firmware download inprogress
//----------------------------------------------------------------------------
// 8192D MAC_PHY_CTRL bits (Offset 0x2C, 8 bits)
//----------------------------------------------------------------------------
#define VAUX_EN BIT(4) // 1 for the system supporting aux power
#define R_SINGLE_FUNC BIT(3) // 1 to force PCIE in single function mode
#define SUPER_MAC_EN BIT(2) // 1 to enable super mac mode
#define DUAL_PHY_EN BIT(1) // 1 to enable dual phy mode
#define DUAL_MAC_EN BIT(0) // 1 to enable dual mac mode
//----------------------------------------------------------------------------
// 8192D LEDCFG bits (Offset 0x4C-4F, 32 bits)
//----------------------------------------------------------------------------
#define LED2DIS_92D BIT(23) // LED2 Disabled for analog signal usage,
// 1: disable (input mode), 0:Enable (output mode).
#define LED2SV_92D BIT(19) // LED2 software value.
#define LED1DIS_92D BIT(15) // LED1 Disabled for analog signal usage,
// 1: disable (input mode), 0:Enable (output mode).
#define LED1SV_92D BIT(11) // LED1 software value.
#define LED0DIS_92D BIT(7) // LED0 Disabled for analog signal usage,
// 1: disable (input mode), 0:Enable (output mode).
#define LED0SV_92D BIT(3) // LED0 software value.
#define LED1CM_SHIFT_92D 16
//----------------------------------------------------------------------------
// 8192D BIST_START_PAUSE bits (Offset 0x240-243, 32 bits)
//----------------------------------------------------------------------------
#define BSP_PCIE_PDATASRAM_REAL BIT(30)
#define BSP_PCIE_PHDRSRAM0 BIT(29)
#define TXDMA_BSP_MAC1 BIT(28)
#define TXLLT_BSP_MAC1 BIT(27)
#define TXOQT_BSP_MAC1 BIT(26)
#define TXPKT_BSP_MAC1 BIT(25)
#define RXPKT_BSP_MAC1 BIT(24)
#define TXDBUF_BSP_MAC1 BIT(23)
#define TXFIFO_BSP_MAC1 BIT(22)
#define RXFIFO_BSP_MAC1 BIT(21)
#define WOL_BSP_MAC1 BIT(20)
#define KEY_BSP_MAC1 BIT(19)
#define RXBA_BSP_MAC1 BIT(18)
#define RC4_SBOX1_BSP_MAC1 BIT(17)
#define RC4_SBOX0_BSP_MAC1 BIT(16)
#define BSP_PCIE_PHDRSRAM1 BIT(15)
#define BSP_PCIE_RTYRAM_REAL BIT(14)
#define BSP_PCIE_RTYSOTRAM BIT(13)
#define TXDMA_BSP_MAC0 BIT(12)
#define TXLLT_BSP_MAC0 BIT(11)
#define TXOQT_BSP_MAC0 BIT(10)
#define TXPKT_BSP_MAC0 BIT(9)
#define RXPKT_BSP_MAC0 BIT(8)
#define TXDBUF_BSP_MAC0 BIT(7)
#define TXFIFO_BSP_MAC0 BIT(6)
#define RXFIFO_BSP_MAC0 BIT(5)
#define WOL_BSP_MAC0 BIT(4)
#define KEY_BSP_MAC0 BIT(3)
#define RXBA_BSP_MAC0 BIT(2)
#define RC4_SBOX1_BSP_MAC0 BIT(1)
#define RC4_SBOX0_BSP_MAC0 BIT(0)
//----------------------------------------------------------------------------
// 8192D D_BIST_RDY bits (Offset 0x244-247, 32 bits)
//----------------------------------------------------------------------------
#define BD_PCIE_PDATASRAM_REAL BIT(30)
#define BD_PCIE_PHDRSRAM0 BIT(29)
#define TXDMA_BD_MAC1 BIT(28)
#define TXLLT_BD_MAC1 BIT(27)
#define TXOQT_BD_MAC1 BIT(26)
#define TXPKT_BD_MAC1 BIT(25)
#define RXPKT_BD_MAC1 BIT(24)
#define TXDBUF_BD_MAC1 BIT(23)
#define TXFIFO_BD_MAC1 BIT(22)
#define RXFIFO_BD_MAC1 BIT(21)
#define WOL_BD_MAC1 BIT(20)
#define KEY_BD_MAC1 BIT(19)
#define RXBA_BD_MAC1 BIT(18)
#define RC4_SBOX1_BD_MAC1 BIT(17)
#define RC4_SBOX0_BD_MAC1 BIT(16)
#define BD_PCIE_PHDRSRAM1 BIT(15)
#define BD_PCIE_RTYRAM_REAL BIT(14)
#define BD_PCIE_RTYSOTRAM BIT(13)
#define TXDMA_BD_MAC0 BIT(12)
#define TXLLT_BD_MAC0 BIT(11)
#define TXOQT_BD_MAC0 BIT(10)
#define TXPKT_BD_MAC0 BIT(9)
#define RXPKT_BD_MAC0 BIT(8)
#define TXDBUF_BD_MAC0 BIT(7)
#define TXFIFO_BD_MAC0 BIT(6)
#define RXFIFO_BD_MAC0 BIT(5)
#define WOL_BD_MAC0 BIT(4)
#define KEY_BD_MAC0 BIT(3)
#define RXBA_BD_MAC0 BIT(2)
#define RC4_SBOX1_BD_MAC0 BIT(1)
#define RC4_SBOX0_BD_MAC0 BIT(0)
//----------------------------------------------------------------------------
// 8192D D_BIST_FAIL bits (Offset 0x248-24B, 32 bits)
//----------------------------------------------------------------------------
#define BF_PCIE_PDATASRAM_REAL BIT(30)
#define BF_PCIE_PHDRSRAM0 BIT(29)
#define TXDMA_BF_MAC1 BIT(28)
#define TXLLT_BF_MAC1 BIT(27)
#define TXOQT_BF_MAC1 BIT(26)
#define TXPKT_BF_MAC1 BIT(25)
#define RXPKT_BF_MAC1 BIT(24)
#define TXDBUF_BF_MAC1 BIT(23)
#define TXFIFO_BF_MAC1 BIT(22)
#define RXFIFO_BF_MAC1 BIT(21)
#define WOL_BF_MAC1 BIT(20)
#define KEY_BF_MAC1 BIT(19)
#define RXBA_BF_MAC1 BIT(18)
#define RC4_SBOX1_BF_MAC1 BIT(17)
#define RC4_SBOX0_BF_MAC1 BIT(16)
#define BF_PCIE_PHDRSRAM1 BIT(15)
#define BF_PCIE_RTYRAM_REAL BIT(14)
#define BF_PCIE_RTYSOTRAM BIT(13)
#define TXDMA_BF_MAC0 BIT(12)
#define TXLLT_BF_MAC0 BIT(11)
#define TXOQT_BF_MAC0 BIT(10)
#define TXPKT_BF_MAC0 BIT(9)
#define RXPKT_BF_MAC0 BIT(8)
#define TXDBUF_BF_MAC0 BIT(7)
#define TXFIFO_BF_MAC0 BIT(6)
#define RXFIFO_BF_MAC0 BIT(5)
#define WOL_BF_MAC0 BIT(4)
#define KEY_BF_MAC0 BIT(3)
#define RXBA_BF_MAC0 BIT(2)
#define RC4_SBOX1_BF_MAC0 BIT(1)
#define RC4_SBOX0_BF_MAC0 BIT(0)
//----------------------------------------------------------------------------
// 8192D D_BIST_RPT bits (Offset 0x24C-24F, 32 bits)
//----------------------------------------------------------------------------
#define D_MAC_BIST_FAIL BIT(31) // At leaset one mac BIST FAIL
#define D_USB_IRAM_FAIL BIT(30)
#define D_USB_RAM1_FAIL BIT(29)
#define D_USB_RAM2_FAIL BIT(28)
#define D_USB_PRAM_FAIL BIT(27)
#define D_USB_PROM_FAIL BIT(26)
#define D_USB_RXDMA_FAIL_MAC0 BIT(25)
#define D_USB_RXDMA_FAIL_MAC1 BIT(24)
#define D_PCIE_PD_BIST_FAIL BIT(20)
#define D_PCIE_PH0_BIST_FAIL BIT(19)
#define D_PCIE_PH1_BIST_FAIL BIT(18)
#define D_PCIE_RETRY_BIST_FAIL BIT(17)
#define D_PCIE_SOT_BIST_FAIL BIT(16)
#define D_MAC_BIST_RDY BIT(10)
#define D_USB_BIST_RDY BIT(9)
#define D_PCIE_BIST_RDY BIT(8)
#define D_MAC_BIST_START BIT(2)
#define D_USB_BIST_START BIT(1)
#define D_PCIE_BIST_START BIT(0)
//----------------------------------------------------------------------------
// 8192D MAC_SEL bits (Offset 0x250-253, 32 bits)
//----------------------------------------------------------------------------
#define SIC_LBK_MAC_SEL BIT(3)
#define MAC0_TXRPT_SEL_8051 BIT(2) // Mac0/1 tx report selection
#define MAC0_SEL_MACPHY BIT(1) // Mac0/1 phy seletion
#define R_MAC0_SEL_DBG BIT(0) // Mac0/1 debug port selection
//----------------------------------------------------------------------------
// 8192D BT_COEX_GLB_CTRL bits (Offset 0x2C0-2C3, 32 bits)
//----------------------------------------------------------------------------
#define ERR_CHK_TH_Shift 24 // In RTK 2wire mode, the interval of bt clock will be counted to check whether the communication functions well. This register indicates the check threshold.
#define ERR_CHK_TH_Mask 0x0FF
#define ARB_WIN_WL_Shift 16 // Arbitration window if WLAN device active first
#define ARB_WIN_WL_Mask 0x0FF
#define ARB_WIN_BT_Shift 8 // Arbitration window if bluetooth device active first
#define ARB_WIN_BT_Mask 0x0FF
#define CSR_2W BIT(7) // indicates whether the current operating mode is CSR 2-wire coexstence, which is only available when r_BT_MODE = 2'b10 and r_ENHBT = 1'b0.
#define ANT_SEL_Shift 5 // 2 bits indicates the antenna usage of the wireless and bluetooth device, bit[0] for WL device, bit[1] for BT device 0: use ant a; 1: use ant b
#define ANT_SEL_Mask 0x03
#define WL_BAND_Shift 3 // Indicating the operating band of the chip, bit[0] for a path, bit[1] for b path; 0: 2.4G; 1: 5G
#define WL_BAND_Mask 0x03
#define STATIS_BT_RST BIT(2) // Reset BT_ACT_STATISTICS Counters. Write ¡§1¡¨ pulse.
#define STATIS_BT_EN BIT(1) // bit is set, the BT_ACT_STATISTICS counters starts counting
#define ENHBT BIT(0) // Used with r_BT_MODE to select Enhanced BT mode
//----------------------------------------------------------------------------
// 8192D BT_SSI bits (Offset 0x2D4-2D5, 16 bits)
//----------------------------------------------------------------------------
#define BT_TSSI_Shift 8 // BT tx signal strength index
#define BT_TSSI_Mask 0x03F
#define BT_RSSI_Shift 0 // BT rx signal strength index
#define BT_RSSI_Mask 0x03F
//----------------------------------------------------------------------------
// 8192D BT_COEXT_CSR_ENH_INTF_CTRL bits (Offset 0x2D6-2D7, 16 bits)
//----------------------------------------------------------------------------
#define BT_TRX_DELAY_Shift 8 // When BT_PRI is high, if BT goes low from high, then BT will TX after BT_TX_DELAY time. WLAN can pause WLAN TX or RX after this delay to avoid impacting on BT. Unit: 8us
#define BT_TRX_DELAY_Mask 0x0F
#define BT_TRX_INIT_DETECT_Shift 4 // After BT_PRI asserting for BT_TRX_INIT_DETECT us, if BT_STAT is low, then BT will receive packets; otherwise, if BT goes high, BT will TX data. Unit 4us.
#define BT_TRX_INIT_DETECT_Mask 0x0F
#define BT_PRI_DETECT_TO_Shift 0 // After BT_PRI asserting, if BT_STAT is asserted within this TO duration, BT will initiate high priority activities; otherwise, if BT_STAT is not asserted within this duration, it would be low priority activities. Units 1us.
#define BT_PRI_DETECT_TO_Mask 0x0F
//----------------------------------------------------------------------------
// 8192D BT_ACT_STATS bits (Offset 0x2D8-2DF, 64 bits)
//----------------------------------------------------------------------------
#define STATS_BT_LO_RX_Shift 16 // Counters for BT low priority RX. It counts up when STATIS_BT_EN is set. This counter will reset when STTIS_BT_RST is written by 1 pulse. This counter cannot wrap around when overflow occurs. Under overflow, this counter is kept with 0xFFFF.
#define STATS_BT_LO_RX_Mask 0x0FFFF
#define STATS_BT_LO_TX_Shift 0 // Counters for BT low priority TX. It counts up when STATIS_BT_EN is set. This counter will reset when STATIS_BT_RST is written by 1 pulse. This counter cannot wrap around when overflow occurs. Under overflow, this counter is kept with 0xFFFF.
#define STATS_BT_LO_TX_Mask 0x0FFFF
#define STATS_BT_HI_RX_Shift 16 // Counters for BT high priority RX. It counts up when STATIS_BT_EN is set. This counter will reset when STATIS_BT_RST is written by 1 pulse. This counter cannot wrap around when overflow occurs. Under overflow, this counter is kept with 0xFFFF.
#define STATS_BT_HI_RX_Mask 0x0FFFF
#define STATS_BT_HI_TX_Shift 0 // Counters for BT high priority TX. It counts up when STATIS_BT_EN is set. This counter will reset when STATIS_BT_RST is written by 1 pulse. This counter cannot wrap around when overflow occurs. Under overflow, this counter is kept with 0xFFFF.
#define STATS_BT_HI_TX_Mask 0x0FFFF
//----------------------------------------------------------------------------
// 8192D BT_CMD_LATCH bits (Offset 0x2E2-2E3, 16 bits)
//----------------------------------------------------------------------------
#define BT_CMD_BT_STAT_Shift 8 // Latched data from BT_STAT after CMD pattern is matched.
#define BT_CMD_BT_STAT_Mask 0x0FF
#define BT_CMD_BT_PRI_Shift 0 // Latched data from BT_PRI after CMD pattern is matched.
#define BT_CMD_BT_PRI_Mask 0x0FF
//----------------------------------------------------------------------------
// 8192D EARLY_MODE_CTRL bits (Offset 0x4D0-4D3, 32 bits)
//----------------------------------------------------------------------------
#define SINGLE_AMPDU_EN BIT(31) // Single pkt will be tx as single ampdu if enabled
#define SINGLE_LEN_TH_Shift 8 // Early mode work on if (single ampdu > thd), default: 512B
#define SINGLE_LEN_TH_Mask 0x07FF
#define EARLY_MODE_EN_Shift 0 // Early mode enable for {BK, BE, VI, VO}
#define EARLY_MODE_EN_Mask 0x0F
//----------------------------------------------------------------------------
// 8192D OTHERMAC_TBTTBK_CRTL bits (Offset 0x4D8-4DB, 32 bits)
//----------------------------------------------------------------------------
#define DIS_TBTTBK_OTHERMAC BIT(0) // Ptcl gen cmd will not cross the othermac's tbtt if set 0
//----------------------------------------------------------------------------
// 8192D Pkt_Lifetime_CTRL bits (Offset 0x528-52A, 24 bits)
//----------------------------------------------------------------------------
#define EN_NAVEND_RST_TXOP BIT(17) // set this bit, TXOP will be reset while NAV end.
#define EN_FILTER_CCA BIT(16) // Enable CCA filter threshold
#define CCA_FILTER_THRS_Shift 8 // CCA filter threshold value
#define CCA_FILTER_THRS_Mask 0x0FF
#define EDCCA_THRS_Shift 0 // EDCCA threshold value
#define EDCCA_THRS_Mask 0x0FF
//----------------------------------------------------------------------------
// 8192D SCH_TXCMD_NOA bits (Offset 0x5CF, 8 bits)
//----------------------------------------------------------------------------
#define NOA_SEL BIT(4) // Noa1 and noa2 parameter select
#define SCH_TXCMD_SEL_Shift 0 // Select to read which dword of tx_cmd
#define SCH_TXCMD_SEL_Mask 0x0F
//----------------------------------------------------------------------------
// 8192D DMR bits (Offset 0x5F0-5F1, 16 bits)
//----------------------------------------------------------------------------
#define DMR_R_DIS_TXOVER_TBTT_OTHERMAC BIT(8) //set 1, the packet can¡¦t be sent out whose pkt and nav time will be over the tbtt of the other mac
#define DMR_R_BLOCK_BY_SETBCN BIT(7) // tx backoff reset at tbtt of the other MAC in both DMDP and DMSP mode to prevent bcn tx blocked by the tx of the other mac
#define DMR_R_BLOCK_BY_TXPTCLACT BIT(6) // tx blocked by txptcl_active of the other MAC in DMSP mode to protect the whole tx procedure including rx response
#define DMR_R_BLOCK_BY_TXNAV BIT(5) // 1 to enable the co-existence mechanism for blocking Tx to protect rx response and NAV by TXNAV of another MAC in both DMDP and DMSP modes.
#define DMR_R_BLOCK_BY_TXON BIT(4) // 1 to enable the co-existence mechanism for blocking Tx by another MAC Tx in both DMDP and DMSP modes.
#define DMR_R_BLOCK_BY_RXNAV BIT(3) // 1 to enable the co-existence mechanism for blocking Tx to protect tx response and txop by RXNAV of another MAC in both DMDP and DMSP modes.
#define DMR_R_BLOCK_BY_EDCCA BIT(2) // 1 to enable the co-existence mechanism for blocking Tx by EDCCA of another MAC in DMDP mode.
#define DMR_R_BLOCK_BY_RXON BIT(1) // 1 to enable the co-existence mechanism for blocking Tx by another MAC Rx in DMDP mode
#define DMR_R_INTFR_COEXIST_EN BIT(0) // 1 to enable dual MAC co-existence mechanism for avoiding RF interference in DMDP mode.
//----------------------------------------------------------------------------
// 8192D WL_PRI_MASK bits (Offset 0x6C0-6C3, 32 bits)
//----------------------------------------------------------------------------
#define PRI_MASK_WAITRESP BIT(28) // Priority Mask for RX Response Packet
#define PRI_MASK_RXOFDM BIT(27) // Priority Mask for RX OFDM
#define PRI_MASK_RXCCK BIT(26) // Priority Mask for RX CCK
#define PRI_MASK_TXAC_Shift 19 // Priority Mask for Tx Queue
#define PRI_MASK_TXAC_Mask 0x07F
#define PRI_MASK_NAV_Shift 11 // Priority Mask for TX NAV
#define PRI_MASK_NAV_Mask 0x0FF
#define PRI_MASK_TXCCK BIT(10) // Priority Mask for TX CCK
#define PRI_MASK_TXOFDM BIT(9) // Priority Mask for TX OFDM
#define PRI_MASK_RTY BIT(8) // Priority Mask for Tx Retry Packet
#define PRI_MASK_NUM_Shift 4 // Priority Mask for Tx packet number
#define PRI_MASK_NUM_Mask 0x0F
#define PRI_MASK_NEAR_TBTT BIT(2) // Priority Mask for near tbtt
#define PRI_MASK_TX_RESP BIT(1) // Priority Mask for Tx Response Packet
#define PRI_MASK_RX_RESP BIT(0) // Priority Mask for RX Response Packet
//----------------------------------------------------------------------------
// 8192D BT_COEX_CTRL bits (Offset 0x6C4-6C7, 32 bits)
//----------------------------------------------------------------------------
#define PROTECT_RX_RSP BIT(11) // When wlan tx packets, this bit decides whether WLAN_ACT to BT device will overprotect wlan active not be interfered until rx response frame finish.
#define WLRX_TER_BY_CTL BIT(10) // When wlan receive a control packet without fit address, whether the signal indicating wlan rx can be terminated as soon as the address check finish is not only controlled by r_WLRX_TER_BY_AD, but also should be refered to this bit.
#define WLRX_TER_BY_AD BIT(9) // When wlan receive the packet without fit address, the signal indicating wlan rx can be terminated as soon as the address check finish. This feature can be enabled by this bit.
#define D_OOB BIT(8) // indicates the BT is out of the band of WLAN device. It's available only when r_BT_MODE is not the 2wire mode
#define WL_CHNNL_Shift 2 // WLAN channel information only for 2.4G band
#define WL_CHNNL_Mask 0x03F
#define RX_ISO_OK BIT(1) // Isolation check result if OOB is true when WLAN is RX. 1: pass; 0: fail
#define TX_ISO_OK BIT(0) // Isolation check result if OOB is true when WLAN is TX. 1: pass; 0: fail
//----------------------------------------------------------------------------
// 8192D SW_AES_CONF bits (Offset 0x760, 8 bits)
//----------------------------------------------------------------------------
#define SET_SWAES_REG BIT(7) // Set software aes engine request,to start aes engine calculation
#define CLR_SWAES_REQ BIT(6) // Clear software aes engine request
#define R_WMAC_SWAES_WE BIT(3) // Write enable of register ro_WMAC_SWAES_RD
#define R_WMAC_SWAES_SEL BIT(0) // 1,the content of register 0750-075F used to be aes engine data in or data out; 0, the content of register 0750-075F uesed to be aes engine security key
//----------------------------------------------------------------------------
// 8192D WLAN_ACT_MSK_CTRL bits (Offset 0x768-76E, 56 bits)
//----------------------------------------------------------------------------
#define GNTALL_WL_MASK BIT(19) // bit indicates whether to grant all devices or bt device only when WLAN_ACT Mask active.
#define WL_ACT_MASK_Enable BIT(17) // Enable WLAN_ACT Mask Function
//XXX
#define WACTMSK_RX_RESP_ON_DUR_Shift 7
#define WACTMSK_RX_RESP_ON_DUR_Mask 0x03
#define WACTMSK_TX_DATA_OFF_DUR_Shift 24
#define WACTMSK_TX_DATA_OFF_DUR_Mask 0x0FF
#define WACTMSK_TX_DATA_ON_DUR_Shift 16
#define WACTMSK_TX_DATA_ON_DUR_Mask 0x0FF
#define WACTMSK_TX_RESP_OFF_DUR_Shift 8
#define WACTMSK_TX_RESP_OFF_DUR_Mask 0x0FF
#define WACTMSK_TX_RESP_ON_DUR_Shift 0
#define WACTMSK_TX_RESP_ON_DUR_Mask 0x0FF
#if defined(CONFIG_RTL_92D_SUPPORT) && defined(EN_EFUSE)
#define EEPROM_MAC0_MACADDRESS 0x55 // MAC-0 MAC Address
#define EEPROM_MAC1_MACADDRESS 0x5B // MAC-1 MAC Address
#define EEPROM_2G_TxPowerCCK 0x61 // 2.4G CCK Tx Power base
#define EEPROM_2G_TxPowerHT40_1S 0x67 // 2.4G HT40 Tx Power base
#define EEPROM_2G_TxPowerHT40_2SDiff 0x6D // 2.4G HT40 Tx Power diff
#define EEPROM_2G_TxPowerHT20Diff 0x70 // 2.4G HT20 Tx Power diff
#define EEPROM_2G_TxPowerOFDMDiff 0x73 // 2.4G OFDM Tx Power diff
#define EEPROM_5GL_TxPowerHT40_1S 0x7C // 5G Ch.36-44 HT40 Tx Power base
#define EEPROM_5GL_TxPowerHT40_2SDiff 0x82 // 5G Ch.36-44 HT40 Tx Power diff
#define EEPROM_5GL_TxPowerHT20Diff 0x85 // 5G Ch.36-44 HT20 Tx Power diff
#define EEPROM_5GL_TxPowerOFDMDiff 0x88 // 5G Ch.36-44 OFDM Tx Power diff
#define EEPROM_5GM_TxPowerHT40_1S 0x91 // 5G Ch.100-112 HT40 Tx Power base
#define EEPROM_5GM_TxPowerHT40_2SDiff 0x97 // 5G Ch.100-112 HT40 Tx Power diff
#define EEPROM_5GM_TxPowerHT20Diff 0x9A // 5G Ch.100-112 HT20 Tx Power diff
#define EEPROM_5GM_TxPowerOFDMDiff 0x9D // 5G Ch.100-112 OFDM Tx Power diff
#define EEPROM_5GH_TxPowerHT40_1S 0xA6 // 5G Ch.149-153 HT40 Tx Power base
#define EEPROM_5GH_TxPowerHT40_2SDiff 0xAC // 5G Ch.149-153 HT40 Tx Power diff
#define EEPROM_5GH_TxPowerHT20Diff 0xAF // 5G Ch.149-153 HT20 Tx Power diff
#define EEPROM_5GH_TxPowerOFDMDiff 0xB2 // 5G Ch.149-153 OFDM Tx Power diff
#define EEPROM_92D_IQK_DELTA 0xBC
#define EEPROM_92D_LCK_DELTA 0xBC
#define EEPROM_92D_XTAL_K 0xBD //[7:0]
#define EEPROM_92D_TSSI_A_5G 0xBE
#define EEPROM_92D_TSSI_B_5G 0xBF
#define EEPROM_92D_TSSI_AB_5G 0xC0
#define EEPROM_92D_THERMAL_METER 0xC3 //[4:0]
#define EEPROM_92D_TRSW_CTRL 0xC9
#define EEPROM_92D_PAPE_CTRL 0xCC
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8192e_reg.h
Executable
+537
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@@ -0,0 +1,537 @@
/*
* Header file of 8188E register
*
* $Id: 8188e_reg.h,v 1.1 2011/06/30 11:02:56 victoryman Exp $
*
* Copyright (c) 2011 Realtek Semiconductor Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _8192E_REG_H_
#define _8192E_REG_H_
//============================================================
// 8188E Regsiter offset definition
//============================================================
/*
* Project RTL8188E follows most of registers in Project RTL8192c
* This file includes additional registers for RTL8188E only
* Header file of RTL8192C registers should always be included
*/
//
// 1. System Configure Register. (Offset 0x000 - 0x0FFh)
//
#define REG_92E_BB_PAD_CTRL 0x64
#define REG_92E_HMEBOX_E0 0x88
#define REG_92E_HMEBOX_E1 0x8A
#define REG_92E_HMEBOX_E2 0x8C
#define REG_92E_HMEBOX_E3 0x8E
#define REG_92E_WLLPS_CTRL 0x90
#define REG_92E_RPWM2 0x9E
#define REG_92E_HIMR 0xB0
#define REG_92E_HISR 0xB4
#define REG_92E_HIMRE 0xB8
#define REG_92E_HISRE 0xBC
#define REG_92E_EFUSE_DATA1 0xCC
#define REG_92E_EFUSE_DATA0 0xCD
#define REG_92E_EPPR 0xCF
#define REG_92E_TQPNT1 0x218
#define REG_92E_TQPNT2 0x21C
#define REG_92E_TDECTRL1 0x228
#define REG_92E_WATCHDOG 0x35C
#define REG_92E_VOQ_IDX 0x310
#define REG_92E_VIQ_IDX 0x314
#define REG_92E_MGQ_DESA 0x318
#define REG_92E_VOQ_DESA 0x320
#define REG_92E_VIQ_DESA 0x328
#define REG_92E_BEQ_DESA 0x330
#define REG_92E_BKQ_DESA 0x338
#define REG_92E_PCIE_HRPWM 0x361
#define REG_92E_PCIE_CLK_RECOVER 0x362
#define REG_92E_PCIE_HCPWM 0x363
#define REG_92E_BEQ_IDX 0x364
#define REG_92E_BKQ_IDX 0x368
#define REG_92E_MGQ_IDX 0x36C
#define REG_92E_HI0Q_IDX 0x370
#define REG_92E_HI1Q_IDX 0x374
#define REG_92E_HI2Q_IDX 0x378
#define REG_92E_HI3Q_IDX 0x37C
#define REG_92E_PCIE_HRPWM2 0x380
#define REG_92E_PCIE_HCPWM2 0x382
#define REG_92E_HCI_PCIE_H2C_MSG 0x384
#define REG_92E_HCI_PCIE_C2H_MSG 0x388
#define REG_92E_RXQ_IDX 0x38C
#define REG_92E_HI4Q_IDX 0x390
#define REG_92E_HI5Q_IDX 0x394
#define REG_92E_HI6Q_IDX 0x398
#define REG_92E_HI7Q_IDX 0x39C
#define REG_92E_HQ_DES_NUM0 0x3A0
#define REG_92E_HQ_DES_NUM1 0x3A4
#define REG_92E_HQ_DES_NUM2 0x3A8
#define REG_92E_HQ_DES_NUM3 0x3AC
#define REG_92E_TSFT_CLRQ 0x3B0
#define REG_92E_ACQ_DES_NUM0 0x3B4
#define REG_92E_ACQ_DES_NUM1 0x3B8
#define REG_92E_ACQ_DES_NUM2 0x3BC
#define REG_92E_HI0Q_DESA 0x3C0
#define REG_92E_HI1Q_DESA 0x3C8
#define REG_92E_HI2Q_DESA 0x3D0
#define REG_92E_HI3Q_DESA 0x3D8
#define REG_92E_HI4Q_DESA 0x3E0
#define REG_92E_HI5Q_DESA 0x3E8
#define REG_92E_HI6Q_DESA 0x3F0
#define REG_92E_HI7Q_DESA 0x3F8
#define REG_92E_TXPKTBUF_BCNQ_BDNY1 0x457
#define REG_92E_MACID_NOLINK 0x484
#define REG_92E_MACID_PAUSE 0x48C
#define REG_92E_TXRPT_CTRL 0x4EC
#define REG_92E_TXRPT_TIM 0x4F0
#define REG_92E_TXRPT_STSSET 0x4F2
#define REG_92E_TXRPT_STSVLD 0x4F4
#define REG_92E_TXRPT_STSINF 0x4F8
#define REG_92E_MBSSID_CTRL 0x526
#define REG_92E_PKT_LIFETIME_CTRL 0x528
#define REG_92E_ATIMWND1 0x570
#define REG_92E_PRE_DL_BCN_ITV 0x58F
#define REG_92E_ATIMWND2 0x5A0
#define REG_92E_ATIMWND3 0x5A1
#define REG_92E_ATIMWND4 0x5A2
#define REG_92E_ATIMWND5 0x5A3
#define REG_92E_ATIMWND6 0x5A4
#define REG_92E_ATIMWND7 0x5A5
#define REG_92E_ATIMUGT 0x5A6
#define REG_92E_HIQ_NO_LMT_EN 0x5A7
#define REG_92E_DTIM_COUNT_ROOT 0x5A8
#define REG_92E_DTIM_COUNT_VAP1 0x5A9
#define REG_92E_DTIM_COUNT_VAP2 0x5AA
#define REG_92E_DTIM_COUNT_VAP3 0x5AB
#define REG_92E_DTIM_COUNT_VAP4 0x5AC
#define REG_92E_DTIM_COUNT_VAP5 0x5AD
#define REG_92E_DTIM_COUNT_VAP6 0x5AE
#define REG_92E_DTIM_COUNT_VAP7 0x5AF
#define REG_92E_DIS_ATIM 0x5B0
#define REG_92E_UPD_HGQMD 0x604
//----------------------------------------------------------------------------
// 8192E REG_92E_HIMR bits (Offset 0xB0-B3, 32 bits)
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// 8192E REG_92E_HISR bits (Offset 0xB4-B7, 32 bits)
//----------------------------------------------------------------------------
#define HIMR_92E_TXCCK BIT(30) // TXRPT interrupt when CCX bit of the packet is set
#define HIMR_92E_PSTIMEOUT BIT(29) // Power Save Time Out Interrupt
#define HIMR_92E_GTINT4 BIT(28) // When GTIMER4 expires, this bit is set to 1
#define HIMR_92E_GTINT3 BIT(27) // When GTIMER3 expires, this bit is set to 1
#define HIMR_92E_TBDER BIT(26) // Transmit Beacon0 Error
#define HIMR_92E_TBDOK BIT(25) // Transmit Beacon0 OK, ad hoc only
#define HIMR_92E_TSF_BIT32_TOGGLE BIT(24) // TSF Timer BIT32 toggle indication interrupt
#define HIMR_92E_BcnInt BIT(20) // Beacon DMA Interrupt 0
#define HIMR_92E_BDERR0 BIT(16) // Beacon Queue DMA OK0
#define HIMR_92E_HSISR_IND_ON_INT BIT(15) // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
#define HIMR_92E_BCNDMAINT_E BIT(14) // Beacon DMA Interrupt Extension for Win7
#define HIMR_92E_ATIMEND BIT(12) // CTWidnow End or ATIM Window End
#define HIMR_92E_HISR1_IND_INT BIT(11) // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)
#define HIMR_92E_C2HCMD BIT(10) // CPU to Host Command INT Status, Write 1 clear
#define HIMR_92E_CPWM2 BIT(9) // CPU power Mode exchange INT Status, Write 1 clear
#define HIMR_92E_CPWM BIT(8) // CPU power Mode exchange INT Status, Write 1 clear
#define HIMR_92E_HIGHDOK BIT(7) // High Queue DMA OK
#define HIMR_92E_MGNTDOK BIT(6) // Management Queue DMA OK
#define HIMR_92E_BKDOK BIT(5) // AC_BK DMA OK
#define HIMR_92E_BEDOK BIT(4) // AC_BE DMA OK
#define HIMR_92E_VIDOK BIT(3) // AC_VI DMA OK
#define HIMR_92E_VODOK BIT(2) // AC_VO DMA OK
#define HIMR_92E_RDU BIT(1) // Rx Descriptor Unavailable
#define HIMR_92E_ROK BIT(0) // Receive DMA OK
//----------------------------------------------------------------------------
// 8192E REG_92E_HIMRE bits (Offset 0xB8-BB, 32 bits)
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// 8192E REG_92E_HIMSE bits (Offset 0xBC-BF, 32 bits)
//----------------------------------------------------------------------------
#define HIMRE_92E_BCNDMAINT7 BIT(27) // Beacon DMA Interrupt 7
#define HIMRE_92E_BCNDMAINT6 BIT(26) // Beacon DMA Interrupt 6
#define HIMRE_92E_BCNDMAINT5 BIT(25) // Beacon DMA Interrupt 5
#define HIMRE_92E_BCNDMAINT4 BIT(24) // Beacon DMA Interrupt 4
#define HIMRE_92E_BCNDMAINT3 BIT(23) // Beacon DMA Interrupt 3
#define HIMRE_92E_BCNDMAINT2 BIT(22) // Beacon DMA Interrupt 2
#define HIMRE_92E_BCNDMAINT1 BIT(21) // Beacon DMA Interrupt 1
#define HIMRE_92E_BCNDOK7 BIT(20) // Beacon Queue DMA OK Interrup 7
#define HIMRE_92E_BCNDOK6 BIT(19) // Beacon Queue DMA OK Interrup 6
#define HIMRE_92E_BCNDOK5 BIT(18) // Beacon Queue DMA OK Interrup 5
#define HIMRE_92E_BCNDOK4 BIT(17) // Beacon Queue DMA OK Interrup 4
#define HIMRE_92E_BCNDOK3 BIT(16) // Beacon Queue DMA OK Interrup 3
#define HIMRE_92E_BCNDOK2 BIT(15) // Beacon Queue DMA OK Interrup 2
#define HIMRE_92E_BCNDOK1 BIT(14) // Beacon Queue DMA OK Interrup 1
#define HIMRE_92E_ATIMEND_E BIT(13) // ATIM Window End Extension for Win7
#define HIMRE_92E_TXERR BIT(11) // Tx Error Flag Interrupt Status, write 1 clear.
#define HIMRE_92E_RXERR BIT(10) // Rx Error Flag INT Status, Write 1 clear
#define HIMRE_92E_TXFOVW BIT(9) // Transmit FIFO Overflow
#define HIMRE_92E_RXFOVW BIT(8) // Receive FIFO Overflow
//----------------------------------------------------------------------------
// 8192E REG_92E_HQ_DES_NUM0 bits (Offset 0x3A0-3A3, 32 bits)
//----------------------------------------------------------------------------
#define ACQ_92E_H1Q_DESCS_MODE_8SEG BIT(31)
#define ACQ_92E_H1Q_DESC_NUM_MASK 0xfff
#define ACQ_92E_H1Q_DESC_NUM_SHIFT 16
#define ACQ_92E_H0Q_DESCS_MODE_8SEG BIT(15)
#define ACQ_92E_H0Q_DESC_NUM_MASK 0xfff
#define ACQ_92E_H0Q_DESC_NUM_SHIFT 0
//----------------------------------------------------------------------------
// 8192E REG_92E_HQ_DES_NUM1 bits (Offset 0x3A4-3A7, 32 bits)
//----------------------------------------------------------------------------
#define ACQ_92E_H3Q_DESCS_MODE_8SEG BIT(31)
#define ACQ_92E_H3Q_DESC_NUM_MASK 0xfff
#define ACQ_92E_H3Q_DESC_NUM_SHIFT 16
#define ACQ_92E_H2Q_DESCS_MODE_8SEG BIT(15)
#define ACQ_92E_H2Q_DESC_NUM_MASK 0xfff
#define ACQ_92E_H2Q_DESC_NUM_SHIFT 0
//----------------------------------------------------------------------------
// 8192E REG_92E_HQ_DES_NUM2 bits (Offset 0x3A8-3AB, 32 bits)
//----------------------------------------------------------------------------
#define ACQ_92E_H5Q_DESCS_MODE_8SEG BIT(31)
#define ACQ_92E_H5Q_DESC_NUM_MASK 0xfff
#define ACQ_92E_H5Q_DESC_NUM_SHIFT 16
#define ACQ_92E_H4Q_DESCS_MODE_8SEG BIT(15)
#define ACQ_92E_H4Q_DESC_NUM_MASK 0xfff
#define ACQ_92E_H4Q_DESC_NUM_SHIFT 0
//----------------------------------------------------------------------------
// 8192E REG_92E_HQ_DES_NUM3 bits (Offset 0x3AC-3AF, 32 bits)
//----------------------------------------------------------------------------
#define ACQ_92E_H7Q_DESCS_MODE_8SEG BIT(31)
#define ACQ_92E_H7Q_DESC_NUM_MASK 0xfff
#define ACQ_92E_H7Q_DESC_NUM_SHIFT 16
#define ACQ_92E_H6Q_DESCS_MODE_8SEG BIT(15)
#define ACQ_92E_H6Q_DESC_NUM_MASK 0xfff
#define ACQ_92E_H6Q_DESC_NUM_SHIFT 0
//----------------------------------------------------------------------------
// 8192E REG_92E_CLRQ bits (Offset 0x3B0-3B4, 32 bits)
//----------------------------------------------------------------------------
#define CLRQ_92E_ALL_IDX 0x3FFF3FFF
#define CLRQ_92E_HI7Q_HW_IDX BIT(29)
#define CLRQ_92E_HI6Q_HW_IDX BIT(28)
#define CLRQ_92E_HI5Q_HW_IDX BIT(27)
#define CLRQ_92E_HI4Q_HW_IDX BIT(26)
#define CLRQ_92E_HI3Q_HW_IDX BIT(25)
#define CLRQ_92E_HI2Q_HW_IDX BIT(24)
#define CLRQ_92E_HI1Q_HW_IDX BIT(23)
#define CLRQ_92E_HI0Q_HW_IDX BIT(22)
#define CLRQ_92E_BKQ_HW_IDX BIT(21)
#define CLRQ_92E_BEQ_HW_IDX BIT(20)
#define CLRQ_92E_VIQ_HW_IDX BIT(19)
#define CLRQ_92E_VOQ_HW_IDX BIT(18)
#define CLRQ_92E_MGQ_HW_IDX BIT(17)
#define CLRQ_92E_RXQ_HW_IDX BIT(16)
#define CLRQ_92E_HI7Q_HOST_IDX BIT(13)
#define CLRQ_92E_HI6Q_HOST_IDX BIT(12)
#define CLRQ_92E_HI5Q_HOST_IDX BIT(11)
#define CLRQ_92E_HI4Q_HOST_IDX BIT(10)
#define CLRQ_92E_HI3Q_HOST_IDX BIT(9)
#define CLRQ_92E_HI2Q_HOST_IDX BIT(8)
#define CLRQ_92E_HI1Q_HOST_IDX BIT(7)
#define CLRQ_92E_HI0Q_HOST_IDX BIT(6)
#define CLRQ_92E_BKQ_HOST_IDX BIT(5)
#define CLRQ_92E_BEQ_HOST_IDX BIT(4)
#define CLRQ_92E_VIQ_HOST_IDX BIT(3)
#define CLRQ_92E_VOQ_HOST_IDX BIT(2)
#define CLRQ_92E_MGQ_HOST_IDX BIT(1)
#define CLRQ_92E_RXQ_HOST_IDX BIT(0)
//----------------------------------------------------------------------------
// 8192E REG_92E_ACQ_DES_NUM0 bits (Offset 0x3B4-3B7, 32 bits)
//----------------------------------------------------------------------------
#define ACQ_92E_VIQ_DESCS_MODE_8SEG BIT(31)
#define ACQ_92E_VIQ_DESC_NUM_MASK 0xfff
#define ACQ_92E_VIQ_DESC_NUM_SHIFT 16
#define ACQ_92E_VOQ_DESCS_MODE_8SEG BIT(15)
#define ACQ_92E_VOQ_DESC_NUM_MASK 0xfff
#define ACQ_92E_VOQ_DESC_NUM_SHIFT 0
//----------------------------------------------------------------------------
// 8192E REG_92E_ACQ_DES_NUM1 bits (Offset 0x3B8-3BB, 32 bits)
//----------------------------------------------------------------------------
#define ACQ_92E_BKQ_DESCS_MODE_8SEG BIT(31)
#define ACQ_92E_BKQ_DESC_NUM_MASK 0xfff
#define ACQ_92E_BKQ_DESC_NUM_SHIFT 16
#define ACQ_92E_BEQ_DESCS_MODE_8SEG BIT(15)
#define ACQ_92E_BEQ_DESC_NUM_MASK 0xfff
#define ACQ_92E_BEQ_DESC_NUM_SHIFT 0
//----------------------------------------------------------------------------
// 8192E REG_92E_ACQ_DES_NUM2 bits (Offset 0x3BC-3BF, 32 bits)
//----------------------------------------------------------------------------
#define ACQ_92E_RXQ_DESC_NUM_MASK 0xfff
#define ACQ_92E_RXQ_DESC_NUM_SHIFT 16
#define ACQ_92E_MGQ_DESCS_MODE_8SEG BIT(15)
#define ACQ_92E_MGQ_DESC_NUM_MASK 0xfff
#define ACQ_92E_MGQ_DESC_NUM_SHIFT 0
//----------------------------------------------------------------------------
// 8192E MBID_NUM bits (Offset 0x552, 8 bits)
//----------------------------------------------------------------------------
#define MBID_NUM_92E_EN_PREDOWN_BCN BIT(3)
//----------------------------------------------------------------------------
// 8192E REG_EFUSE_ACCESS (Offset 0xCF, 8 bits)
//----------------------------------------------------------------------------
#define EFUSE_ACCESS_ON_8192E 0x69
#define EFUSE_ACCESS_OFF_8192E 0x00
//====================================================
// EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES
//====================================================
#if defined(EN_EFUSE)
#define PATHA_OFFSET 0x10
#define PATHB_OFFSET 0x3A
#define PATHC_OFFSET 0x64
#define PATHD_OFFSET 0x8E
/*2.4 GHz, PATH A, 1T*/
#define EEPROM_2G_CCK1T_TxPower 0x0 // CCK Tx Power base
#define EEPROM_2G_HT401S_TxPower 0x6 // HT40 Tx Power base
#define EEPROM_2G_HT201S_TxPowerDiff 0xB // HT20 Tx Power Diff [7:4]
#define EEPROM_2G_OFDM1T_TxPowerDiff 0xB // OFDM Tx Power Diff [3:0]
/*2.4 GHz, PATH A, 2T*/
#define EEPROM_2G_HT402S_TxPowerDiff 0xC // HT40 Tx Power Diff [7:4]
#define EEPROM_2G_HT202S_TxPowerDiff 0xC // HT20 Tx Power Diff [3:0]
#define EEPROM_2G_OFDM2T_TxPowerDiff 0xD // OFDM Tx Power Diff [7:4]
#define EEPROM_2G_CCK2T_TxPowerDiff 0xD // CCK Tx Power Diff [3:0]
/*2.4 GHz, PATH A, 3T*/
#define EEPROM_2G_HT403S_TxPowerDiff 0xE // HT40 Tx Power Diff [7:4]
#define EEPROM_2G_HT203S_TxPowerDiff 0xE // HT40 Tx Power Diff [3:0]
#define EEPROM_2G_OFDM3T_TxPowerDiff 0xF // OFDM Tx Power Diff [7:4]
#define EEPROM_2G_CCK3T_TxPowerDiff 0xF // CCK Tx Power Diff [3:0]
/*2.4 GHz, PATH A, 4T*/
#define EEPROM_2G_HT404S_TxPowerDiff 0x10 // HT40 Tx Power Diff [7:4]
#define EEPROM_2G_HT204S_TxPowerDiff 0x10 // HT20 Tx Power Diff [0:3]
#define EEPROM_2G_OFDM4T_TxPowerDiff 0x11 // OFDM Tx Power Diff [7:4]
#define EEPROM_2G_CCK4T_TxPowerDiff 0x11 // CCK Tx Power Diff [3:0]
/*5 GHz, PATH A, 1T*/
#define EEPROM_5G_HT401S_TxPower 0x12 // HT40 Tx Power Base
#define EEPROM_5G_HT201S_TxPowerDiff 0x20 // HT20 Tx Power Diff [7:4]
#define EEPROM_5G_OFDM1T_TxPowerDiff 0x20 // OFDM Tx Power Diff [3:0]
#define EEPROM_5G_HT801S_TxPowerDiff 0x26 // HT80 Tx Power Diff [7:4]
#define EEPROM_5G_HT1601S_TxPowerDiff 0x26 // HT160 Tx Power Diff [3:0]
/*5 GHz, PATH A, 2T*/
#define EEPROM_5G_HT402S_TxPowerDiff 0x21 // HT40 Tx Power Diff [7:4]
#define EEPROM_5G_HT202S_TxPowerDiff 0x21 // HT20 Tx Power Diff [3:0]
#define EEPROM_5G_OFDM2T_TxPowerDiff 0x24 // OFDM Tx Power Diff [7:4]
#define EEPROM_5G_HT802S_TxPowerDiff 0x27 // HT80 Tx Power Diff [7:4]
/*5 GHz, PATH A, 3T*/
#define EEPROM_5G_OFDM3T_TxPowerDiff 0x24 // OFDM Tx Power Diff [3:0]
#define EEPROM_5G_HT403S_TxPowerDiff 0x22 // HT40 Tx Power Diff [7:4]
#define EEPROM_5G_HT203S_TxPowerDiff 0x22 // HT20 Tx Power Diff [3:0]
#define EEPROM_5G_HT803S_TxPowerDiff 0x28 // HT80 Tx Power Diff [7:4]
#define EEPROM_5G_HT1603S_TxPowerDiff 0x28 // HT160 Tx Power Diff [3:0]
/*5 GHz, PATH A, 4T*/
#define EEPROM_5G_HT404S_TxPowerDiff 0x23 // HT40 Tx Power Diff [7:4]
#define EEPROM_5G_HT204S_TxPowerDiff 0x23 // HT20 Tx Power Diff [3:0]
#define EEPROM_5G_OFDM4T_TxPowerDiff 0x25 // OFDM Tx Power Diff [3:0]
#define EEPROM_5G_HT804S_TxPowerDiff 0x29 // HT80 Tx Power Diff [7:4]
#define EEPROM_5G_HT1604S_TxPowerDiff 0x29 // HT160 Tx Power Diff [3:0]
#define EEPROM_92E_XTAL_K 0xB9 //Crystal Calibration [5:0]
#define EEPROM_92E_THERMAL_METER 0xBA //Thermal meter
#ifdef CONFIG_SDIO_HCI
#define EEPROM_92E_SDIOTYPE 0xD0
#define EEPROM_92E_MACADDRESS 0x11A
#else
#define EEPROM_92E_MACADDRESS 0xD0 // MAC Address
#endif
#endif
#if 0
#define PATHA_OFFSET 0x10
#define PATHB_OFFSET 0x3A
// 0x10 ~ 0x63 = TX power area.
#define EEPROM_TX_PWR_INX_8192E 0x0
#define EEPROM_ChannelPlan_8192E 0xB8
#define EEPROM_XTAL_8192E 0xB9
#define EEPROM_THERMAL_METER_8192E 0xBA
#define EEPROM_IQK_LCK_8192E 0xBB
#define EEPROM_2G_5G_PA_TYPE_8192E 0xBC
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF
#define EEPROM_RF_BOARD_OPTION_8192E 0xC1
#define EEPROM_RF_FEATURE_OPTION_8192E 0xC2
#define EEPROM_RF_BT_SETTING_8192E 0xC3
#define EEPROM_VERSION_8192E 0xC4
#define EEPROM_CustomID_8192E 0xC5
#define EEPROM_TX_BBSWING_2G_8192E 0xC6
#define EEPROM_TX_BBSWING_5G_8192E 0xC7
#define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8
#define EEPROM_RF_ANTENNA_OPT_8192E 0xC9
// RTL8192EE
#define EEPROM_MAC_ADDR_8192EE 0xD0
#define EEPROM_VID_8192EE 0xD6
#define EEPROM_DID_8192EE 0xD8
#define EEPROM_SVID_8192EE 0xDA
#define EEPROM_SMID_8192EE 0xDC
//RTL8192EU
#define EEPROM_MAC_ADDR_8192EU 0xD7
#define EEPROM_VID_8192EU 0xD0
#define EEPROM_PID_8192EU 0xD2
#define EEPROM_PA_TYPE_8192EU 0xBC
#define EEPROM_LNA_TYPE_2G_8192EU 0xBD
#define EEPROM_LNA_TYPE_5G_8192EU 0xBF
// RTL8192ES
#define EEPROM_MAC_ADDR_8192ES 0x11B
#endif
//-----------------------------------------------------
//
// RTL8192E SDIO Configuration
//
//-----------------------------------------------------
// I/O bus domain address mapping
#define SDIO_LOCAL_BASE 0x10250000
#define WLAN_IOREG_BASE 0x10260000
#define FIRMWARE_FIFO_BASE 0x10270000
#define TX_HIQ_BASE 0x10310000
#define TX_MIQ_BASE 0x10320000
#define TX_LOQ_BASE 0x10330000
#define TX_EXQ_BASE 0x10350000 // 92E Add
#define RX_RX0FF_BASE 0x10340000
// SDIO host local register space mapping.
#define SDIO_LOCAL_MSK 0x0FFF
#define WLAN_IOREG_MSK 0x7FFF
#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0]
#define WLAN_RX0FF_MSK 0x0003
#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID
#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13]
#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13]
#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13]
#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13]
#define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13] (False map) // 0b[16], 111b[15:13] (True map)(92E New)
#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13]
#define WLAN_IOREG_DEVICE_ID 8 // 1b[16]
// SDIO Tx Free Page Index (This order must match SDIO_REG_FREE_TXPG)
#define HI_QUEUE_IDX 0
#define MID_QUEUE_IDX 1
#define LOW_QUEUE_IDX 2
#define PUBLIC_QUEUE_IDX 3
#define EXTRA_QUEUE_IDX 4 // 92E New
#define SDIO_MAX_TX_QUEUE 4 // HIQ, MIQ, LOQ and EXQ
#define SDIO_MAX_RX_QUEUE 1
#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control
#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask
#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine
#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
#define SDIO_REG_OQT_FREE_SPACE 0x001E // OQT Free Space
#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page
#define SDIO_REG_HCPWM1 0x0025 // HCI Current Power Mode 1
#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2
#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion
#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1
#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2
#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control
#define SDIO_HIMR_DISABLED 0
// RTL8188E SDIO Host Interrupt Mask Register
#define SDIO_HIMR_RX_REQUEST_MSK BIT0
#define SDIO_HIMR_AVAL_MSK BIT1
#define SDIO_HIMR_TXERR_MSK BIT2
#define SDIO_HIMR_RXERR_MSK BIT3
#define SDIO_HIMR_TXFOVW_MSK BIT4
#define SDIO_HIMR_RXFOVW_MSK BIT5
#define SDIO_HIMR_TXBCNOK_MSK BIT6
#define SDIO_HIMR_TXBCNERR_MSK BIT7
#define SDIO_HIMR_BCNERLY_INT_MSK BIT16
#define SDIO_HIMR_C2HCMD_MSK BIT17
#define SDIO_HIMR_CPWM1_MSK BIT18
#define SDIO_HIMR_CPWM2_MSK BIT19
#define SDIO_HIMR_HSISR_IND_MSK BIT20
#define SDIO_HIMR_GTINT3_IND_MSK BIT21
#define SDIO_HIMR_GTINT4_IND_MSK BIT22
#define SDIO_HIMR_PSTIMEOUT_MSK BIT23
#define SDIO_HIMR_OCPINT_MSK BIT24
#define SDIO_HIMR_ATIMEND_MSK BIT25
#define SDIO_HIMR_ATIMEND_E_MSK BIT26
#define SDIO_HIMR_CTWEND_MSK BIT27
//RTL8188E SDIO Specific
#define SDIO_HIMR_MCU_ERR_MSK BIT28
#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29
// SDIO Host Interrupt Service Routine
#define SDIO_HISR_RX_REQUEST BIT0
#define SDIO_HISR_AVAL BIT1
#define SDIO_HISR_TXERR BIT2
#define SDIO_HISR_RXERR BIT3
#define SDIO_HISR_TXFOVW BIT4
#define SDIO_HISR_RXFOVW BIT5
#define SDIO_HISR_TXBCNOK BIT6
#define SDIO_HISR_TXBCNERR BIT7
#define SDIO_HISR_BCNERLY_INT BIT16
#define SDIO_HISR_C2HCMD BIT17
#define SDIO_HISR_CPWM1 BIT18
#define SDIO_HISR_CPWM2 BIT19
#define SDIO_HISR_HSISR_IND BIT20
#define SDIO_HISR_GTINT3_IND BIT21
#define SDIO_HISR_GTINT4_IND BIT22
#define SDIO_HISR_PSTIMEOUT BIT23
#define SDIO_HISR_OCPINT BIT24
#define SDIO_HISR_ATIMEND BIT25
#define SDIO_HISR_ATIMEND_E BIT26
#define SDIO_HISR_CTWEND BIT27
//RTL8188E SDIO Specific
#define SDIO_HISR_MCU_ERR BIT28
#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29
#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\
SDIO_HISR_RXERR |\
SDIO_HISR_TXFOVW |\
SDIO_HISR_RXFOVW |\
SDIO_HISR_TXBCNOK |\
SDIO_HISR_TXBCNERR |\
SDIO_HISR_C2HCMD |\
SDIO_HISR_CPWM1 |\
SDIO_HISR_CPWM2 |\
SDIO_HISR_HSISR_IND |\
SDIO_HISR_GTINT3_IND |\
SDIO_HISR_GTINT4_IND |\
SDIO_HISR_PSTIMEOUT |\
SDIO_HISR_OCPINT)
// SDIO HCI Suspend Control Register
#define HCI_RESUME_PWR_RDY BIT1
#define HCI_SUS_CTRL BIT0
// SDIO Tx FIFO related
#define SDIO_TX_FREE_PG_QUEUE 5 // The number of Tx FIFO free page
#define SDIO_TX_FIFO_PAGE_SZ 256
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8812_hw.c
Executable
+3500
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8812_reg.h
Executable
+1819
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8812_vht_gen.c
Executable
+617
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@@ -0,0 +1,617 @@
#include "8192cd.h"
#include "8192cd_cfg.h"
#include "8192cd_util.h"
#include "8192cd_headers.h"
#include "8812_vht_gen.h"
#ifdef RTK_AC_SUPPORT
void input_value_32(unsigned long *p, unsigned char start, unsigned char end, unsigned int value)
{
unsigned int bit_mask = 0;
if(value > 0) //only none-zero value needs to be assigned
{
if(start == end) //1-bit value
{
*p |= BIT(start);
}
else
{
unsigned char x = 0;
for(x = 0; x<=(end-start); x ++)
bit_mask |= BIT(x);
*p |= ((value&bit_mask) << start);
}
}
}
// 20/40/80, ShortGI, MCS Rate
const u2Byte VHT_MCS_DATA_RATE[3][2][30] =
{ { {13, 26, 39, 52, 78, 104, 117, 130, 156, 156,
26, 52, 78, 104, 156, 208, 234, 260, 312, 312,
39, 78, 117, 156, 234, 312, 351, 390, 468, 520}, // Long GI, 20MHz
{14, 29, 43, 58, 87, 116, 130, 144, 173, 173,
29, 58, 87, 116, 173, 231, 260, 289, 347, 347,
43, 86, 130, 173, 260, 347, 390, 433, 520, 578} }, // Short GI, 20MHz
{ {27, 54, 81, 108, 162, 216, 243, 270, 324, 360,
54, 108, 162, 216, 324, 432, 486, 540, 648, 720,
81, 162, 243, 342, 486, 648, 729, 810, 972, 1080}, // Long GI, 40MHz
{30, 60, 90, 120, 180, 240, 270, 300,360, 400,
60, 120, 180, 240, 360, 480, 540, 600, 720, 800,
90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200} }, // Short GI, 40MHz
{ {59, 117, 176, 234, 351, 468, 527, 585, 702, 780,
117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560,
176, 351, 527, 702, 1053, 1408, 1408, 1745, 2106, 2340}, // Long GI, 80MHz
{65, 130, 195, 260, 390, 520, 585, 650, 780, 867,
130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1733,
195, 390, 585, 780, 1170, 1560, 1560, 1950, 2340, 2600} } // Short GI, 80MHz
};
enum _VHT_SUPPORT_RATE_MAP_ {
SUPPORT_MCS_0_7_RATES = 0,
SUPPORT_MCS_0_8_RATES = 1,
SUPPORT_MCS_0_9_RATES = 2,
NOT_SUPPORT_VHT_RATES = 3
};
/*
* Description:
* This function will get the highest speed rate in input MCS set.
*
* /param Adapter Pionter to Adapter entity
* pMCSRateSet Pointer to MCS rate bitmap
* pMCSFilter Pointer to MCS rate filter
*
* /return Highest MCS rate included in pMCSRateSet and filtered by pMCSFilter.
*
*/
u1Byte
VHTGetHighestMCSRate(
struct rtl8192cd_priv *priv,
IN pu1Byte pVHTMCSRateSet
)
{
u1Byte i, j;
u1Byte bitMap;
u1Byte VHTMcsRate = 0;
for(i = 0; i < 2; i++)
{
if(pVHTMCSRateSet[i] != 0xff)
{
for(j = 0; j < 8; j += 2)
{
bitMap = (pVHTMCSRateSet[i] >> j) & 3;
if(bitMap != 3)
VHTMcsRate = _NSS1_MCS7_RATE_ + 5*j + i*40 + bitMap; //VHT rate indications begin from 0x90
}
}
}
return VHTMcsRate;
}
u2Byte
VHTMcsToDataRate(
struct rtl8192cd_priv *priv
)
{
BOOLEAN isShortGI = FALSE;
u2Byte VHTMcsRate;
#if 1
if(priv->pshare->rf_ft_var.lgirate == 0)
return 0;
isShortGI = 0;
if((priv->pmib->dot11acConfigEntry.dot11SupportedVHT & 0x30) != 0x30)
VHTMcsRate = _NSS3_MCS7_RATE_ +((priv->pmib->dot11acConfigEntry.dot11SupportedVHT>>4) &3);
else if((priv->pmib->dot11acConfigEntry.dot11SupportedVHT & 0x000c) != 0x0c)
VHTMcsRate = _NSS2_MCS7_RATE_ +((priv->pmib->dot11acConfigEntry.dot11SupportedVHT>>2) &3);
else
VHTMcsRate = _NSS1_MCS7_RATE_ +((priv->pmib->dot11acConfigEntry.dot11SupportedVHT) &3); ;
#else
switch(priv->pshare->CurrentChannelBW){
case HT_CHANNEL_WIDTH_20:
isShortGI = priv->pmib->dot11nConfigEntry.dot11nShortGIfor20M?1:0;
break;
case HT_CHANNEL_WIDTH_20_40:
isShortGI = priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M?1:0;
break;
case HT_CHANNEL_WIDTH_80:
isShortGI = priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M?1:0; // ??
break;
}
#endif
VHTMcsRate -=_NSS1_MCS0_RATE_;
if( ((VHTMcsRate>20)&&get_rf_mimo_mode(priv)==MIMO_2T2R)|| (priv->pshare->is_40m_bw > 2))
return 600;
else
return VHT_MCS_DATA_RATE[priv->pshare->is_40m_bw][isShortGI][(VHTMcsRate&0x3f)];
}
unsigned int filter_mcs_9(unsigned int supported_vht, int num_ss)
{
int tmp = 0;
//panic_printk(" +++ supported_vht = 0x%x \n", supported_vht);
for(tmp = 1; tmp <= num_ss; tmp++)
{
int bit_shift = ((tmp-1)*2);
if(tmp > 8)
break;
if((tmp==3) || (tmp==6)) //3SS & 6SS support 20M + MCS9
continue;
if(( supported_vht & (3 << bit_shift)) == (SUPPORT_MCS_0_9_RATES << bit_shift))
{
supported_vht &= ~(3 << bit_shift);
supported_vht |= (SUPPORT_MCS_0_8_RATES << bit_shift);
}
}
//panic_printk(" --- supported_vht = 0x%x \n", supported_vht);
return supported_vht;
}
#ifdef MCR_WIRELESS_EXTEND
void construct_vht_ie_mcr(struct rtl8192cd_priv *priv, unsigned char channel_center, struct stat_info *pstat)
{
struct vht_cap_elmt *vht_cap;
struct vht_oper_elmt *vht_oper;
unsigned int value;
unsigned char txbf_max_ant, txbf_sounding_dim;
unsigned int supported_vht = priv->pmib->dot11acConfigEntry.dot11SupportedVHT;
//// ===== VHT CAPABILITIES ELEMENT ===== /////
//VHT CAPABILITIES INFO field
priv->vht_cap_len = sizeof(struct vht_cap_elmt);
vht_cap = &priv->vht_cap_buf;
memset(vht_cap, 0, sizeof(struct vht_cap_elmt));
switch(get_rf_mimo_mode(priv)) {
case MIMO_1T1R:
supported_vht |= 0xfffe;
break;
case MIMO_3T3R:
case MIMO_4T4R:
supported_vht |= 0xffea;
break;
default: //2T2R
supported_vht |= 0xfffa;
break;
}
// TODO: MAX_MPDU_LENGTH_E in 11AC
if(priv->pmib->dot11nConfigEntry.dot11nAMSDURecvMax)
input_value_32(&vht_cap->vht_cap_info, MAX_MPDU_LENGTH_S, MAX_MPDU_LENGTH_E, (priv->pmib->dot11nConfigEntry.dot11nAMSDURecvMax & 0x3));
else
input_value_32(&vht_cap->vht_cap_info, MAX_MPDU_LENGTH_S, MAX_MPDU_LENGTH_E, 0);
//0 - not support 160/80+80; 1 - support 160; 2 - support 80+80
if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_160)
value = 1;
else
value = 0;
input_value_32(&vht_cap->vht_cap_info, CHL_WIDTH_S, CHL_WIDTH_E, value);
if((GET_CHIP_VER(priv) == VERSION_8814A) && (priv->pshare->is_40m_bw == HT_CHANNEL_WIDTH_AC_80))
input_value_32(&vht_cap->vht_cap_info, SHORT_GI80M_S, SHORT_GI80M_E, (priv->pmib->dot11nConfigEntry.dot11nShortGIfor40M ? 1 : 0));
input_value_32(&vht_cap->vht_cap_info, SHORT_GI160M_S, SHORT_GI160M_E, 0);
if( (priv->pmib->dot11nConfigEntry.dot11nLDPC&1)
#if defined(CONFIG_WLAN_HAL_8881A)
&& (GET_CHIP_VER(priv) != VERSION_8881A)
#endif
)
input_value_32(&vht_cap->vht_cap_info, RX_LDPC_S, RX_LDPC_E, 1);
else
input_value_32(&vht_cap->vht_cap_info, RX_LDPC_S, RX_LDPC_E, 0);
#if 1
if (priv->pmib->dot11nConfigEntry.dot11nSTBC)
{
if ((get_rf_mimo_mode(priv) == MIMO_2T2R) || (get_rf_mimo_mode(priv) == MIMO_3T3R)) //eric_8814
input_value_32(&vht_cap->vht_cap_info, TX_STBC_S, TX_STBC_E, 1);
input_value_32(&vht_cap->vht_cap_info, RX_STBC_S, RX_STBC_E, 1);
}
else
#endif
{
input_value_32(&vht_cap->vht_cap_info, TX_STBC_S, TX_STBC_E, 0);
input_value_32(&vht_cap->vht_cap_info, RX_STBC_S, RX_STBC_E, 0);
}
#ifdef BEAMFORMING_SUPPORT
if (priv->pmib->dot11RFEntry.txbf == 1) {
if(priv->pmib->dot11RFEntry.txbfer == 1)
input_value_32(&vht_cap->vht_cap_info, SU_BFER_S, SU_BFER_E, 1);
if(priv->pmib->dot11RFEntry.txbfee == 1)
input_value_32(&vht_cap->vht_cap_info, SU_BFEE_S, SU_BFEE_E, 1);
} else
#endif
{
input_value_32(&vht_cap->vht_cap_info, SU_BFER_S, SU_BFER_E, 0);
input_value_32(&vht_cap->vht_cap_info, SU_BFEE_S, SU_BFEE_E, 0);
}
#ifdef CONFIG_WLAN_HAL_8814AE
if(priv->pshare->rf_ft_var.bf_sup_val != 0){
input_value_32(&vht_cap->vht_cap_info, MAX_ANT_SUPP_S, MAX_ANT_SUPP_E, priv->pshare->rf_ft_var.bf_sup_val);
input_value_32(&vht_cap->vht_cap_info, SOUNDING_DIMENSIONS_S, SOUNDING_DIMENSIONS_E, priv->pshare->rf_ft_var.bf_sup_val);
}else
#endif
{
#ifdef CONFIG_WLAN_HAL_8814AE
if(GET_CHIP_VER(priv)==VERSION_8814A) {
if(get_rf_mimo_mode(priv) == MIMO_4T4R) {
txbf_max_ant = 3;
txbf_sounding_dim = 3;
} else if(get_rf_mimo_mode(priv) == MIMO_3T3R) {
txbf_max_ant = 2;
txbf_sounding_dim = 3;
} else if(get_rf_mimo_mode(priv) == MIMO_2T4R) {
txbf_max_ant = 2;
txbf_sounding_dim = 1;
} else if(get_rf_mimo_mode(priv) == MIMO_2T2R) {
txbf_max_ant = 2;
txbf_sounding_dim = 1;
} else {
txbf_max_ant = 1;
txbf_sounding_dim = 1;
}
input_value_32(&vht_cap->vht_cap_info, MAX_ANT_SUPP_S, MAX_ANT_SUPP_E, txbf_max_ant);
input_value_32(&vht_cap->vht_cap_info, SOUNDING_DIMENSIONS_S, SOUNDING_DIMENSIONS_E, txbf_sounding_dim);
}
else
#endif
{
input_value_32(&vht_cap->vht_cap_info, MAX_ANT_SUPP_S, MAX_ANT_SUPP_E, BEAMFORM_MAX_ANT_SUPP);
input_value_32(&vht_cap->vht_cap_info, SOUNDING_DIMENSIONS_S, SOUNDING_DIMENSIONS_E, BEAMFORM_SOUNDING_DIMENSIONS);
}
}
input_value_32(&vht_cap->vht_cap_info, MU_BFER_S, MU_BFER_E, 0);
input_value_32(&vht_cap->vht_cap_info, MU_BFEE_S, MU_BFEE_E, 0);
input_value_32(&vht_cap->vht_cap_info, TXOP_PS_S, TXOP_PS_E, 0);
input_value_32(&vht_cap->vht_cap_info, HTC_VHT_S, HTC_VHT_E, 1);
#ifdef MCR_WIRELESS_EXTEND
input_value_32(&vht_cap->vht_cap_info, MAX_RXAMPDU_FACTOR_S, MAX_RXAMPDU_FACTOR_E, priv->pshare->rf_ft_var.ampdu_den_vht);
#else
input_value_32(&vht_cap->vht_cap_info, MAX_RXAMPDU_FACTOR_S, MAX_RXAMPDU_FACTOR_E, 7);
#endif
input_value_32(&vht_cap->vht_cap_info, LINK_ADAPTION_S, LINK_ADAPTION_E, 0);
input_value_32(&vht_cap->vht_cap_info, RX_ANT_PC_S, RX_ANT_PC_E, 0);
input_value_32(&vht_cap->vht_cap_info, TX_ANT_PC_S, TX_ANT_PC_E, 0);
//printk("vht_cap->vht_cap_info 0x%08X ", vht_cap->vht_cap_info);
vht_cap->vht_cap_info = cpu_to_le32(vht_cap->vht_cap_info);
//printk("0x%08X\n", vht_cap->vht_cap_info);
#if defined(AC2G_256QAM) || defined(WLAN_HAL_8814AE)
if(is_ac2g(priv) && ((priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_20)||(GET_CHIP_VER(priv)==VERSION_8814A))) //if bw = 20M, not support MCS9
{
if(get_rf_mimo_mode(priv) == MIMO_1T1R)
{
supported_vht = 0xfffd;
}
else if(get_rf_mimo_mode(priv) == MIMO_2T2R)
{
supported_vht = 0xfff5;
}
else if(get_rf_mimo_mode(priv) == MIMO_3T3R || get_rf_mimo_mode(priv) == MIMO_4T4R)
{
supported_vht = 0xffd5;
}
else
supported_vht = 0xfff5; //2ss as default
}
#endif
if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_20)
{
// 1SS & 2SS do NOT support MCS9 in BW 20m
if(get_rf_mimo_mode(priv) == MIMO_1T1R)
supported_vht = filter_mcs_9(supported_vht, 1);
else if(get_rf_mimo_mode(priv) == MIMO_2T2R)
supported_vht = filter_mcs_9(supported_vht, 2);
}
if (GET_CHIP_VER(priv)==VERSION_8814A && get_rf_mimo_mode(priv) == MIMO_2T2R) {
if (pstat->IOTPeer == HT_IOT_PEER_REALTEK_8812) {
supported_vht = 0xfff5;
}
}
{
input_value_32(&vht_cap->vht_support_mcs[0], MCS_RX_MAP_S, MCS_RX_MAP_E, supported_vht);
value = (VHTMcsToDataRate(priv)+1)>>1;
input_value_32(&vht_cap->vht_support_mcs[0], MCS_RX_HIGHEST_RATE_S, MCS_RX_HIGHEST_RATE_E, value);
vht_cap->vht_support_mcs[0] = cpu_to_le32(vht_cap->vht_support_mcs[0]);
input_value_32(&vht_cap->vht_support_mcs[1], MCS_TX_MAP_S, MCS_TX_MAP_E, supported_vht);
value = (VHTMcsToDataRate(priv)+1)>>1;
input_value_32(&vht_cap->vht_support_mcs[1], MCS_TX_HIGHEST_RATE_S, MCS_TX_HIGHEST_RATE_E, value);
vht_cap->vht_support_mcs[1] = cpu_to_le32(vht_cap->vht_support_mcs[1]);
}
//// ===== VHT CAPABILITIES ELEMENT ===== /////
priv->vht_oper_len = sizeof(struct vht_oper_elmt);
vht_oper = &priv->vht_oper_buf;
memset(vht_oper, 0, sizeof(struct vht_oper_elmt));
if((priv->pshare->is_40m_bw == HT_CHANNEL_WIDTH_AC_80) || (GET_CHIP_VER(priv)==VERSION_8814A))
{
vht_oper->vht_oper_info[0] = (priv->pshare->is_40m_bw ==2) ? 1 : 0;
if(OPMODE & (WIFI_STATION_STATE))
vht_oper->vht_oper_info[0] = 1; //8812_client
if(priv->pshare->is_40m_bw ==2) {
int channel = priv->pmib->dot11RFEntry.dot11channel;
if (channel <= 48)
channel_center = 42;
else if (channel <= 64)
channel_center = 58;
else if (channel <= 112)
channel_center = 106;
else if (channel <= 128)
channel_center = 122;
else if (channel <= 144)
channel_center = 138;
else if (channel <= 161)
channel_center = 155;
else if (channel <= 177)
channel_center = 171;
}
vht_oper->vht_oper_info[1] = channel_center;
vht_oper->vht_oper_info[2] = 0;
}
if(get_rf_mimo_mode(priv) == MIMO_1T1R)
value = 0xfffc;
else if(get_rf_mimo_mode(priv) == MIMO_2T2R)
value = 0xfff0;
else if(get_rf_mimo_mode(priv) == MIMO_3T3R || get_rf_mimo_mode(priv) == MIMO_4T4R)
value = 0xffea;
else
value = 0xfff0; //2ss as default
vht_oper->vht_basic_msc = value;
vht_oper->vht_basic_msc = cpu_to_le16(vht_oper->vht_basic_msc);
}
#endif
void construct_vht_ie(struct rtl8192cd_priv *priv, unsigned char channel_center)
{
struct vht_cap_elmt *vht_cap;
struct vht_oper_elmt *vht_oper;
unsigned int value;
unsigned int supported_vht = priv->pmib->dot11acConfigEntry.dot11SupportedVHT;
//// ===== VHT CAPABILITIES ELEMENT ===== /////
//VHT CAPABILITIES INFO field
priv->vht_cap_len = sizeof(struct vht_cap_elmt);
vht_cap = &priv->vht_cap_buf;
memset(vht_cap, 0, sizeof(struct vht_cap_elmt));
switch(get_rf_mimo_mode(priv)) {
case MIMO_1T1R:
supported_vht |= 0xfffe;
break;
case MIMO_3T3R:
case MIMO_4T4R:
supported_vht |= 0xffea;
break;
default: //2T2R
supported_vht |= 0xfffa;
break;
}
// TODO: MAX_MPDU_LENGTH_E in 11AC
if(priv->pmib->dot11nConfigEntry.dot11nAMSDURecvMax)
input_value_32(&vht_cap->vht_cap_info, MAX_MPDU_LENGTH_S, MAX_MPDU_LENGTH_E, (priv->pmib->dot11nConfigEntry.dot11nAMSDURecvMax & 0x3));
else
input_value_32(&vht_cap->vht_cap_info, MAX_MPDU_LENGTH_S, MAX_MPDU_LENGTH_E, 0);
//0 - not support 160/80+80; 1 - support 160; 2 - support 80+80
if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_160)
value = 1;
else
value = 0;
input_value_32(&vht_cap->vht_cap_info, CHL_WIDTH_S, CHL_WIDTH_E, value);
if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_80)
input_value_32(&vht_cap->vht_cap_info, SHORT_GI80M_S, SHORT_GI80M_E, (priv->pmib->dot11nConfigEntry.dot11nShortGIfor80M ? 1 : 0));
input_value_32(&vht_cap->vht_cap_info, SHORT_GI160M_S, SHORT_GI160M_E, 0);
if( (priv->pmib->dot11nConfigEntry.dot11nLDPC&1) && (can_enable_rx_ldpc(priv)) )
input_value_32(&vht_cap->vht_cap_info, RX_LDPC_S, RX_LDPC_E, 1);
else
input_value_32(&vht_cap->vht_cap_info, RX_LDPC_S, RX_LDPC_E, 0);
#if 1
if (priv->pmib->dot11nConfigEntry.dot11nSTBC)
{
if ((get_rf_mimo_mode(priv) == MIMO_2T2R) || (get_rf_mimo_mode(priv) == MIMO_3T3R)) //eric_8814
input_value_32(&vht_cap->vht_cap_info, TX_STBC_S, TX_STBC_E, 1);
input_value_32(&vht_cap->vht_cap_info, RX_STBC_S, RX_STBC_E, 1);
}
else
#endif
{
input_value_32(&vht_cap->vht_cap_info, TX_STBC_S, TX_STBC_E, 0);
input_value_32(&vht_cap->vht_cap_info, RX_STBC_S, RX_STBC_E, 0);
}
#ifdef BEAMFORMING_SUPPORT
if (priv->pmib->dot11RFEntry.txbf == 1) {
if(priv->pmib->dot11RFEntry.txbfer == 1)
input_value_32(&vht_cap->vht_cap_info, SU_BFER_S, SU_BFER_E, 1);
if(priv->pmib->dot11RFEntry.txbfee == 1)
input_value_32(&vht_cap->vht_cap_info, SU_BFEE_S, SU_BFEE_E, 1);
} else
#endif
{
input_value_32(&vht_cap->vht_cap_info, SU_BFER_S, SU_BFER_E, 0);
input_value_32(&vht_cap->vht_cap_info, SU_BFEE_S, SU_BFEE_E, 0);
}
input_value_32(&vht_cap->vht_cap_info, MAX_ANT_SUPP_S, MAX_ANT_SUPP_E, BEAMFORM_SUPPORT_VALUE);
input_value_32(&vht_cap->vht_cap_info, SOUNDING_DIMENSIONS_S, SOUNDING_DIMENSIONS_E, BEAMFORM_SUPPORT_VALUE);
input_value_32(&vht_cap->vht_cap_info, MU_BFER_S, MU_BFER_E, 0);
input_value_32(&vht_cap->vht_cap_info, MU_BFEE_S, MU_BFEE_E, 0);
input_value_32(&vht_cap->vht_cap_info, TXOP_PS_S, TXOP_PS_E, 0);
input_value_32(&vht_cap->vht_cap_info, HTC_VHT_S, HTC_VHT_E, 1);
input_value_32(&vht_cap->vht_cap_info, MAX_RXAMPDU_FACTOR_S, MAX_RXAMPDU_FACTOR_E, 7);
input_value_32(&vht_cap->vht_cap_info, LINK_ADAPTION_S, LINK_ADAPTION_E, 0);
input_value_32(&vht_cap->vht_cap_info, RX_ANT_PC_S, RX_ANT_PC_E, 0);
input_value_32(&vht_cap->vht_cap_info, TX_ANT_PC_S, TX_ANT_PC_E, 0);
//printk("vht_cap->vht_cap_info 0x%08X ", vht_cap->vht_cap_info);
vht_cap->vht_cap_info = cpu_to_le32(vht_cap->vht_cap_info);
//printk("0x%08X\n", vht_cap->vht_cap_info);
#if defined(AC2G_256QAM) || defined(WLAN_HAL_8814AE)
if(is_ac2g(priv) && ((priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_20)||(GET_CHIP_VER(priv)==VERSION_8814A))) //if bw = 20M, not support MCS9
{
if(get_rf_mimo_mode(priv) == MIMO_1T1R)
{
supported_vht = 0xfffd;
}
else if(get_rf_mimo_mode(priv) == MIMO_2T2R)
{
supported_vht = 0xfff5;
}
else if(get_rf_mimo_mode(priv) == MIMO_3T3R || get_rf_mimo_mode(priv) == MIMO_4T4R)
{
supported_vht = 0xffd5;
}
else
supported_vht = 0xfff5; //2ss as default
}
#endif
if(priv->pshare->CurrentChannelBW == HT_CHANNEL_WIDTH_AC_20)
{
// 1SS & 2SS do NOT support MCS9 in BW 20m
if(get_rf_mimo_mode(priv) == MIMO_1T1R)
supported_vht = filter_mcs_9(supported_vht, 1);
else if(get_rf_mimo_mode(priv) == MIMO_2T2R)
supported_vht = filter_mcs_9(supported_vht, 2);
}
{
input_value_32(&vht_cap->vht_support_mcs[0], MCS_RX_MAP_S, MCS_RX_MAP_E, supported_vht);
value = (VHTMcsToDataRate(priv)+1)>>1;
input_value_32(&vht_cap->vht_support_mcs[0], MCS_RX_HIGHEST_RATE_S, MCS_RX_HIGHEST_RATE_E, value);
vht_cap->vht_support_mcs[0] = cpu_to_le32(vht_cap->vht_support_mcs[0]);
input_value_32(&vht_cap->vht_support_mcs[1], MCS_TX_MAP_S, MCS_TX_MAP_E, supported_vht);
value = (VHTMcsToDataRate(priv)+1)>>1;
input_value_32(&vht_cap->vht_support_mcs[1], MCS_TX_HIGHEST_RATE_S, MCS_TX_HIGHEST_RATE_E, value);
vht_cap->vht_support_mcs[1] = cpu_to_le32(vht_cap->vht_support_mcs[1]);
}
//// ===== VHT CAPABILITIES ELEMENT ===== /////
priv->vht_oper_len = sizeof(struct vht_oper_elmt);
vht_oper = &priv->vht_oper_buf;
memset(vht_oper, 0, sizeof(struct vht_oper_elmt));
if((priv->pshare->is_40m_bw == HT_CHANNEL_WIDTH_AC_80) || (GET_CHIP_VER(priv)==VERSION_8814A))
{
vht_oper->vht_oper_info[0] = (priv->pshare->is_40m_bw ==2) ? 1 : 0;
if(OPMODE & (WIFI_STATION_STATE))
vht_oper->vht_oper_info[0] = 1; //8812_client
if(priv->pshare->is_40m_bw ==2) {
int channel = priv->pmib->dot11RFEntry.dot11channel;
if (channel <= 48)
channel_center = 42;
else if (channel <= 64)
channel_center = 58;
else if (channel <= 112)
channel_center = 106;
else if (channel <= 128)
channel_center = 122;
else if (channel <= 144)
channel_center = 138;
else if (channel <= 161)
channel_center = 155;
else if (channel <= 177)
channel_center = 171;
}
vht_oper->vht_oper_info[1] = channel_center;
vht_oper->vht_oper_info[2] = 0;
}
if(get_rf_mimo_mode(priv) == MIMO_1T1R)
value = 0xfffc;
else if(get_rf_mimo_mode(priv) == MIMO_2T2R)
value = 0xfff0;
else if(get_rf_mimo_mode(priv) == MIMO_3T3R || get_rf_mimo_mode(priv) == MIMO_4T4R)
value = 0xffea;
else
value = 0xfff0; //2ss as default
vht_oper->vht_basic_msc = value;
vht_oper->vht_basic_msc = cpu_to_le16(vht_oper->vht_basic_msc);
}
#endif //CONFIG_RTL_8812_SUPPORT
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/8812_vht_gen.h
Executable
+105
View File
@@ -0,0 +1,105 @@
/*****************************************************************************
* Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved.
*
* Module: __INC_HAL8812REG_H
*
*
* Note: 1. Define Mac register address and corresponding bit mask map
*
*
* Export: Constants, macro, functions(API), global variables(None).
*
* Abbrev:
*
* History:
* Data Who Remark
*
*****************************************************************************/
#ifdef RTK_AC_SUPPORT
#ifdef CONFIG_WLAN_HAL_8814AE
#define BEAMFORM_SUPPORT_VALUE 3
#else
#define BEAMFORM_SUPPORT_VALUE 1
#endif
//=== VHT capability info field ===
#define MAX_MPDU_LENGTH_S 0
#define MAX_MPDU_LENGTH_E 1
#define CHL_WIDTH_S 2
#define CHL_WIDTH_E 3
#define RX_LDPC_S 4
#define RX_LDPC_E 4
#define SHORT_GI80M_S 5
#define SHORT_GI80M_E 5
#define SHORT_GI160M_S 6
#define SHORT_GI160M_E 6
#define TX_STBC_S 7
#define TX_STBC_E 7
#define RX_STBC_S 8
#define RX_STBC_E 10
#define SU_BFER_S 11
#define SU_BFER_E 11
#define SU_BFEE_S 12
#define SU_BFEE_E 12
#define MAX_ANT_SUPP_S 13
#define MAX_ANT_SUPP_E 15
#define SOUNDING_DIMENSIONS_S 16
#define SOUNDING_DIMENSIONS_E 18
#define MU_BFER_S 19
#define MU_BFER_E 19
#define MU_BFEE_S 20
#define MU_BFEE_E 20
#define TXOP_PS_S 21
#define TXOP_PS_E 21
#define HTC_VHT_S 22
#define HTC_VHT_E 22
#define MAX_RXAMPDU_FACTOR_S 23
#define MAX_RXAMPDU_FACTOR_E 25
#define LINK_ADAPTION_S 26
#define LINK_ADAPTION_E 27
#define RX_ANT_PC_S 28
#define RX_ANT_PC_E 28
#define TX_ANT_PC_S 29
#define TX_ANT_PC_E 29
//30 - 31 Reserved
//=== VHT supported mcs set field ===
#define MCS_RX_MAP_S 0
#define MCS_RX_MAP_E 15
#define MCS_RX_HIGHEST_RATE_S 16
#define MCS_RX_HIGHEST_RATE_E 28
#define MCS_TX_MAP_S 0 //32-32
#define MCS_TX_MAP_E 15 //47-32
#define MCS_TX_HIGHEST_RATE_S 16 //48-32
#define MCS_TX_HIGHEST_RATE_E 28 //60-32
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Beamforming.c
Executable
+2210
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Beamforming.h
Executable
+128
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@@ -0,0 +1,128 @@
#ifdef BEAMFORMING_SUPPORT
#define TxBF_Nr(a,b) ((a>b) ? (b) : (a))
u1Byte
Beamforming_GetHTNDPTxRate(
struct rtl8192cd_priv *priv,
u1Byte CompSteeringNumofBFer
);
u1Byte
Beamforming_GetVHTNDPTxRate(
struct rtl8192cd_priv *priv,
u1Byte CompSteeringNumofBFer
);
VOID
Beamforming_GidPAid(
struct rtl8192cd_priv *priv,
struct stat_info *pstat
);
enum _BEAMFORMING_CAP
Beamforming_GetEntryBeamCapByMacId(
struct rtl8192cd_priv *priv,
IN u1Byte MacId
);
BOOLEAN
Beamforming_InitEntry(
struct rtl8192cd_priv *priv,
struct stat_info *pSTA,
pu1Byte Idx
);
BOOLEAN
Beamforming_DeInitEntry(
struct rtl8192cd_priv *priv,
pu1Byte RA
);
VOID
Beamforming_Notify(
struct rtl8192cd_priv *priv
);
VOID
Beamforming_Enter(
struct rtl8192cd_priv *priv,
struct stat_info *pstat
);
VOID
Beamforming_TimerCallback(
struct rtl8192cd_priv *priv
);
VOID
Beamforming_AutoTest(
struct rtl8192cd_priv *priv,
u1Byte Idx,
struct _RT_BEAMFORMING_ENTRY *pBeamformEntry
);
VOID
Beamforming_End(
struct rtl8192cd_priv *priv,
BOOLEAN Status
);
VOID
Beamforming_Leave(
struct rtl8192cd_priv *priv,
pu1Byte RA
);
VOID
Beamforming_Release(
struct rtl8192cd_priv *priv
);
BEAMFORMING_CAP
Beamforming_GetBeamCap(
IN PRT_BEAMFORMING_INFO pBeamInfo
);
VOID
Beamforming_Init(
struct rtl8192cd_priv *priv
);
VOID
Beamforming_SetTxBFen(
struct rtl8192cd_priv *priv,
u1Byte MacId,
BOOLEAN bTxBF
);
PRT_BEAMFORMING_ENTRY
Beamforming_GetEntryByMacId(
struct rtl8192cd_priv *priv,
u1Byte MacId,
pu1Byte Idx
);
PRT_BEAMFORMING_ENTRY
Beamforming_GetFreeBFeeEntry(
struct rtl8192cd_priv *priv,
pu1Byte Idx,
pu1Byte RA
);
PRT_BEAMFORMER_ENTRY
Beamforming_GetFreeBFerEntry(
struct rtl8192cd_priv *priv,
OUT pu1Byte Idx,
pu1Byte RA
);
VOID
Beamforming_GetNDPAFrame(
struct rtl8192cd_priv *priv,
pu1Byte pNDPAFrame
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Config.in
Executable
+31
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@@ -0,0 +1,31 @@
#
# Wireless LAN device configuration
#
tristate ' RTL8192C/D 802.11b/g/n support' CONFIG_RTL8192CD
if [ "$CONFIG_RTL8192CD" != "n" ]; then
bool ' Private skb buffer management' CONFIG_RTL8190_PRIV_SKB
bool ' WAPI support' CONFIG_RTL_WAPI_SUPPORT
if [ "$CONFIG_RTL_WAPI_SUPPORT" = "y" ]; then
bool ' support local AS' CONFIG_RTL_WAPI_LOCAL_AS_SUPPORT
#bool ' enable WAPI module' CONFIG_RTL_WAPI_MODULE_SUPPORT
#bool ' dynamic IRAM mapping for WAPI' CONFIG_RTL_DYNAMIC_IRAM_MAPPING_FOR_WAPI
fi
bool ' Client Mode support' CONFIG_RTL_CLIENT_MODE_SUPPORT
if [ "$CONFIG_RTL_CLIENT_MODE_SUPPORT" = "y" ]; then
bool ' Repeater Mode support' CONFIG_RTL_REPEATER_MODE_SUPPORT
fi
bool ' Mesh Mode support' CONFIG_MESH_ENABLE
if [ "$CONFIG_MESH_ENABLE" = "y" ]; then
dep_bool ' Enable Mesh NMS' CONFIG_NMS $CONFIG_MESH_ENABLE
# bool 'Test Package(netperf, test_traffic ...)' CONFIG_TEST_PKG
# bool 'Enable 11s Test Mode' CONFIG_11S_TEST_MODE
fi
bool ' WDS Support' CONFIG_RTL_WDS_SUPPORT
bool ' Virtual AP Support' CONFIG_RTL_VAP_SUPPORT
bool ' Efuse Support' CONFIG_ENABLE_EFUSE
bool ' Config File support' CONFIG_RTL_COMAPI_CFGFILE
dep_bool ' Wireless Tools v29 support' CONFIG_RTL_COMAPI_WLTOOLS $CONFIG_WIRELESS_EXT_V18
fi
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/EdcaTurboCheck.c
Executable
+916
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@@ -0,0 +1,916 @@
#include "./8192cd_cfg.h"
#include "./8192cd.h"
#include "./8192cd_util.h"
void EdcaParaInit(
struct rtl8192cd_priv *priv
)
{
int mode=priv->pmib->dot11BssType.net_work_type;
static unsigned int slot_time, sifs_time;
struct ParaRecord EDCA[4];
memset(EDCA, 0, 4*sizeof(struct ParaRecord));
sifs_time = 10;
slot_time = 20;
if (mode & (WIRELESS_11N))
sifs_time = 16;
if (mode & (WIRELESS_11N| WIRELESS_11G|WIRELESS_11A))
slot_time = 9;
#ifdef RTK_AC_SUPPORT //for 11ac logo, edit aifs time for cca test cases
if(AC_SIGMA_MODE != AC_SIGMA_NONE)
sifs_time = 10;
#endif
#if(defined(RTL_MANUAL_EDCA))
if( priv->pmib->dot11QosEntry.ManualEDCA ) {
if( OPMODE & WIFI_AP_STATE )
memcpy(EDCA, priv->pmib->dot11QosEntry.AP_manualEDCA, 4*sizeof(struct ParaRecord));
else
memcpy(EDCA, priv->pmib->dot11QosEntry.STA_manualEDCA, 4*sizeof(struct ParaRecord));
#ifdef WIFI_WMM
if (QOS_ENABLE)
RTL_W32(0x504, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
else
#endif
RTL_W32(0x504, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
}else
#endif //RTL_MANUAL_EDCA
{
if(OPMODE & WIFI_AP_STATE)
{
memcpy(EDCA, rtl_ap_EDCA, 2*sizeof(struct ParaRecord));
if(mode & (WIRELESS_11A|WIRELESS_11G|WIRELESS_11N))
memcpy(&EDCA[VI], &rtl_ap_EDCA[VI_AG], 2*sizeof(struct ParaRecord));
else
memcpy(&EDCA[VI], &rtl_ap_EDCA[VI], 2*sizeof(struct ParaRecord));
}
else
{
memcpy(EDCA, rtl_sta_EDCA, 2*sizeof(struct ParaRecord));
if(mode & (WIRELESS_11A|WIRELESS_11G|WIRELESS_11N))
memcpy(&EDCA[VI], &rtl_sta_EDCA[VI_AG], 2*sizeof(struct ParaRecord));
else
memcpy(&EDCA[VI], &rtl_sta_EDCA[VI], 2*sizeof(struct ParaRecord));
}
#ifdef WIFI_WMM
if (QOS_ENABLE)
RTL_W32(0x504, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
else
#endif
RTL_W32(0x504, (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
}
RTL_W32(0x500, (EDCA[VO].TXOPlimit<< 16) | (EDCA[VO].ECWmax<< 12) | (EDCA[VO].ECWmin<< 8) | (sifs_time + EDCA[VO].AIFSN* slot_time));
RTL_W32(0x508, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[BE].AIFSN* slot_time));
RTL_W32(0x50C, (EDCA[BK].TXOPlimit<< 16) | (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[BK].AIFSN* slot_time));
#if defined(RTK_AC_SUPPORT) && defined(RTL_MANUAL_EDCA) //for 11ac logo, make BK worse to seperate with BE.
if((AC_SIGMA_MODE != AC_SIGMA_NONE) && (priv->pmib->dot11QosEntry.ManualEDCA))
{
RTL_W32(0x50C, (EDCA[BK].TXOPlimit<< 16) | (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | 0xa4 );
}
#endif
// ODM_Write1Byte(pDM_Odm,ACMHWCTRL, 0x00);
priv->pshare->iot_mode_enable = 0;
if (priv->pshare->rf_ft_var.wifi_beq_iot)
priv->pshare->iot_mode_VI_exist = 0;
#ifdef WMM_VIBE_PRI
priv->pshare->iot_mode_BE_exist = 0;
#endif
#ifdef WMM_BEBK_PRI
priv->pshare->iot_mode_BK_exist = 0;
#endif
#ifdef LOW_TP_TXOP
priv->pshare->BE_cwmax_enhance = 0;
#endif
priv->pshare->iot_mode_VO_exist = 0;
}
BOOLEAN
ChooseIotMainSTA(
struct rtl8192cd_priv *priv,
IN PSTA_INFO_T pstat
)
{
BOOLEAN bhighTP_found_pstat=FALSE;
if ((GET_ROOT(priv)->up_time % 2) == 0) {
unsigned int tx_2s_avg = 0;
unsigned int rx_2s_avg = 0;
int i=0, aggReady=0;
unsigned long total_sum = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes);
int assoc_num = GET_ROOT(priv)->assoc_num;
#ifdef MBSSID
if (GET_ROOT(priv)->pmib->miscEntry.vap_enable){
for (i=0; i<RTL8192CD_NUM_VWLAN; ++i)
assoc_num += GET_ROOT(priv)->pvap_priv[i]-> assoc_num;
}
#endif
#ifdef UNIVERSAL_REPEATER
if (IS_DRV_OPEN(GET_VXD_PRIV(GET_ROOT(priv))))
assoc_num += GET_VXD_PRIV(GET_ROOT(priv))-> assoc_num;
#endif
#ifdef WDS
if(GET_ROOT(priv)->pmib->dot11WdsInfo.wdsEnabled)
assoc_num ++;
#endif
pstat->current_tx_bytes += pstat->tx_byte_cnt;
pstat->current_rx_bytes += pstat->rx_byte_cnt;
if (total_sum != 0) {
if (total_sum <= 1000000) {
tx_2s_avg = (unsigned int)((pstat->current_tx_bytes*100) / total_sum);
rx_2s_avg = (unsigned int)((pstat->current_rx_bytes*100) / total_sum);
} else {
tx_2s_avg = (unsigned int)(pstat->current_tx_bytes / (total_sum / 100));
rx_2s_avg = (unsigned int)(pstat->current_rx_bytes / (total_sum / 100));
}
}
for(i=0; i<8; i++)
aggReady += (pstat->ADDBA_ready[i]);
if ((pstat->ht_cap_len && (
#ifdef SUPPORT_TX_AMSDU
AMSDU_ENABLE ||
#endif
aggReady)) || (pstat->IOTPeer==HT_IOT_PEER_INTEL) || (tx_2s_avg >= 50))
{
if ((assoc_num==1) || (tx_2s_avg + rx_2s_avg >= 25)) {
priv->pshare->highTP_found_pstat = pstat;
}
#ifdef CLIENT_MODE
if (OPMODE & WIFI_STATION_STATE) {
if ((tx_2s_avg + rx_2s_avg) >= 20)
priv->pshare->highTP_found_pstat = pstat;
}
#endif
}
}
else {
pstat->current_tx_bytes = pstat->tx_byte_cnt;
pstat->current_rx_bytes = pstat->rx_byte_cnt;
}
return bhighTP_found_pstat;
}
#ifdef WIFI_WMM
VOID
IotEdcaSwitch(
struct rtl8192cd_priv *priv,
IN unsigned char enable
)
{
int mode=priv->pmib->dot11BssType.net_work_type;
unsigned int slot_time = 20, sifs_time = 10, BE_TXOP = 47, VI_TXOP = 94;
unsigned int vi_cw_max = 4, vi_cw_min = 3, vi_aifs;
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
u32 be_edca, vi_edca;
#endif
if (!(!priv->pmib->dot11OperationEntry.wifi_specific ||
((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific))
#ifdef CLIENT_MODE
|| ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific))
#endif
))
return;
#ifdef RTK_AC_SUPPORT //for 11ac logo, do not dynamic switch edca
if(AC_SIGMA_MODE != AC_SIGMA_NONE)
return;
#endif
if ((mode & WIRELESS_11N) && (priv->pshare->ht_sta_num
#ifdef WDS
|| ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum)
#endif
))
sifs_time = 16;
if (mode & (WIRELESS_11N|WIRELESS_11G|WIRELESS_11A)) {
slot_time = 9;
}
else
{
BE_TXOP = 94;
VI_TXOP = 188;
}
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = -1;
vi_edca = -1;
#endif
if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) {
if (priv->pshare->iot_mode_VO_exist) {
#ifdef WMM_VIBE_PRI
if (priv->pshare->iot_mode_BE_exist)
{
vi_cw_max = 5;
vi_cw_min = 3;
vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
}
else
#endif
{
vi_cw_max = 6;
vi_cw_min = 4;
vi_aifs = 0x2b;
}
}
else {
vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
}
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
vi_edca = ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)
| (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs;
#else
RTL_W32(0x504, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)
| (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs);
#endif
#ifdef WMM_BEBK_PRI
#ifdef CONFIG_RTL_88E_SUPPORT
if ((GET_CHIP_VER(priv) == VERSION_8188E) && priv->pshare->iot_mode_BK_exist) {
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (10 << 12) | (6 << 8) | 0x4f;
#else
RTL_W32(0x50C, (10 << 12) | (6 << 8) | 0x4f);
#endif
}
#endif
#endif
#if defined(CONFIG_WLAN_HAL_8881A)
if (GET_CHIP_VER(priv) == VERSION_8881A)
RTL_W32(0x50C, 0xa64f);
#endif
}
if (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist) {
#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_RTL_8812_SUPPORT)
if (GET_CHIP_VER(priv) == VERSION_8188E || GET_CHIP_VER(priv) == VERSION_8812E) {
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (10 << 12) | (6 << 8) | 0x4f;
#else
RTL_W32(0x508, (10 << 12) | (6 << 8) | 0x4f);
#endif
}
else
#endif
{
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (10 << 12) | (4 << 8) | 0x4f;
#else
RTL_W32(0x508, (10 << 12) | (4 << 8) | 0x4f);
#endif
}
} else if(!enable)
{
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8)
| (sifs_time + 3 * slot_time);
#else
RTL_W32(0x508, (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8)
| (sifs_time + 3 * slot_time));
#endif
#ifdef CONFIG_PCI_HCI
// ODM_Write2Byte(pDM_Odm, RD_CTRL, ODM_Read2Byte(pDM_Odm, RD_CTRL) | (DIS_TXOP_CFE));
#endif
}
else
{
int txop;
unsigned int cw_max;
#ifdef LOW_TP_TXOP
unsigned int txop_close;
#endif
#if(defined LOW_TP_TXOP)
cw_max = ((priv->pshare->BE_cwmax_enhance) ? 10 : 6);
txop_close = ((priv->pshare->rf_ft_var.low_tp_txop && priv->pshare->rf_ft_var.low_tp_txop_close) ? 1 : 0);
if(priv->pshare->txop_enlarge == 0xe) //if intel case
txop = (txop_close ? 0 : (BE_TXOP*2));
else //if other case
txop = (txop_close ? 0: (BE_TXOP*priv->pshare->txop_enlarge));
#else
cw_max=6;
if((priv->pshare->txop_enlarge==0xe)||(priv->pshare->txop_enlarge==0xd))
txop=BE_TXOP*2;
else
txop=BE_TXOP*priv->pshare->txop_enlarge;
#endif
if (priv->pshare->ht_sta_num
#ifdef WDS
|| ((OPMODE & WIFI_AP_STATE) && (mode & WIRELESS_11N) &&
priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum)
#endif
)
{
if (priv->pshare->txop_enlarge == 0xe) {
// is intel client, use a different edca value
//ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop<< 16) | (cw_max<< 12) | (4 << 8) | 0x1f);
if (get_rf_mimo_mode(priv)==MIMO_1T1R) {
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (txop << 16) | (5 << 12) | (3 << 8) | 0x1f;
#else
RTL_W32(0x508, (txop << 16) | (5 << 12) | (3 << 8) | 0x1f);
#endif
}
else {
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (txop << 16) | (8 << 12) | (5 << 8) | 0x1f;
#else
RTL_W32(0x508, (txop << 16) | (8 << 12) | (5 << 8) | 0x1f);
#endif
}
#ifdef CONFIG_PCI_HCI
// ODM_Write2Byte(pDM_Odm, RD_CTRL, ODM_Read2Byte(pDM_Odm, RD_CTRL) & ~(DIS_TXOP_CFE));
#endif
priv->pshare->txop_enlarge = 2;
}
#ifndef LOW_TP_TXOP
else if (priv->pshare->txop_enlarge == 0xd) {
// is intel ralink, use a different edca value
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (txop << 16) | (6 << 12) | (5 << 8) | 0x2b;
#else
RTL_W32(0x508, (txop << 16) | (6 << 12) | (5 << 8) | 0x2b);
#endif
priv->pshare->txop_enlarge = 2;
}
#endif
else
{
if (get_rf_mimo_mode(priv)==MIMO_2T2R) {
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (txop << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time);
#else
RTL_W32(0x508, (txop << 16) |
(cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
#endif
}
else
#if(DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP)
{
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (txop << 16) |
(((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | (3 << 8) | (sifs_time + 2 * slot_time);
#else
RTL_W32(0x508, (txop << 16) |
(((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | (3 << 8) | (sifs_time + 2 * slot_time));
#endif
}
#else
{
PSTA_INFO_T pstat = priv->pshare->highTP_found_pstat;
if ((GET_CHIP_VER(priv)==VERSION_8881A) && pstat && (pstat->IOTPeer == HT_IOT_PEER_HTC))
RTL_W32(0x508, 0x642b);
else {
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (txop << 16) | (5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time);
#else
RTL_W32(0x508, (txop << 16) |
(5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time));
#endif
}
}
#endif
}
}
else
{
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
be_edca = (BE_TXOP << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time);
#else
#if(defined LOW_TP_TXOP)
RTL_W32(0x508, (BE_TXOP << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
#endif
#endif
}
}
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
notify_IOT_EDCA_switch(priv, be_edca, vi_edca);
#endif
}
#endif
VOID
IotEngine(
struct rtl8192cd_priv *priv
)
{
PSTA_INFO_T pstat = NULL;
u4Byte i;
#ifdef SW_TX_QUEUE
int swqd = priv->swq_decision;
#endif
#ifdef WIFI_WMM
unsigned int switch_turbo = 0, avg_tp;
#endif
////////////////////////////////////////////////////////
// if EDCA Turbo function is not supported or Manual EDCA Setting
// then return
////////////////////////////////////////////////////////
#if(defined(RTL_MANUAL_EDCA) && defined(WIFI_WMM))
if(priv->pmib->dot11QosEntry.ManualEDCA){
return ;
}
#endif
pstat=priv->pshare->highTP_found_pstat;
// if(pstat) {
// if((pstat->tx_avarage + pstat->rx_avarage) < (1<<17)) // 1M bps
// pstat = NULL;
// }
#ifdef WIFI_WMM
if (QOS_ENABLE) {
if (!priv->pmib->dot11OperationEntry.wifi_specific
||((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific))
) {
if (priv->pshare->iot_mode_enable &&
((priv->pshare->phw->VO_pkt_count > 50) ||
(priv->pshare->phw->VI_pkt_count > 50) ||
(priv->pshare->phw->BK_pkt_count > 50))) {
priv->pshare->iot_mode_enable = 0;
switch_turbo++;
#ifdef CONFIG_WLAN_HAL_8881A
if (GET_CHIP_VER(priv) == VERSION_8881A) {
RTL_W32(0x460, 0x03086666);
}
#endif //CONFIG_WLAN_HAL_8881A
} else if ((!priv->pshare->iot_mode_enable) &&
((priv->pshare->phw->VO_pkt_count < 50) &&
(priv->pshare->phw->VI_pkt_count < 50) &&
(priv->pshare->phw->BK_pkt_count < 50))) {
priv->pshare->iot_mode_enable++;
switch_turbo++;
//#ifdef CONFIG_WLAN_HAL_8881A
#if 0
if (GET_CHIP_VER(priv) == VERSION_8881A) {
if (get_bonding_type_8881A()==BOND_8881AB) {
RTL_W32(0x460, 0x03086666);
}
else {
RTL_W32(0x460, 0x0320ffff);
}
}
#endif //CONFIG_WLAN_HAL_8881A
}
}
if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific)
{
if (!priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count > 50)) {
priv->pshare->iot_mode_VO_exist++;
switch_turbo++;
} else if (priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count < 50)) {
priv->pshare->iot_mode_VO_exist = 0;
switch_turbo++;
}
#if(defined WMM_VIBE_PRI)
if (priv->pshare->iot_mode_VO_exist) {
//printk("[%s %d] BE_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BE_pkt_count);
if (!priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count > 250)) {
priv->pshare->iot_mode_BE_exist++;
switch_turbo++;
} else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count < 250)) {
priv->pshare->iot_mode_BE_exist = 0;
switch_turbo++;
}
}
#endif
#if(defined WMM_BEBK_PRI)
if (priv->pshare->phw->BE_pkt_count) {
//printk("[%s %d] BK_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BK_pkt_count);
if (!priv->pshare->iot_mode_BK_exist && (priv->pshare->phw->BK_pkt_count > 250)) {
priv->pshare->iot_mode_BK_exist++;
switch_turbo++;
} else if (priv->pshare->iot_mode_BK_exist && (priv->pshare->phw->BK_pkt_count < 250)) {
priv->pshare->iot_mode_BK_exist = 0;
switch_turbo++;
}
}
#endif
if (priv->pshare->rf_ft_var.wifi_beq_iot)
{
if (!priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count > 50)) {
priv->pshare->iot_mode_VI_exist++;
switch_turbo++;
} else if (priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count < 50)) {
priv->pshare->iot_mode_VI_exist = 0;
switch_turbo++;
}
}
}
else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) {
if (priv->pshare->txop_enlarge) {
priv->pshare->txop_enlarge = 0;
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
}
#if(defined(CLIENT_MODE) )
if ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific))
{
if (priv->pshare->iot_mode_enable &&
(((priv->pshare->phw->VO_pkt_count > 50) ||
(priv->pshare->phw->VI_pkt_count > 50) ||
(priv->pshare->phw->BK_pkt_count > 50)) ||
(pstat && (!pstat->ADDBA_ready[0]) & (!pstat->ADDBA_ready[3]))))
{
priv->pshare->iot_mode_enable = 0;
switch_turbo++;
}
else if ((!priv->pshare->iot_mode_enable) &&
(((priv->pshare->phw->VO_pkt_count < 50) &&
(priv->pshare->phw->VI_pkt_count < 50) &&
(priv->pshare->phw->BK_pkt_count < 50)) &&
(pstat && (pstat->ADDBA_ready[0] | pstat->ADDBA_ready[3]))))
{
priv->pshare->iot_mode_enable++;
switch_turbo++;
}
}
#endif
priv->pshare->phw->VO_pkt_count = 0;
priv->pshare->phw->VI_pkt_count = 0;
priv->pshare->phw->BK_pkt_count = 0;
#if(defined WMM_VIBE_PRI)
priv->pshare->phw->BE_pkt_count = 0;
#endif
if (priv->pshare->rf_ft_var.wifi_beq_iot)
priv->pshare->phw->VI_rx_pkt_count = 0;
}
#endif
if ((priv->up_time % 2) == 0) {
/*
* decide EDCA content for different chip vendor
*/
#ifdef WIFI_WMM
if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific ||
((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
#ifdef CLIENT_MODE
|| ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
#endif
))
{
if (pstat && pstat->rssi >= priv->pshare->rf_ft_var.txop_enlarge_upper) {
#ifdef LOW_TP_TXOP
if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
{
if (priv->pshare->txop_enlarge != 0xe)
{
priv->pshare->txop_enlarge = 0xe;
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
}
else if (priv->pshare->txop_enlarge != 2)
{
priv->pshare->txop_enlarge = 2;
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
#else
if (priv->pshare->txop_enlarge != 2)
{
if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
priv->pshare->txop_enlarge = 0xe;
else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
priv->pshare->txop_enlarge = 0xd;
else if (pstat->IOTPeer==HT_IOT_PEER_HTC)
priv->pshare->txop_enlarge = 0;
else
priv->pshare->txop_enlarge = 2;
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
#endif
}
else if ((!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower)
#ifdef SW_TX_QUEUE
&& (priv->swq_en == 0)
#endif
)
{
if (priv->pshare->txop_enlarge) {
priv->pshare->txop_enlarge = 0;
if (priv->pshare->iot_mode_enable)
switch_turbo++;
}
}
#if(defined LOW_TP_TXOP)
// for Intel IOT, need to enlarge CW MAX from 6 to 10
if (pstat && pstat->IOTPeer==HT_IOT_PEER_INTEL && (((pstat->tx_avarage+pstat->rx_avarage)>>10) <
priv->pshare->rf_ft_var.cwmax_enhance_thd))
{
if (!priv->pshare->BE_cwmax_enhance && priv->pshare->iot_mode_enable)
{
priv->pshare->BE_cwmax_enhance = 1;
switch_turbo++;
}
} else {
if (priv->pshare->BE_cwmax_enhance) {
priv->pshare->BE_cwmax_enhance = 0;
switch_turbo++;
}
}
#endif
}
#endif
priv->pshare->current_tx_bytes = 0;
priv->pshare->current_rx_bytes = 0;
}else {
if ((GET_CHIP_VER(priv) == VERSION_8881A)||(GET_CHIP_VER(priv) == VERSION_8192E)|| (GET_CHIP_VER(priv) == VERSION_8188E) ){
unsigned int uldl_tp = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes)>>17;
if((uldl_tp > 40) && (priv->pshare->agg_to!= 1)) {
RTL_W8(0x462, 0x08);
priv->pshare->agg_to = 1;
} else if((uldl_tp < 35) && (priv->pshare->agg_to !=0)) {
RTL_W8(0x462, 0x02);
priv->pshare->agg_to = 0;
}
}
}
#if(defined SW_TX_QUEUE)
if(AMPDU_ENABLE) {
#ifdef TX_EARLY_MODE
if (GET_TX_EARLY_MODE) {
if (!GET_EM_SWQ_ENABLE &&
((priv->assoc_num > 1) ||
(pstat && pstat->IOTPeer != HT_IOT_PEER_UNKNOWN))) {
if ((priv->pshare->em_tx_byte_cnt >> 17) > EM_TP_UP_BOUND)
priv->pshare->reach_tx_limit_cnt++;
else
priv->pshare->reach_tx_limit_cnt = 0;
if (priv->pshare->txop_enlarge && priv->pshare->reach_tx_limit_cnt /*>= WAIT_TP_TIME*/) {
GET_EM_SWQ_ENABLE = 1;
priv->pshare->reach_tx_limit_cnt = 0;
if (pstat->IOTPeer == HT_IOT_PEER_INTEL)
MAX_EM_QUE_NUM = 12;
else if (pstat->IOTPeer == HT_IOT_PEER_RALINK)
MAX_EM_QUE_NUM = 10;
enable_em(priv);
}
}
else if (GET_EM_SWQ_ENABLE) {
if ((priv->pshare->em_tx_byte_cnt >> 17) < EM_TP_LOW_BOUND)
priv->pshare->reach_tx_limit_cnt++;
else
priv->pshare->reach_tx_limit_cnt = 0;
if (!priv->pshare->txop_enlarge || priv->pshare->reach_tx_limit_cnt >= WAIT_TP_TIME) {
GET_EM_SWQ_ENABLE = 0;
priv->pshare->reach_tx_limit_cnt = 0;
disable_em(priv);
}
}
}
#endif
#if defined(CONFIG_WLAN_HAL_8881A) || defined(CONFIG_WLAN_HAL_8192EE) || defined(CONFIG_RTL_8812_SUPPORT)
if ((GET_CHIP_VER(priv) == VERSION_8188E) || (priv->assoc_num > 9))
#endif
{
if((priv->ext_stats.tx_avarage>>17)>TP_HIGH_WATER_MARK /*|| (priv->ext_stats.rx_avarage>>17)> TP_HIGH_WATER_MARK*/) {
if ((priv->swq_decision == 0)){
switch_turbo++;
if (pstat) {
if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
priv->pshare->txop_enlarge = 0xe;
else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
priv->pshare->txop_enlarge = 0xd;
else if (pstat->IOTPeer==HT_IOT_PEER_HTC)
priv->pshare->txop_enlarge = 0;
else
priv->pshare->txop_enlarge = 2;
} else if (priv->pshare->txop_enlarge == 0) {
priv->pshare->txop_enlarge = 2;
}
priv->swq_decision = 1;
}
}
else{
if (priv->swq_txmac_chg >= priv->pshare->rf_ft_var.swq_en_highthd){
if ((priv->swq_decision == 0)){
switch_turbo++;
if (priv->pshare->txop_enlarge == 0)
priv->pshare->txop_enlarge = 2;
priv->swq_decision = 1;
}
else
{
if ((switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0))
{
priv->pshare->txop_enlarge = 2;
switch_turbo--;
}
}
}
else if(priv->swq_txmac_chg <= priv->pshare->rf_ft_var.swq_dis_lowthd){
priv->swq_decision = 0;
}
else if ((priv->swq_decision == 1) && (switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0)){
priv->pshare->txop_enlarge = 2;
switch_turbo--;
}
}
}
if( swqd ^priv->swq_decision ) {
if((priv->swq_decision == 1)
#if (defined(TX_EARLY_MODE))
|| (GET_EM_SWQ_ENABLE == 1)
#endif
) {
priv->swq_en = 1;
priv->swqen_keeptime = priv->up_time;
extern void init_STA_SWQAggNum(struct rtl8192cd_priv *priv);
init_STA_SWQAggNum(priv);
} else {
priv->swq_en = 0;
priv->swqen_keeptime = 0;
}
}
}
if(priv->pshare->rf_ft_var.swq_enable == 0) {
priv->swq_en = 0;
priv->swqen_keeptime = 0;
}
#endif
#ifdef WIFI_WMM
#ifdef LOW_TP_TXOP
if ((!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2))
&& QOS_ENABLE) {
if (switch_turbo || priv->pshare->rf_ft_var.low_tp_txop) {
unsigned int thd_tp;
unsigned char under_thd;
unsigned int curr_tp;
if (priv->pmib->dot11BssType.net_work_type & (WIRELESS_11N| WIRELESS_11G))
{
// Determine the upper bound throughput threshold.
if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) {
if (priv->assoc_num && priv->assoc_num != priv->pshare->ht_sta_num)
thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g;
else
thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_n;
}
else
thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g;
// Determine to close txop.
#if defined(UNIVERSAL_REPEATER) || defined(MBSSID)
if(IS_STA_VALID(pstat))
{
struct rtl8192cd_priv *tmppriv;
struct aid_obj *aidarray;
aidarray = container_of(pstat, struct aid_obj, station);
tmppriv = aidarray->priv;
curr_tp = (unsigned int)(tmppriv->ext_stats.tx_avarage>>17) + (unsigned int)(tmppriv->ext_stats.rx_avarage>>17);
}
else
#endif
curr_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17);
if (curr_tp <= thd_tp && curr_tp >= priv->pshare->rf_ft_var.low_tp_txop_thd_low)
under_thd = 1;
else
under_thd = 0;
}
else
{
under_thd = 0;
}
if (switch_turbo)
{
priv->pshare->rf_ft_var.low_tp_txop_close = under_thd;
priv->pshare->rf_ft_var.low_tp_txop_count = 0;
}
else if (priv->pshare->iot_mode_enable && (priv->pshare->rf_ft_var.low_tp_txop_close != under_thd)) {
priv->pshare->rf_ft_var.low_tp_txop_count++;
if (priv->pshare->rf_ft_var.low_tp_txop_close) {
priv->pshare->rf_ft_var.low_tp_txop_count = priv->pshare->rf_ft_var.low_tp_txop_delay;
}
if (priv->pshare->rf_ft_var.low_tp_txop_count ==priv->pshare->rf_ft_var.low_tp_txop_delay)
{
priv->pshare->rf_ft_var.low_tp_txop_count = 0;
priv->pshare->rf_ft_var.low_tp_txop_close = under_thd;
switch_turbo++;
}
}
else
{
priv->pshare->rf_ft_var.low_tp_txop_count = 0;
}
}
}
#endif
#ifdef WMM_DSCP_C42
if (switch_turbo) {
if (!priv->pshare->iot_mode_enable && !priv->pshare->aggrmax_change) {
RTL_W16(0x4ca, 0x0404);
priv->pshare->aggrmax_change = 1;
}
else if (priv->pshare->iot_mode_enable && priv->pshare->aggrmax_change) {
RTL_W16(0x4ca, priv->pshare->aggrmax_bak);
priv->pshare->aggrmax_change = 0;
}
}
#endif
#ifdef TX_EARLY_MODE
unsigned int em_tp = ((priv->ext_stats.tx_avarage>>17) + (priv->ext_stats.rx_avarage>>17));
if (em_tp > 80)
RTL_W32(0x508, (0x5e << 16) | (4 << 12) | (3 << 8) | 0x19);
else //if (em_tp < 75)
RTL_W32(0x508, (0x5e << 16) | (6 << 12) | (5 << 8) | 0x2b);
#endif
if (switch_turbo)
IotEdcaSwitch( priv, priv->pshare->iot_mode_enable );
#endif
}
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/EdcaTurboCheck.h
Executable
+30
View File
@@ -0,0 +1,30 @@
#ifndef __EDCATURBOCHECK_H__
#define __EDCATURBOCHECK_H__
void EdcaParaInit(
struct rtl8192cd_priv *priv
);
#ifdef WIFI_WMM
VOID
IotEdcaSwitch(
struct rtl8192cd_priv *priv,
unsigned char enable
);
#endif
BOOLEAN
ChooseIotMainSTA(
struct rtl8192cd_priv *priv,
PSTA_INFO_T pstat
);
VOID
IotEngine(
struct rtl8192cd_priv *priv
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Hal8188EPwrSeq.c
Executable
+103
View File
@@ -0,0 +1,103 @@
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
Hal8188EPwrSeq.c
Abstract:
This file includes all kinds of Power Action event for RTL8188E and corresponding hardware configurtions which are released from HW SD.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-07-07 Roger Create.
--*/
#ifdef __ECOS
#include <cyg/io/eth/rltk/819x/wrapper/sys_support.h>
#endif
#include "8192cd.h"
#ifdef CONFIG_RTL_88E_SUPPORT
#include "HalPwrSeqCmd.h"
#include "Hal8188EPwrSeq.h"
/*
* drivers should parse below arrays and do the corresponding actions
*/
/* Power on Array */
WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_CARDEMU_TO_ACT
RTL8188E_TRANS_END
};
/* Radio off Array */
WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
RTL8188E_TRANS_END
};
/* Card Disable Array */
WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
RTL8188E_TRANS_CARDEMU_TO_CARDDIS
RTL8188E_TRANS_END
};
/* Card Enable Array */
WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_CARDDIS_TO_CARDEMU
RTL8188E_TRANS_CARDEMU_TO_ACT
RTL8188E_TRANS_END
};
/* Suspend Array */
WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
RTL8188E_TRANS_CARDEMU_TO_SUS
RTL8188E_TRANS_END
};
/* Resume Array */
WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_SUS_TO_CARDEMU
RTL8188E_TRANS_CARDEMU_TO_ACT
RTL8188E_TRANS_END
};
/* HWPDN Array */
WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS]=
{
RTL8188E_TRANS_ACT_TO_CARDEMU
RTL8188E_TRANS_CARDEMU_TO_PDN
RTL8188E_TRANS_END
};
/* Enter LPS */
WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS]=
{
//FW behavior
RTL8188E_TRANS_ACT_TO_LPS
RTL8188E_TRANS_END
};
/* Leave LPS */
WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS]=
{
//FW behavior
RTL8188E_TRANS_LPS_TO_ACT
RTL8188E_TRANS_END
};
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Hal8188EPwrSeq.h
Executable
+164
View File
@@ -0,0 +1,164 @@
#ifdef CONFIG_RTL_88E_SUPPORT
#ifndef REALTEK_POWER_SEQUENCE_8188E
#define REALTEK_POWER_SEQUENCE_8188E
#include "typedef.h"
#ifdef BIT
#undef BIT
#endif
#define BIT(x) (1 << (x))
/*
Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
PWR SEQ Version: rtl8188E_PwrSeq_V09.h
*/
#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8188E_TRANS_END_STEPS 1
#define RTL8188E_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
/* {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},*/ /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \
#define RTL8188E_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
#define RTL8188E_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
/* {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},*/ /*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
//This is used by driver for LPSRadioOff Procedure, not for FW LPS Step
#define RTL8188E_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
#define RTL8188E_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8188E_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Hal8192CDMOutSrc.c
Executable
+9606
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File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/HalDMOutSrc.c
Executable
+1956
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File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/HalPwrSeqCmd.c
Executable
+177
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@@ -0,0 +1,177 @@
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
HalPwrSeqCmd.c
Abstract:
Implement HW Power sequence configuration CMD handling routine for Realtek devices.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-07-07 Roger Create.
--*/
#ifdef __ECOS
#include <cyg/io/eth/rltk/819x/wrapper/sys_support.h>
#include <cyg/io/eth/rltk/819x/wrapper/skbuff.h>
#include <cyg/io/eth/rltk/819x/wrapper/timer.h>
#include <cyg/io/eth/rltk/819x/wrapper/wrapper.h>
#endif
//#include "Mp_Precomp.h"
#ifdef __KERNEL__
#include <linux/kernel.h>
#endif
#include "8192cd.h"
#include "8192cd_debug.h"
#include "8192cd_headers.h"
#include "8192cd_util.h"
#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_RTL_8812_SUPPORT)
#define TRUE 1
#define FALSE 0
//
// Description:
// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
//
// Assumption:
// We should follow specific format which was released from HW SD.
//
// 2011.07.07, added by Roger.
//
unsigned int HalPwrSeqCmdParsing(struct rtl8192cd_priv *priv, unsigned char CutVersion, unsigned char FabVersion,
unsigned char InterfaceType, WLAN_PWR_CFG PwrSeqCmd[])
{
WLAN_PWR_CFG PwrCfgCmd = {0};
unsigned int bPollingBit = FALSE;
unsigned int AryIdx=0;
unsigned char value = 0;
unsigned int offset = 0;
unsigned int pollingCount = 0; // polling autoload done.
unsigned int maxPollingCnt = 5000;
do {
PwrCfgCmd=PwrSeqCmd[AryIdx];
DEBUG_INFO("%s %d, ENTRY, offset:0x%x, cut_msk:0x%x, fab_msk:0x%x, if_msk:0x%x, base:0x%x, cmd:0x%x, msk:0x%x, value:0x%x\n",
__FUNCTION__, __LINE__, GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
GET_PWR_CFG_FAB_MASK(PwrCfgCmd), GET_PWR_CFG_INTF_MASK(PwrCfgCmd), GET_PWR_CFG_BASE(PwrCfgCmd),
GET_PWR_CFG_CMD(PwrCfgCmd), GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd));
//2 Only Handle the command whose FAB, CUT, and Interface are matched
if((GET_PWR_CFG_FAB_MASK(PwrCfgCmd)&FabVersion)&&
(GET_PWR_CFG_CUT_MASK(PwrCfgCmd)&CutVersion)&&
(GET_PWR_CFG_INTF_MASK(PwrCfgCmd)&InterfaceType)) {
switch(GET_PWR_CFG_CMD(PwrCfgCmd))
{
case PWR_CMD_READ:
DEBUG_INFO("%s %d, PWR_CMD_READ\n", __FUNCTION__, __LINE__);
break;
case PWR_CMD_WRITE:
DEBUG_INFO("%s %d, PWR_CMD_WRITE\n", __FUNCTION__, __LINE__);
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
#ifdef CONFIG_SDIO_HCI
//
// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
// 2011.07.07.
//
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
{
// Read Back SDIO Local value
value = SdioLocalCmd52Read1Byte(priv, offset);
value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
// Write Back SDIO Local value
SdioLocalCmd52Write1Byte(priv, offset, value);
}
else
#endif
{
//Read the value from system register
value = RTL_R8(offset);
value = value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
value = value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
//Write the value back to sytem register
RTL_W8(offset, value);
}
break;
case PWR_CMD_POLLING:
DEBUG_INFO("%s %d, PWR_CMD_POLLING\n", __FUNCTION__, __LINE__);
bPollingBit = FALSE;
offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
do {
#ifdef CONFIG_SDIO_HCI
if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
value = SdioLocalCmd52Read1Byte(priv, offset);
else
#endif
value = RTL_R8(offset);
value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
if(value==(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd)))
bPollingBit=TRUE;
else
delay_us(10);
if(pollingCount++ > maxPollingCnt){
int i, j, len;
unsigned char tmpbuf[100];
printk("%s %d, PWR_CMD_POLLING, Fail to polling Offset[0x%x]\n", __FUNCTION__, __LINE__, offset);
panic_printk("\nMAC Registers:\n");
for (i=0; i<0x100; i+=0x10) {
len = sprintf((char *)tmpbuf, "%03X\t", i);
for (j=i; j<i+0x10; j+=4)
len += sprintf((char *)(tmpbuf+len), "%08X ", (unsigned int)RTL_R32(j));
panic_printk("%s\n", (char *)tmpbuf);
}
}
panic_printk("\n");
return FALSE;
}
}while(!bPollingBit);
break;
case PWR_CMD_DELAY:
DEBUG_INFO("%s %d, PWR_CMD_DELAY\n", __FUNCTION__, __LINE__);
if(GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd));
else
delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
break;
case PWR_CMD_END:
// When this command is parsed, end the process
DEBUG_INFO("%s %d, PWR_CMD_END\n", __FUNCTION__, __LINE__);
return TRUE;
break;
default:
DEBUG_ERR("%s %d, Unknown CMD!!\n", __FUNCTION__, __LINE__);
break;
}
}
AryIdx++;//Add Array Index
}while(1);
return TRUE;
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/HalPwrSeqCmd.h
Executable
+109
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@@ -0,0 +1,109 @@
#ifndef __HAL_PWRSEQCMD_H__
#define __HAL_PWRSEQCMD_H__
//#if defined(CONFIG_RTL_88E_SUPPORT)|| defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_92E_SUPPORT)
/*---------------------------------------------*/
//3 The value of cmd: 4 bits
/*---------------------------------------------*/
#define PWR_CMD_READ 0x00
// offset: the read register offset
// msk: the mask of the read value
// value: N/A, left by 0
// note: dirver shall implement this function by read & msk
#define PWR_CMD_WRITE 0x01
// offset: the read register offset
// msk: the mask of the write bits
// value: write value
// note: driver shall implement this cmd by read & msk after write
#define PWR_CMD_POLLING 0x02
// offset: the read register offset
// msk: the mask of the polled value
// value: the value to be polled, masked by the msd field.
// note: driver shall implement this cmd by
// do{
// if( (Read(offset) & msk) == (value & msk) )
// break;
// } while(not timeout);
#define PWR_CMD_DELAY 0x03
// offset: the value to delay
// msk: N/A
// value: the unit of delay, 0: us, 1: ms
#define PWR_CMD_END 0x04
// offset: N/A
// msk: N/A
// value: N/A
/*---------------------------------------------*/
//3 The value of base: 4 bits
/*---------------------------------------------*/
// define the base address of each block
#define PWR_BASEADDR_MAC 0x00
#define PWR_BASEADDR_USB 0x01
#define PWR_BASEADDR_PCIE 0x02
#define PWR_BASEADDR_SDIO 0x03
/*---------------------------------------------*/
//3 The value of interface_msk: 4 bits
/*---------------------------------------------*/
#define PWR_INTF_SDIO_MSK BIT(0)
#define PWR_INTF_USB_MSK BIT(1)
#define PWR_INTF_PCI_MSK BIT(2)
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3 The value of fab_msk: 4 bits
/*---------------------------------------------*/
#define PWR_FAB_TSMC_MSK BIT(0)
#define PWR_FAB_UMC_MSK BIT(1)
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
/*---------------------------------------------*/
//3The value of cut_msk: 8 bits
/*---------------------------------------------*/
#define PWR_CUT_TESTCHIP_MSK BIT(0)
#define PWR_CUT_A_MSK BIT(1)
#define PWR_CUT_B_MSK BIT(2)
#define PWR_CUT_C_MSK BIT(3)
#define PWR_CUT_D_MSK BIT(4)
#define PWR_CUT_E_MSK BIT(5)
#define PWR_CUT_F_MSK BIT(6)
#define PWR_CUT_G_MSK BIT(7)
#define PWR_CUT_ALL_MSK 0xFF
typedef enum _PWRSEQ_CMD_DELAY_UNIT_
{
PWRSEQ_DELAY_US,
PWRSEQ_DELAY_MS,
} PWRSEQ_DELAY_UNIT;
typedef struct _WL_PWR_CFG_
{
unsigned short offset;
unsigned char cut_msk;
unsigned char fab_msk:4;
unsigned char interface_msk:4;
unsigned char base:4;
unsigned char cmd:4;
unsigned char msk;
unsigned char value;
} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
//#endif
#endif //__HAL_PWRSEQCMD_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Kconfig
Executable
+682
View File
@@ -0,0 +1,682 @@
#
# Wireless LAN device configuration
#
config RTL8192CD
tristate "RTL8192C/D 802.11b/g/n support"
select WIRELESS_EXT
##########################################################################
# Select the interface WiFi device connects to
##########################################################################
config PCI_HCI
bool
default y
##########################################################################
# Select WiFi device on Lextra Bus
##########################################################################
#config USE_Lextra_BUS
# bool "USE Lextra BUS WiFi device"
# depends on CONFIG_RTL_8881A && RTL8192CD
# default n
#choice
# prompt "Lextra BUS device"
# depends on USE_Lextra_BUS
# default LBUS_8881A
#config LBUS_8881A
# bool "Realtek 8881A wireless support "
# select RTL_ODM_WLAN_DRIVER
#endchoice
config WLAN_HAL_8881A
bool "Realtek 8881A wireless support "
depends on RTL_8881A && RTL8192CD
select RTL_ODM_WLAN_DRIVER
default y
choice
prompt "8881A PA TYPE"
depends on RTL_8881A
default 8881A_EXT_PA
config 8881A_EXT_PA
bool "External PA (skyworks 85703)"
config 8881A_INT_PA
bool "Internal PA (skyworks SE5008)"
config 8881A_RTC5634
bool "Internal PA (RTC 5634)"
endchoice
config RTL_8881A_SELECTIVE
bool "Realtek 8881A selective support "
depends on WLAN_HAL_8881A && !(RTL_88E_SUPPORT || WLAN_HAL_8192EE)
default y
config RTL_8881A_ANT_SWITCH
bool "Realtek 8881A Enable Antenna Diversity"
depends on WLAN_HAL_8881A
default n
choice
prompt "Choose Antenna Diversity Type"
depends on RTL_8881A_ANT_SWITCH
default NO_5G_DIVERSITY_8881A
config NO_5G_DIVERSITY_8881A
bool "Not Support Antenna Diversity"
config 5G_CGCS_RX_DIVERSITY_8881A
bool "Enable RX Antenna Diversity"
config 5G_CG_TRX_DIVERSITY_8881A
bool "Enable TRX Antenna Diversity"
config 2G5G_CG_TRX_DIVERSITY_8881A
bool "Enable 2G5G TRX Antenna Diversity"
#config 5G_CG_SMART_ANT_DIVERSITY
# bool "Enable Smart Antenna Diversity"
endchoice
#choice
# prompt "Register parameter"
# depends on RTL_8881A
# default MAC_PHY_RF_Parameter_V702B_Skyworth
# config MAC_PHY_RF_Parameter_V700
# bool "MAC PHY RF Parameter V700"
# config MAC_PHY_RF_Parameter_V702B
# bool "MAC PHY RF Parameter V702B"
# config MAC_PHY_RF_Parameter_V702B_Skyworth
# bool "MAC PHY RF Parameter V702B Skyworth"
# config MAC_PHY_RF_Parameter_V702B_MP
# bool "MAC PHY RF Parameter V702B MP"
#endchoice
config MAC_PHY_RF_Parameter_V702B_Skyworth
bool
default y
##########################################################################
# Select WiFi device on PCIe slot 0
##########################################################################
config USE_PCIE_SLOT_0
bool "Use PCIe slot 0 WiFi device"
depends on RTL8192CD
default y
choice
prompt "PCIe Slot 0 device"
depends on USE_PCIE_SLOT_0
default SLOT_0_92C
config SLOT_0_8192EE
bool "Realtek 8192EE wireless support "
select RTL_ODM_WLAN_DRIVER
config SLOT_0_92C
bool "Realtek 8192C wireless support "
config SLOT_0_92D
bool "Realtek 8192D wireless support"
select RTL_5G_SLOT_0
config RTL_92D_DMDP
bool "RTL8192D dual-MAC-dual-PHY mode"
depends on SLOT_0_92D
default y if (!RTL_8198 && !RTL_8197D && !RTL_8197DL)
config SLOT_0_88E
bool "Realtek 8188E wireless support"
config SLOT_0_8812
bool "Realtek 8812 wireless support"
select RTL_5G_SLOT_0
config SLOT_0_8812AR_VN
bool "Realtek 8812AR-VN wireless support"
select RTL_5G_SLOT_0
config SLOT_0_8814AE
bool "Realtek 8814AE wireless support "
select RTL_ODM_WLAN_DRIVER
select RTL_5G_SLOT_0
config SLOT_0_8194AE
bool "Realtek 8194AE wireless support "
select RTL_ODM_WLAN_DRIVER
endchoice
choice
prompt "RFE Type"
depends on USE_PCIE_SLOT_0 && (SLOT_0_8814AE || SLOT_0_8194AE)
default SLOT_0_RFE_TYPE_2
config SLOT_0_RFE_TYPE_0
bool "Type 0: internal PA/LNA"
config SLOT_0_RFE_TYPE_2
bool "Type 2: external PA/LNA (2G SKY85300, 5G LX5586A)"
select SLOT_0_EXT_PA
select SLOT_0_EXT_LNA
config SLOT_0_RFE_TYPE_3
bool "Type 3: external PA/LNA (2G SE2623L/SKY85201-11, 5G SKY85405/SKY85605-11)"
select SLOT_0_EXT_PA
select SLOT_0_EXT_LNA
config SLOT_0_RFE_TYPE_4
bool "Type 4: external PA/LNA (2G SKY85303, 5G SKY85717)"
select SLOT_0_EXT_PA
select SLOT_0_EXT_LNA
config SLOT_0_RFE_TYPE_5
bool "Type 5: external PA/LNA (2G SE2623L/SKY85201-11, 5G SKY85405/SKY85605-11)"
select SLOT_0_EXT_PA
select SLOT_0_EXT_LNA
endchoice
config SLOT_0_EXT_PA
bool "PCIe slot 0 Enable external PA"
depends on USE_PCIE_SLOT_0 && (!SLOT_0_RFE_TYPE_0)
default n
config SLOT_0_EXT_LNA
bool "PCIe slot 0 Enable external LNA"
depends on USE_PCIE_SLOT_0 && (SLOT_0_92C || SLOT_0_88E || SLOT_0_8812 || SLOT_0_8812AR_VN || SLOT_0_8192EE ||SLOT_0_8814AE || SLOT_0_8194AE) && (!SLOT_0_RFE_TYPE_0)
default n
config SLOT_0_TX_BEAMFORMING
bool "PCIe slot 0 Enable Tx Beamforming"
depends on USE_PCIE_SLOT_0 && (SLOT_0_8192EE || SLOT_0_8812 ||SLOT_0_8814AE || SLOT_0_8194AE)
default y
config SLOT_0_ANT_SWITCH
bool "PCIe slot 0 Enable Antenna Diversity"
depends on USE_PCIE_SLOT_0 && (SLOT_0_8192EE || SLOT_0_88E) && !( SLOT_0_92C || SLOT_0_92D)
default n
choice
prompt "Choose Antenna Diversity Type"
depends on SLOT_0_ANT_SWITCH
default NO_2G_DIVERSITY
config NO_2G_DIVERSITY
bool "Not Support Antenna Diversity"
config 2G_CGCS_RX_DIVERSITY
bool "Enable RX Antenna Diversity"
config 2G_CG_TRX_DIVERSITY
bool "Enable TRX Antenna Diversity"
#config 2G_CG_SMART_ANT_DIVERSITY
# bool "Enable Smart Antenna Diversity"
endchoice
##########################################################################
# Select WiFi device on PCIe slot 1
##########################################################################
config USE_PCIE_SLOT_1
bool "Use PCIe slot 1 WiFi device"
depends on RTL8192CD && (RTL_8198 || RTL_8197D || RTL_8197DL || RTL8672 || RTL_8198C)
default y
choice
prompt "PCIe Slot 1 device"
depends on USE_PCIE_SLOT_1
default SLOT_1_92D
config SLOT_1_92C
bool "Realtek 8192C wireless support"
config SLOT_1_92D
bool "Realtek 8192D wireless support"
select RTL_5G_SLOT_1
#config RTL_92D_DMDP
# bool "RTL8192D dual-MAC-dual-PHY mode"
# depends on SLOT_1_92D
# default y
config SLOT_1_88E
bool "Realtek 8188E wireless support"
config SLOT_1_8812
bool "Realtek 8812 wireless support"
select RTL_5G_SLOT_1
config SLOT_1_8192EE
bool "Realtek 8192EE wireless support "
select RTL_ODM_WLAN_DRIVER
config SLOT_1_8812AR_VN
bool "Realtek 8812AR-VN wireless support"
select RTL_5G_SLOT_1
config SLOT_1_8814AE
bool "Realtek 8814AE wireless support "
select RTL_ODM_WLAN_DRIVER
select RTL_5G_SLOT_1
config SLOT_1_8194AE
bool "Realtek 8194AE wireless support "
select RTL_ODM_WLAN_DRIVER
endchoice
choice
prompt "RFE Type"
depends on USE_PCIE_SLOT_1 && (SLOT_1_8814AE || SLOT_1_8194AE)
default SLOT_1_RFE_TYPE_2
config SLOT_1_RFE_TYPE_0
bool "Type 0: internal PA/LNA"
config SLOT_1_RFE_TYPE_2
bool "Type 2: external PA/LNA (2G SKY85300, 5G LX5586A)"
select SLOT_1_EXT_PA
select SLOT_1_EXT_LNA
config SLOT_1_RFE_TYPE_3
bool "Type 3: external PA/LNA (2G SE2623L/SKY85201-11, 5G SKY85405/SKY85605-11)"
select SLOT_1_EXT_PA
select SLOT_1_EXT_LNA
config SLOT_1_RFE_TYPE_4
bool "Type 4: external PA/LNA (2G SKY85303, 5G SKY85717)"
select SLOT_1_EXT_PA
select SLOT_1_EXT_LNA
config SLOT_1_RFE_TYPE_5
bool "Type 5: external PA/LNA (2G SE2623L/SKY85201-11, 5G SKY85405/SKY85605-11)"
select SLOT_1_EXT_PA
select SLOT_1_EXT_LNA
endchoice
config SLOT_1_EXT_PA
bool "PCIe slot 1 Enable external PA"
depends on USE_PCIE_SLOT_1 && (!SLOT_1_RFE_TYPE_0)
default n
config SLOT_1_EXT_LNA
bool "PCIe slot 1 Enable external LNA"
depends on USE_PCIE_SLOT_1 && (SLOT_1_92C || SLOT_1_88E || SLOT_1_8812 || SLOT_1_8812AR_VN || SLOT_1_8192EE || SLOT_1_8814AE || SLOT_1_8194AE) && (!SLOT_1_RFE_TYPE_0)
default n
config SLOT_1_TX_BEAMFORMING
bool "PCIe slot 1 Enable Tx Beamforming"
depends on USE_PCIE_SLOT_1 && (SLOT_1_8192EE || SLOT_1_8812 || SLOT_1_8814AE || SLOT_1_8194AE)
default y
config SLOT_1_ANT_SWITCH
bool "PCIe slot 1 Enable Antenna Diversity"
depends on USE_PCIE_SLOT_1 && SLOT_1_8812
default n
choice
prompt "Choose Antenna Diversity Type"
depends on SLOT_1_ANT_SWITCH && SLOT_1_8812
default NO_5G_DIVERSITY
config NO_5G_DIVERSITY
bool "Not Support Antenna Diversity"
config 5G_CGCS_RX_DIVERSITY
bool "Enable RX Antenna Diversity"
config 5G_CG_TRX_DIVERSITY
bool "Enable TRX Antenna Diversity"
#config 5G_CG_SMART_ANT_DIVERSITY
# bool "Enable Smart Antenna Diversity"
endchoice
##########################################################################
# Select interface config
##########################################################################
###### WLAN_HAL relative configuration
config WLAN_HAL
bool
default y if (WLAN_HAL_8192EE || WLAN_HAL_8881A || WLAN_HAL_8814AE)
config WLAN_HAL_88XX
bool
default y if (WLAN_HAL_8192EE || WLAN_HAL_8881A || WLAN_HAL_8814AE)
config WLAN_HAL_8192EE
bool
default y if (SLOT_0_8192EE || SLOT_1_8192EE)
config WLAN_HAL_8814AE
bool
default y if (SLOT_0_8814AE || SLOT_1_8814AE || SLOT_0_8194AE || SLOT_1_8194AE)
###### End------WLAN_HAL relative configuration
config RTL_92C_SUPPORT
bool
default y if (SLOT_0_92C || SLOT_1_92C)
config RTL_92D_SUPPORT
bool
default y if (SLOT_0_92D || SLOT_1_92D)
config RTL_88E_SUPPORT
bool
select RTL_ODM_WLAN_DRIVER
default y if (SLOT_0_88E || SLOT_1_88E)
config RTL_8812_SUPPORT
bool
select RTL_ODM_WLAN_DRIVER
# select CONFIG_RTL_DUAL_92C_8812E
default y if (SLOT_0_8812 || SLOT_1_8812 || SLOT_0_8812AR_VN || SLOT_1_8812AR_VN )
config RTL_8812AR_VN_SUPPORT
bool
default y if ( SLOT_0_8812AR_VN || SLOT_1_8812AR_VN )
#
# General options
#
choice
prompt "8812 external PA type"
depends on ((SLOT_0_8812 && SLOT_0_EXT_PA) || (SLOT_1_8812 && SLOT_1_EXT_PA) || (SLOT_0_8812AR_VN && SLOT_0_EXT_PA) || (SLOT_1_8812AR_VN && SLOT_1_EXT_PA))
default PA_SKYWORKS_5022
config PA_SKYWORKS_5022
bool "Skyworks-5022"
config PA_RFMD_4501
bool "RFDM-4501 / Skywork-85703"
config PA_SKYWORKS_5023
bool "Skyworks-5023"
config PA_SKYWORKS_85712_HP
bool "Skyworks-85712 High Poewr"
endchoice
config PA_RTC5634
bool "Support 8812 Internal PA (RTC5634) and PAPE on"
depends on ((USE_PCIE_SLOT_0 && SLOT_0_8812 && !SLOT_0_EXT_PA) || (USE_PCIE_SLOT_1 && SLOT_1_8812 && !SLOT_1_EXT_PA))
default n
config RTL_AC2G_256QAM
bool "Support 256QAM (11AC mode) for Band 2.4G"
depends on (RTL_8812_SUPPORT && !RTL_8812AR_VN_SUPPORT) || RTL_8881A_SELECTIVE
default n
config RTL_8812_1T1R_SUPPORT
bool "Realtek 8812 1T1R mode"
depends on RTL_8812_SUPPORT
default n
config RTL_HOSTAPD_SUPPORT
bool "Realtek hostapd support"
depends on RTL8192CD
default n
#config HIGH_POWER_EXT_PA
# bool "Enable external high power PA"
# depends on RTL8192CD && !RTL_88E_SUPPORT
# default n
#config HIGH_POWER_EXT_LNA
# bool "Enable external LNA"
# depends on RTL8192CD && RTL_92C_SUPPORT
# default n
config ANT_SWITCH
bool "Enable 92c/92d Antenna Diversity"
depends on RTL8192CD &&!(RTL_88E_SUPPORT || WLAN_HAL_8881A || WLAN_HAL_8192EE || RTL_8812_SUPPORT)
default n
#config RTL_DUAL_PCIESLOT_BIWLAN
# bool "Enable both of the 2 pcie slot for bi-8192C support"
# depends on RTL8192CD && RTL_8198 && !RTL_92D_SUPPORT && !RTL_88E_SUPPORT && !RTL_8812_SUPPORT
# default n
#config RTL_92D_SUPPORT
# bool "Realtek 8192D wireless support "
# depends on RTL8192CD && !RTL_88E_SUPPORT && !RTL_8812_SUPPORT
# default n
#config PCIE_POWER_SAVING
# bool "Enable PCIE power saving support"
# depends on RTL8192CD && !RTL_88E_SUPPORT && !RTL_8812_SUPPORT
# default y if CONFIG_RTL8196C
#config RTL_92D_DMDP
# bool "RTL8192D dual-MAC-dual-PHY mode"
# depends on RTL8192CD && RTL_92D_SUPPORT && !RTL_DUAL_PCIESLOT_BIWLAN_D
# default y
config USB_POWER_BUS
bool "Use USB Power"
depends on RTL8192CD && RTL_92D_SUPPORT && !RTL_92C_SUPPORT
default n
config RTL_DFS_SUPPORT
bool "DFS Support"
depends on RTL8192CD && (RTL_92D_SUPPORT || RTL_8812_SUPPORT || WLAN_HAL_8881A || WLAN_HAL_8814AE)
default y
#config RTL_TX_EARLY_MODE_SUPPORT
# bool "Tx Early Mode Support"
# depends on RTL8192CD && RTL_92D_SUPPORT
# default n
#config RTL_DUAL_PCIESLOT_BIWLAN_D
# bool "Support Dual card:92C+92D"
# depends on RTL8192CD && !RTL_88E_SUPPORT && !RTL_8812_SUPPORT
# select RTL_92C_SUPPORT
# select RTL_92D_SUPPORT
# default n
#config RTL_DUAL_92C_8812E
# bool "Support Dual card:92C+8812E"
# depends on RTL8192CD
# select RTL_92C_SUPPORT
# select RTL_8812_SUPPORT
# default n
config RTL8190_PRIV_SKB
bool "Private skb buffer management"
depends on RTL8192CD
default y
config RTL_VAP_SUPPORT
bool "Virtual AP Support"
depends on RTL8192CD
default y
config RTL_CLIENT_MODE_SUPPORT
bool "Client Mode Support"
depends on RTL8192CD
default y
config RTL_REPEATER_MODE_SUPPORT
bool "Repeater Mode support"
depends on RTL8192CD && RTL_CLIENT_MODE_SUPPORT
default y
#not support multi-repeater also can use multi-clone,
#but now only 92E support per-entery set differenct CAM search,bo depend on 92E
config RTL_MULTI_CLONE_SUPPORT
bool "multiple clone support"
depends on RTL_CLIENT_MODE_SUPPORT && (WLAN_HAL_8192EE || WLAN_HAL_8814AE)
default n
config RTL_802_1X_CLIENT_SUPPORT
bool "Client Mode 802.1x Support"
depends on RTL8192CD && RTL_CLIENT_MODE_SUPPORT
default n
config RTL_SUPPORT_MULTI_PROFILE
bool "Multiple AP profile Support"
depends on RTL8192CD && RTL_CLIENT_MODE_SUPPORT
default y
config SUPPORT_CLIENT_MIXED_SECURITY
bool "Client mix security Support"
depends on RTL8192CD && RTL_CLIENT_MODE_SUPPORT
default n
config RTL_WDS_SUPPORT
bool "WDS Support"
depends on RTL8192CD
default y
config ENABLE_EFUSE
bool "Efuse Support"
depends on RTL8192CD
default n
config RTL_WAPI_SUPPORT
bool "WAPI Support"
depends on RTL8192CD
default n
config RTL_WAPI_LOCAL_AS_SUPPORT
bool "support local AS"
depends on RTL8192CD && RTL_WAPI_SUPPORT
default n
config RTL_COMAPI_CFGFILE
bool "Config File support"
depends on RTL8192CD
default n
config RTL_COMAPI_WLTOOLS
bool "Wireless Tools v29 support"
depends on RTL8192CD && !RTL_8812_SUPPORT
default n
#config WIRELESS_LAN_MODULE
# bool
# default y if RTL8192CD=m
config MP_PSD_SUPPORT
bool "MP quick PSD support"
depends on RTL8192CD && !RTL_88E_SUPPORT
default n
config RTL_P2P_SUPPORT
bool "Realtek P2P support "
depends on RTL8192CD || RTL8192E
default n
config RTL_WPS2_SUPPORT
bool "Realtek wps2.0 support "
depends on RTL8192CD
default y
config PHY_EAT_40MHZ
bool "HOST Clock Source, Select is 40MHz, otherwise 25MHz"
depends on RTL8192CD && !AUTO_PCIE_PHY_SCAN
default y
config PHY_WLAN_EAT_40MHZ
bool "Device Clock Source, Select is 40MHz, otherwise 25MHz"
depends on RTL8192CD && !AUTO_PCIE_PHY_SCAN
default y if (PHY_EAT_40MHZ)
config ANT_SWITCH
bool "Enable Antenna Diversity"
depends on RTL8192E
default n
config TXPWR_LMT
bool "Band Edge Limit support"
depends on RTL_92C_SUPPORT || RTL_92D_SUPPORT || RTL_8812_SUPPORT || RTL_88E_SUPPORT|| WLAN_HAL_8192EE || WLAN_HAL_8881A || WLAN_HAL_8814AE
default y
config RTL_TPT_THREAD
bool "Use kernel thread to process TX power tracking"
depends on RTL_ODM_WLAN_DRIVER
default n
config RTL_MESH_SUPPORT
bool "RTL Mesh Support"
depends on RTL8192CD
default n
#config RTL_MESH_AUTOPORTAL_SUPPORT
# bool "Support Auto-Poral"
# depends on RTL8192CD && !RTL_88E_SUPPORT && RTL_MESH_SUPPORT
# default n
# help
# This feature is enable Automation of enabling Portal
config RTL_MESH_CROSSBAND
bool "Support Cross-Band Access"
depends on RTL8192CD && RTL_MESH_SUPPORT && ((USE_PCIE_SLOT_0 && USE_PCIE_SLOT_1) || (RTL_8881A && USE_PCIE_SLOT_0) || RTL_92D_DMDP)
default n
help
This feature is to make 2.4GHz WiFi clients connect to 5GHz Mesh,
and 5GHz WiFI clients connect to 2.4GHZ Mesh. It is implemented
through GUEST_ZONE in bridge layer.
config RTL_WLAN_DOS_FILTER
bool "Enable WLAN DoS Filter"
depends on RTL8192CD && !RTL_88E_SUPPORT && !RTL_8812_SUPPORT
default n
config RTL_HS2_SUPPORT
bool "Realtek HS2.0 support "
default n
config PACP_SUPPORT
bool "Monitor mode support"
default n
config RTL_TDLS_SUPPORT
bool "TDLS Support"
default n
config RTL_SIMPLE_CONFIG
bool "Realtek Simple Config Support"
default n
config RTL_SIMPLE_CONFIG_USE_WPS_BUTTON
bool "Realtek Simple Config use the same HW PBC with WPS"
depends on RTL_SIMPLE_CONFIG && RTL_WPS2_SUPPORT
default n
config RTL_11W_SUPPORT
bool "IEEE 802.11W Support"
default y
config RTL_11W_CLI_SUPPORT
depends on RTL_11W_SUPPORT
bool "IEEE 802.11W Client Mode Support"
default n
##########################################################################
# Select WiFi Band on Wlan0
##########################################################################
#choice
# prompt "Select WiFi Band on Wlan0"
# depends on USE_PCIE_SLOT_0
# default BAND_2G_ON_WLAN0
#config BAND_2G_ON_WLAN0
# bool "Select 2.4g band on wlan0"
config BAND_5G_ON_WLAN0
# bool "Select 5g band on wlan0"
bool
default y
#endchoice
#config RTL_ODM_WLAN_DRIVER
# bool "Enable outsource dynamic mechanism driver"
# depends on RTL8192CD && (RTL_88E_SUPPORT || RTL_8812_SUPPORT)
# default y
#
# Hidden options
#
config WIRELESS_LAN_MODULE
bool
default y if RTL8192CD=m
config RTL_5G_SLOT_0
bool
config RTL_5G_SLOT_1
bool
config RTL_ODM_WLAN_DRIVER
bool
config RTL_WLAN_HAL_NOT_EXIST
bool
depends on (RTL_92C_SUPPORT || RTL_92D_SUPPORT || RTL_88E_SUPPORT || RTL_8812_SUPPORT)
default y
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Makefile
Executable
+582
View File
@@ -0,0 +1,582 @@
#
# drivers/net/rtl8192cd
#
# Makefile for the Linux Wireless network device drivers.
#
MODULE_NAME := rtl8192cd
ifndef RTK_WIFI_8192CD_ROOT
export RTK_WIFI_8192CD_ROOT=$(shell cd ../.. && pwd)
export RTK_WIFI_8192CD_SRC=$(shell pwd)
endif
PWD := $(RTK_WIFI_8192CD_SRC)
include $(PWD)/platform.mk
include $(PWD)/config.mk
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
RTL_WLAN_DATA_DIR := data
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
RTL_WLAN_DATA_DIR_D := data_92d
endif
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
RTL_WLAN_DATA_DIR_E := data_88e
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
RTL_WLAN_DATA_DIR_8812 := data_8812
endif
ifeq ($(CONFIG_WLAN_HAL),y)
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
RTL_WLAN_DATA_DIR_8814 := WlanHAL/Data/8814A
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
RTL_WLAN_DATA_DIR_92E := WlanHAL/Data/8192E
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V700),y)
RTL_WLAN_DATA_DIR := WlanHAL/Data/8881A/V700
endif
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B),y)
RTL_WLAN_DATA_DIR := WlanHAL/Data/8881A/V702B
endif
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B_Skyworth),y)
RTL_WLAN_DATA_DIR := WlanHAL/Data/8881A/V702B_Skyworth
endif
# ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B_MP),y)
# RTL_WLAN_DATA_DIR := WlanHAL/Data/8881A/V702B_MP
# endif
RTL_WLAN_DATA_DIR_8812 := WlanHAL/Data/8881A/V702B_MP
endif
endif
ifeq ($(CONFIG_RTL_MESH_SUPPORT),y)
EXTRA_CFLAGS += -DCONFIG_RTK_MESH #-DMESH_USE_METRICOP
# ifeq ($(CONFIG_11S_TEST_MODE),y)
# EXTRA_CFLAGS += -D_11s_TEST_MODE_
# endif
obj-mesh = ../mesh_ext/mesh_proc.o\
../mesh_ext/mesh_route.o\
../mesh_ext/mesh_rx.o\
../mesh_ext/mesh_sme.o\
../mesh_ext/mesh_security.o\
../mesh_ext/mesh_tx.o\
../mesh_ext/mesh_util.o\
../mesh_ext/mesh_11kv.o\
../mesh_ext/hash_table.o
endif
ifeq ($(CONFIG_USB_HCI),y)
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
MODULE_NAME := rtl8188eu
$(MODULE_NAME)-objs += \
usb/8188eu/8192cd_usb.o \
usb/8188eu/8192cd_usb_hw.o \
usb/8188eu/8192cd_usb_xmit.o \
usb/8188eu/8192cd_usb_recv.o \
usb/8188eu/8192cd_usb_cmd.o \
hal_intf_xmit.o
endif
endif
ifeq ($(CONFIG_SDIO_HCI),y)
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
MODULE_NAME := rtl8189es
$(MODULE_NAME)-objs += \
sdio/sdio_io.o \
sdio/8189es/8188e_sdio.o \
sdio/8189es/8188e_sdio_hw.o \
sdio/8189es/8188e_sdio_xmit.o \
sdio/8189es/8188e_sdio_recv.o \
sdio/8189es/8188e_sdio_cmd.o \
hal_intf_xmit.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
MODULE_NAME := rtl8192es
$(MODULE_NAME)-objs += \
sdio/sdio_io.o \
sdio/8192es/8192e_sdio.o \
sdio/8192es/8192e_sdio_hw.o \
sdio/8192es/8192e_sdio_xmit.o \
sdio/8192es/8192e_sdio_recv.o \
sdio/8192es/8192e_sdio_cmd.o \
hal_intf_xmit.o
ifeq ($(CONFIG_SDIO_HCI),y)
PATH_SUF := +SDIO
else
PATH_SUF :=
endif
ifeq ($(CONFIG_EXT_PA)$(CONFIG_EXT_LNA), yy)
EXT_PA_LNA_DATA := $(RTL_WLAN_DATA_DIR_92E)/GPA0+GLNA$(CONFIG_EXT_PA_LNA_TYPE)$(PATH_SUF)
endif
ifeq ($(CONFIG_EXT_PA)$(CONFIG_EXT_LNA), ny)
EXT_LNA_DATA := $(RTL_WLAN_DATA_DIR_92E)/GLNA$(CONFIG_EXT_LNA_TYPE)$(PATH_SUF)
endif
endif
endif
TARGET=$(MODULE_NAME).ko
SRCS_TXT = $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.txt))))
SRCS_BIN = $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.bin))))
SRCS_BIN_U = $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.BIN))))
TXPWR_HEADER =
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
TXPWR_LMT_TXT_92C = $(addprefix $(src)/data/,$(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/TXPWR*.txt)))
TXPWR_LMT_FNAME_92C = $(basename $(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/TXPWR*.txt)))
TXPWR_HEADER += $(obj)/TXPWR_92C.h
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
TXPWR_LMT_TXT_92D = $(addprefix $(src)/data_92d/,$(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/TXPWR*.txt)))
TXPWR_LMT_FNAME_92D = $(basename $(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/TXPWR*.txt)))
TXPWR_HEADER += $(obj)/TXPWR_92D.h
endif
obj-$(CONFIG_RTL8192CD) := $(MODULE_NAME).o
ifeq ($(CONFIG_PREALLOC_MODULE),y)
obj-m += rtw_prealloc.o
endif
ifeq ($(CONFIG_RTL_WAPI_SUPPORT),y)
$(MODULE_NAME)-objs += wapi_wai.o wapiCrypto.o wapiRandom.o
endif
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
$(MODULE_NAME)-objs += HalPwrSeqCmd.o\
Hal8188EPwrSeq.o\
8188e_hw.o
ifeq ($(CONFIG_POWER_SAVE),y)
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_T.o
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_S.o
else
ifneq ($(origin CONFIG_AP_PS), undefined)
ifeq ($(CONFIG_AP_PS),1)
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_OFFLOAD8.o
EXTRA_CFLAGS += -DSDIO_AP_OFFLOAD -DSOFTAP_PS_DURATION
endif
ifeq ($(CONFIG_AP_PS),2)
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_OFFLOAD8.o
EXTRA_CFLAGS += -DSDIO_AP_OFFLOAD
endif
ifeq ($(CONFIG_AP_PS),0)
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_T.o
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_S.o
endif
endif
endif
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
$(MODULE_NAME)-objs += \
OUTSRC/rtl8188e/HalHWImg8188E_BB.o\
OUTSRC/rtl8188e/HalHWImg8188E_MAC.o\
OUTSRC/rtl8188e/HalHWImg8188E_RF.o\
OUTSRC/rtl8188e/phydm_RegConfig8188E.o\
OUTSRC/rtl8188e/Hal8188ERateAdaptive.o\
OUTSRC/rtl8188e/phydm_RTL8188E.o\
OUTSRC/rtl8188e/HalPhyRf_8188e_AP.o
else
$(MODULE_NAME)-objs += Hal8192CDMOutSrc.o \
$(MODULE_NAME)-objs += RateAdaptive.o
endif
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
$(MODULE_NAME)-objs += HalPwrSeqCmd.o\
Hal8812PwrSeq.o\
8812_hw.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
$(MODULE_NAME)-objs += ./OUTSRC/rtl8812a/HalPhyRf_8812A_AP.o
endif
endif
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
$(MODULE_NAME)-objs += Hal8192CDMOutSrc.o
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
$(MODULE_NAME)-objs += Hal8192CDMOutSrc.o
endif
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
$(MODULE_NAME)-objs += \
OUTSRC/phydm.o \
OUTSRC/phydm_DIG.o\
OUTSRC/phydm_EdcaTurboCheck.o\
OUTSRC/phydm_AntDiv.o\
OUTSRC/phydm_DynamicBBPowerSaving.o\
OUTSRC/phydm_PathDiv.o\
OUTSRC/phydm_RaInfo.o\
OUTSRC/phydm_DynamicTxPower.o\
OUTSRC/phydm_PowerTracking_AP.o\
OUTSRC/PhyDM_Adaptivity.o\
OUTSRC/phydm_debug.o\
OUTSRC/phydm_interface.o\
OUTSRC/phydm_HWConfig.o\
OUTSRC/HalPhyRf_AP.o\
OUTSRC/phydm_CfoTracking.o\
OUTSRC/phydm_ACS.o\
EdcaTurboCheck.o
EXTRA_CFLAGS += -I$(src) -I$(src)/OUTSRC
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
$(MODULE_NAME)-objs += OUTSRC/rtl8821a/PhyDM_IQK_8821A_AP.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
$(MODULE_NAME)-objs += \
OUTSRC/rtl8192e/HalPhyRf_8192e_AP.o\
OUTSRC/rtl8192e/phydm_RTL8192E.o
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
$(MODULE_NAME)-objs += OUTSRC/rtl8814a/HalPhyRf_8814A_AP.o
$(MODULE_NAME)-objs += OUTSRC/rtl8814a/PhyDM_IQK_8814A.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
$(MODULE_NAME)-objs += \
OUTSRC/rtl8814a/HalHWImg8814A_BB.o\
OUTSRC/rtl8814a/HalHWImg8814A_MAC.o\
OUTSRC/rtl8814a/HalHWImg8814A_RF.o\
OUTSRC/rtl8814a/phydm_RegConfig8814A.o
endif
endif
$(MODULE_NAME)-objs +=\
8192cd_tx.o\
8192cd_rx.o\
8192cd_osdep.o\
8192cd_sme.o\
8192cd_util.o\
8192d_hw.o\
8192cd_hw.o\
8192cd_security.o\
8192cd_pwrctrl.o\
8192cd_tkip.o\
8192cd_aes.o\
8192cd_proc.o\
8192cd_br_ext.o\
8192cd_eeprom.o\
8192cd_mp.o\
8192cd_psk.o\
8192cd_ioctl.o\
1x_kmsm_aes.o\
1x_kmsm_hmac.o\
1x_md5c.o\
1x_rc4.o\
8192cd_mib.o\
8192cd_dmem.o\
8192cd_host.o\
8192cd_led.o\
8192cd_dfs.o\
8192cd_dfs_det.o\
8812_vht_gen.o\
romeperf.o\
HalDMOutSrc.o\
Beamforming.o\
8192cd_11h.o\
sha256.o\
$(obj-mesh)
ifeq ($(CONFIG_RTL_SIMPLE_CONFIG),y)
$(MODULE_NAME)-objs += 8192cd_profile.o
endif
ifeq ($(CONFIG_RTL_COMAPI_CFGFILE),y)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
ifeq ($(CONFIG_RTL_P2P_SUPPORT),y)
$(MODULE_NAME)-objs += 8192cd_p2p.o
endif
ifeq ($(CONFIG_RTL_COMAPI_WLTOOLS),y)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
ifeq ($(CONFIG_PACP_SUPPORT),y)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
ifeq ($(CONFIG_WPAS_CLI),1)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
#For Hostapd
ifeq ($(CONFIG_RTL_HOSTAPD_SUPPORT),y)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
ifeq ($(CONFIG_RTL8672),y)
$(MODULE_NAME)-objs += rtl8672_port.o
endif
$(MODULE_NAME)-objs += 8192cd_net80211.o
$(MODULE_NAME)-objs += 8192cd_psk_hapd.o
$(MODULE_NAME)-objs += 8192cd_cfg80211.o
ifeq ($(CONFIG_WLAN_HAL),y)
EXTRA_CFLAGS += -I$(src) -I$(src)/WlanHAL/ -I$(src)/WlanHAL/Include -I$(src)/WlanHAL/HalHeader
$(MODULE_NAME)-objs += WlanHAL/HalCommon.o \
WlanHAL/HalCfg.o \
WlanHAL/HalDbgCmd.o
endif
ifeq ($(CONFIG_WLAN_HAL_88XX),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/Hal88XXFirmware.o \
WlanHAL/RTL88XX/Hal88XXGen.o \
WlanHAL/RTL88XX/Hal88XXIsr.o \
WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.o \
WlanHAL/RTL88XX/Hal88XXRxDesc.o \
WlanHAL/RTL88XX/Hal88XXTxDesc.o \
WlanHAL/RTL88XX/Hal88XXPhyCfg.o
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8881A
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8881A/Hal8881AFirmware.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AGen.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AIsr.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.o \
8812_hw.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8192E/RTL8192EE -I$(src)/WlanHAL/RTL88XX/RTL8192E
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8192E/Hal8192EGen.o \
WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.o \
WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.o
ifeq ($(CONFIG_PCI_HCI), y)
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEGen.o
endif
ifeq ($(CONFIG_SDIO_HCI), y)
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8192E/RTL8192ES/Hal8192ESGen.o
ifneq ($(origin CONFIG_AP_PS), undefined)
ifeq ($(CONFIG_AP_PS),1)
EXTRA_CFLAGS += -DSDIO_AP_OFFLOAD -DSOFTAP_PS_DURATION
endif
ifeq ($(CONFIG_AP_PS),2)
EXTRA_CFLAGS += -DSDIO_AP_OFFLOAD
endif
endif
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8814A/RTL8814AE -I$(src)/WlanHAL/RTL88XX/RTL8814A
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEGen.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814AGen.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.o
endif
ifeq ($(CONFIG_WPA_NL80211),y)
EXTRA_CFLAGS += -I$(src)/nl80211
endif
ifeq ($(CONFIG_RTL8672),y)
EXTRA_CFLAGS += -DCONFIG_RTL8196B -DCONFIG_RTL8196C -DCONFIG_RTL8196B_GW -DCONFIG_RTL8196C_TESTCHIP_PATCH -D_MP_TELNET_SUPPORT_
EXTRA_CFLAGS += -DCONFIG_COMPAT_NET_DEV_OPS
endif
#CONFIG_SINUX_SUPPORT=1
ifeq ($(CONFIG_SINUX_SUPPORT),1)
EXTRA_CFLAGS += -DOPENSSL_FIPS -D__linux__ -DRSDK_BUILT -DOPENSSL_NO_SPEED -DOPENSSL_THREADS -D_REENTRANT \
-DDSO_DLFCN -DHAVE_DLFCN_H -DOPENSSL_NO_KRB5 -DB_ENDIAN -DTERMIO \
-fomit-frame-pointer
# -save-temps
$(MODULE_NAME)-objs += wps/ssl/mem.o wps/ssl/mem_clr.o wps/ssl/bn_add.o wps/ssl/bn_lib.o \
wps/ssl/bn_asm.o wps/ssl/bn_const.o wps/ssl/bn_ctx.o \
wps/ssl/bn_div.o wps/ssl/bn_exp.o wps/ssl/bn_gcd.o \
wps/ssl/bn_mod.o wps/ssl/bn_mont.o \
wps/ssl/bn_mul.o wps/ssl/bn_prime.o wps/ssl/bn_rand.o \
wps/ssl/bn_recp.o wps/ssl/bn_shift.o wps/ssl/bn_sqr.o \
wps/ssl/bn_word.o wps/ssl/dh_check.o wps/ssl/dh_gen.o \
wps/ssl/dh_key.o wps/ssl/dh_lib.o wps/ssl/digest.o \
wps/ssl/m_sha1.o wps/ssl/hmac.o wps/ssl/md_rand.o \
wps/ssl/rand_lib.o wps/ssl/sha1dgst.o wps/ssl/sha256.o \
wps/ssl/aes_cbc.o wps/ssl/fips_aes_core.o
#EXTRA_CFLAGS += -I../../../lib
$(MODULE_NAME)-objs += wps/8192cd_wscd.o
$(MODULE_NAME)-objs += wps/sercomm_intf.o
endif
ifneq ($(origin DIR_BOARD), undefined)
EXTRA_CFLAGS += -I$(DIR_BOARD)
#EXTRA_CFLAGS += -I$(DIR_BOARD) -Werror
#EXTRA_CFLAGS += -I$(DIR_LINUX)/drivers/net/rtl819x/
endif
###############################################################################
#EXTRA_CFLAGS += -D"KBUILD_MODNAME=KBUILD_STR(rtl8192cd)" -DMODULE -D__KERNEL__
.PHONY: all debug clean install install_dev install_target FORCE
all: $(TARGET)
$(TARGET): FORCE replace_parm
@echo '--- build the $(TARGET) module'
make ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(PWD) modules
$(CROSS_COMPILE)strip --strip-debug $(TARGET)
#cp $(TARGET) $(RTK_WIFI_LIB)/modules
#mv Module.symvers rtl8192cd.symvers
debug: EXTRA_CFLAGS +=-DDEBUG -g -O0
debug: all
replace_parm:
@if [ "$(CONFIG_WLAN_HAL_8192EE)" = "y" ]; then \
if [ "$(CONFIG_EXT_LNA)" = "y" ] && [ "$(CONFIG_EXT_PA)" = "y" ]; then\
echo "copy HP data from $(EXT_PA_LNA_DATA) to $(RTL_WLAN_DATA_DIR_92E)"; \
if [ "$(CONFIG_SDIO_HCI)" = "y" ]; then \
cp $(EXT_PA_LNA_DATA)/AGC_TAB.txt $(RTL_WLAN_DATA_DIR_92E)/AGC_TAB_8192ES_hp.txt; \
cp $(EXT_PA_LNA_DATA)/PHY_REG.txt $(RTL_WLAN_DATA_DIR_92E)/PHY_REG_8192ES_hp.txt; \
cp $(EXT_PA_LNA_DATA)/RadioA.txt $(RTL_WLAN_DATA_DIR_92E)/RadioA_8192ES_hp.txt; \
cp $(EXT_PA_LNA_DATA)/RadioB.txt $(RTL_WLAN_DATA_DIR_92E)/RadioB_8192ES_hp.txt; \
else \
cp $(EXT_PA_LNA_DATA)/AGC_TAB.txt $(RTL_WLAN_DATA_DIR_92E)/AGC_TAB_8192E_hp.txt; \
cp $(EXT_PA_LNA_DATA)/PHY_REG.txt $(RTL_WLAN_DATA_DIR_92E)/PHY_REG_8192E_hp.txt; \
cp $(EXT_PA_LNA_DATA)/RadioA.txt $(RTL_WLAN_DATA_DIR_92E)/RadioA_8192E_hp.txt; \
cp $(EXT_PA_LNA_DATA)/RadioB.txt $(RTL_WLAN_DATA_DIR_92E)/RadioB_8192E_hp.txt; \
fi \
elif [ "$(CONFIG_EXT_LNA)" = "y" ] && [ "$(CONFIG_EXT_PA)" = "n" ]; then \
echo "copy LNA data from $(EXT_LNA_DATA) to $(RTL_WLAN_DATA_DIR_92E)"; \
if [ "$(CONFIG_SDIO_HCI)" = "y" ]; then \
cp $(EXT_LNA_DATA)/AGC_TAB.txt $(RTL_WLAN_DATA_DIR_92E)/AGC_TAB_8192ES_extlna.txt; \
cp $(EXT_LNA_DATA)/PHY_REG.txt $(RTL_WLAN_DATA_DIR_92E)/PHY_REG_8192ES_extlna.txt; \
cp $(EXT_LNA_DATA)/RadioA.txt $(RTL_WLAN_DATA_DIR_92E)/RadioA_8192ES_extlna.txt; \
cp $(EXT_LNA_DATA)/RadioB.txt $(RTL_WLAN_DATA_DIR_92E)/RadioB_8192ES_extlna.txt; \
else \
cp $(EXT_LNA_DATA)/AGC_TAB.txt $(RTL_WLAN_DATA_DIR_92E)/AGC_TAB_8192E_extlna.txt; \
cp $(EXT_LNA_DATA)/PHY_REG.txt $(RTL_WLAN_DATA_DIR_92E)/PHY_REG_8192E_extlna; \
cp $(EXT_LNA_DATA)/RadioA.txt $(RTL_WLAN_DATA_DIR_92E)/RadioA_8192E_extlna.txt; \
cp $(EXT_LNA_DATA)/RadioB.txt $(RTL_WLAN_DATA_DIR_92E)/RadioB_8192E_extlna.txt; \
fi \
fi \
fi
clean:
# @if [ -e $(KSRC) ] ; then \
# make -C $(KSRC) M=$(PWD) MODFLAGS="$(EXTRA_CFLAGS)" clean; \
# fi
find . -name ".*.cmd" | xargs rm -f
rm -rf Module.symvers rtl8192cd.symvers
find . -name "*.o" | xargs rm -f
rm -f *.mod.c
rm -f modules.order
rm -f *.ko
rm -rf .tmp_versions
rm -f data_*.c
release_clean: clean
rm -rf usb/
rm -rf data/
rm -rf data_92d/
rm -rf data_8812/
rm -rf OUTSRC/rtl8812a
rm -rf OUTSRC/rtl8821a
rm -rf OUTSRC/rtl8814a
rm -rf WlanHAL/Data/8814A
rm -rf WlanHAL/Data/8881A
rm -rf WlanHAL/RTL88XX/RTL8192E/RTL8192EE
rm -rf WlanHAL/RTL88XX/RTL8814A
rm -rf WlanHAL/RTL88XX/RTL8881A
rm -f Hal8812*
rm -f Hal8821A*
rm -f wapi*
rm -f svn_mapping.xlsx
rm -f RateAdaptive.c
find ./ -name ".svn" | xargs rm -Rf
find ./OUTSRC -name "*_CE.[ch]" | xargs rm -Rf
find ./OUTSRC/ -name "*_WIN.[ch]" | xargs rm -Rf
install: install_dev install_target
install_dev:
install_target:
#mkdir -p $(FSROOT)/lib/modules
#cp -pd $(TARGET) $(FSROOT)/lib/modules
#mkdir -p $(BUILD_DEST)/kernel/module.symvers/
#cp -pd rtl8192cd.symvers $(BUILD_DEST)/kernel/module.symvers/rtl8192cd
#
#Build C code for TXT or BIN file
#
$(obj)/8192cd_hw.o : $(SRCS_TXT) $(SRCS_BIN) $(SRCS_BIN_U) $(TXPWR_HEADER)
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.txt FORCE
rm -f $(obj)/TXPWR_92C.h
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.txt FORCE
rm -f $(obj)/TXPWR_92D.h
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.txt FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.txt FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.txt FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.txt FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/TXPWR_92C.h: $(TXPWR_LMT_TXT_92C) FORCE
@echo $(TXPWR_LMT_FNAME_92C) > $(obj)/tmp_TXPWR
@perl -f $(obj)/tplmt2h.pl < $(obj)/tmp_TXPWR > $@
rm -f $(obj)/tmp_TXPWR
$(obj)/TXPWR_92D.h: $(TXPWR_LMT_TXT_92D) FORCE
@echo $(TXPWR_LMT_FNAME_92D) > $(obj)/tmp_TXPWR
@perl -f $(obj)/tplmt2h.pl < $(obj)/tmp_TXPWR > $@
rm -f $(obj)/tmp_TXPWR
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Makefile_formal
Executable
+582
View File
@@ -0,0 +1,582 @@
#
# drivers/net/rtl8192cd
#
# Makefile for the Linux Wireless network device drivers.
#
MODULE_NAME := rtl8192cd
ifndef RTK_WIFI_8192CD_ROOT
export RTK_WIFI_8192CD_ROOT=$(shell cd ../.. && pwd)
export RTK_WIFI_8192CD_SRC=$(shell pwd)
endif
PWD := $(RTK_WIFI_8192CD_SRC)
include $(PWD)/platform.mk
include $(PWD)/config.mk
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
RTL_WLAN_DATA_DIR := data
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
RTL_WLAN_DATA_DIR_D := data_92d
endif
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
RTL_WLAN_DATA_DIR_E := data_88e
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
RTL_WLAN_DATA_DIR_8812 := data_8812
endif
ifeq ($(CONFIG_WLAN_HAL),y)
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
RTL_WLAN_DATA_DIR_8814 := WlanHAL/Data/8814A
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
RTL_WLAN_DATA_DIR_92E := WlanHAL/Data/8192E
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V700),y)
RTL_WLAN_DATA_DIR := WlanHAL/Data/8881A/V700
endif
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B),y)
RTL_WLAN_DATA_DIR := WlanHAL/Data/8881A/V702B
endif
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B_Skyworth),y)
RTL_WLAN_DATA_DIR := WlanHAL/Data/8881A/V702B_Skyworth
endif
# ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B_MP),y)
# RTL_WLAN_DATA_DIR := WlanHAL/Data/8881A/V702B_MP
# endif
RTL_WLAN_DATA_DIR_8812 := WlanHAL/Data/8881A/V702B_MP
endif
endif
ifeq ($(CONFIG_RTL_MESH_SUPPORT),y)
EXTRA_CFLAGS += -DCONFIG_RTK_MESH #-DMESH_USE_METRICOP
# ifeq ($(CONFIG_11S_TEST_MODE),y)
# EXTRA_CFLAGS += -D_11s_TEST_MODE_
# endif
obj-mesh = ../mesh_ext/mesh_proc.o\
../mesh_ext/mesh_route.o\
../mesh_ext/mesh_rx.o\
../mesh_ext/mesh_sme.o\
../mesh_ext/mesh_security.o\
../mesh_ext/mesh_tx.o\
../mesh_ext/mesh_util.o\
../mesh_ext/mesh_11kv.o\
../mesh_ext/hash_table.o
endif
ifeq ($(CONFIG_USB_HCI),y)
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
MODULE_NAME := rtl8188eu
$(MODULE_NAME)-objs += \
usb/8188eu/8192cd_usb.o \
usb/8188eu/8192cd_usb_hw.o \
usb/8188eu/8192cd_usb_xmit.o \
usb/8188eu/8192cd_usb_recv.o \
usb/8188eu/8192cd_usb_cmd.o \
hal_intf_xmit.o
endif
endif
ifeq ($(CONFIG_SDIO_HCI),y)
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
MODULE_NAME := rtl8189es
$(MODULE_NAME)-objs += \
sdio/sdio_io.o \
sdio/8189es/8188e_sdio.o \
sdio/8189es/8188e_sdio_hw.o \
sdio/8189es/8188e_sdio_xmit.o \
sdio/8189es/8188e_sdio_recv.o \
sdio/8189es/8188e_sdio_cmd.o \
hal_intf_xmit.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
MODULE_NAME := rtl8192es
$(MODULE_NAME)-objs += \
sdio/sdio_io.o \
sdio/8192es/8192e_sdio.o \
sdio/8192es/8192e_sdio_hw.o \
sdio/8192es/8192e_sdio_xmit.o \
sdio/8192es/8192e_sdio_recv.o \
sdio/8192es/8192e_sdio_cmd.o \
hal_intf_xmit.o
ifeq ($(CONFIG_SDIO_HCI),y)
PATH_SUF := +SDIO
else
PATH_SUF :=
endif
ifeq ($(CONFIG_EXT_PA)$(CONFIG_EXT_LNA), yy)
EXT_PA_LNA_DATA := $(RTL_WLAN_DATA_DIR_92E)/GPA0+GLNA$(CONFIG_EXT_PA_LNA_TYPE)$(PATH_SUF)
endif
ifeq ($(CONFIG_EXT_PA)$(CONFIG_EXT_LNA), ny)
EXT_LNA_DATA := $(RTL_WLAN_DATA_DIR_92E)/GLNA$(CONFIG_EXT_LNA_TYPE)$(PATH_SUF)
endif
endif
endif
TARGET=$(MODULE_NAME).ko
SRCS_TXT = $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.txt))))
SRCS_BIN = $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.bin))))
SRCS_BIN_U = $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.BIN))))
TXPWR_HEADER =
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
TXPWR_LMT_TXT_92C = $(addprefix $(src)/data/,$(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/TXPWR*.txt)))
TXPWR_LMT_FNAME_92C = $(basename $(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/TXPWR*.txt)))
TXPWR_HEADER += $(obj)/TXPWR_92C.h
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
TXPWR_LMT_TXT_92D = $(addprefix $(src)/data_92d/,$(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/TXPWR*.txt)))
TXPWR_LMT_FNAME_92D = $(basename $(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/TXPWR*.txt)))
TXPWR_HEADER += $(obj)/TXPWR_92D.h
endif
obj-$(CONFIG_RTL8192CD) := $(MODULE_NAME).o
ifeq ($(CONFIG_PREALLOC_MODULE),y)
obj-m += rtw_prealloc.o
endif
ifeq ($(CONFIG_RTL_WAPI_SUPPORT),y)
$(MODULE_NAME)-objs += wapi_wai.o wapiCrypto.o wapiRandom.o
endif
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
$(MODULE_NAME)-objs += HalPwrSeqCmd.o\
Hal8188EPwrSeq.o\
8188e_hw.o
ifeq ($(CONFIG_POWER_SAVE),y)
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_T.o
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_S.o
else
ifneq ($(origin CONFIG_AP_PS), undefined)
ifeq ($(CONFIG_AP_PS),1)
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_OFFLOAD8.o
EXTRA_CFLAGS += -DSDIO_AP_OFFLOAD -DSOFTAP_PS_DURATION
endif
ifeq ($(CONFIG_AP_PS),2)
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_OFFLOAD8.o
EXTRA_CFLAGS += -DSDIO_AP_OFFLOAD
endif
ifeq ($(CONFIG_AP_PS),0)
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_T.o
$(MODULE_NAME)-objs += OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_S.o
endif
endif
endif
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
$(MODULE_NAME)-objs += \
OUTSRC/rtl8188e/HalHWImg8188E_BB.o\
OUTSRC/rtl8188e/HalHWImg8188E_MAC.o\
OUTSRC/rtl8188e/HalHWImg8188E_RF.o\
OUTSRC/rtl8188e/phydm_RegConfig8188E.o\
OUTSRC/rtl8188e/Hal8188ERateAdaptive.o\
OUTSRC/rtl8188e/phydm_RTL8188E.o\
OUTSRC/rtl8188e/HalPhyRf_8188e_AP.o
else
$(MODULE_NAME)-objs += Hal8192CDMOutSrc.o \
$(MODULE_NAME)-objs += RateAdaptive.o
endif
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
$(MODULE_NAME)-objs += HalPwrSeqCmd.o\
Hal8812PwrSeq.o\
8812_hw.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
$(MODULE_NAME)-objs += ./OUTSRC/rtl8812a/HalPhyRf_8812A_AP.o
endif
endif
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
$(MODULE_NAME)-objs += Hal8192CDMOutSrc.o
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
$(MODULE_NAME)-objs += Hal8192CDMOutSrc.o
endif
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
$(MODULE_NAME)-objs += \
OUTSRC/phydm.o \
OUTSRC/phydm_DIG.o\
OUTSRC/phydm_EdcaTurboCheck.o\
OUTSRC/phydm_AntDiv.o\
OUTSRC/phydm_DynamicBBPowerSaving.o\
OUTSRC/phydm_PathDiv.o\
OUTSRC/phydm_RaInfo.o\
OUTSRC/phydm_DynamicTxPower.o\
OUTSRC/phydm_PowerTracking_AP.o\
OUTSRC/PhyDM_Adaptivity.o\
OUTSRC/phydm_debug.o\
OUTSRC/phydm_interface.o\
OUTSRC/phydm_HWConfig.o\
OUTSRC/HalPhyRf_AP.o\
OUTSRC/phydm_CfoTracking.o\
OUTSRC/phydm_ACS.o\
EdcaTurboCheck.o
EXTRA_CFLAGS += -I$(src) -I$(src)/OUTSRC
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
$(MODULE_NAME)-objs += OUTSRC/rtl8821a/PhyDM_IQK_8821A_AP.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
$(MODULE_NAME)-objs += \
OUTSRC/rtl8192e/HalPhyRf_8192e_AP.o\
OUTSRC/rtl8192e/phydm_RTL8192E.o
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
$(MODULE_NAME)-objs += OUTSRC/rtl8814a/HalPhyRf_8814A_AP.o
$(MODULE_NAME)-objs += OUTSRC/rtl8814a/PhyDM_IQK_8814A.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
$(MODULE_NAME)-objs += \
OUTSRC/rtl8814a/HalHWImg8814A_BB.o\
OUTSRC/rtl8814a/HalHWImg8814A_MAC.o\
OUTSRC/rtl8814a/HalHWImg8814A_RF.o\
OUTSRC/rtl8814a/phydm_RegConfig8814A.o
endif
endif
$(MODULE_NAME)-objs +=\
8192cd_tx.o\
8192cd_rx.o\
8192cd_osdep.o\
8192cd_sme.o\
8192cd_util.o\
8192d_hw.o\
8192cd_hw.o\
8192cd_security.o\
8192cd_pwrctrl.o\
8192cd_tkip.o\
8192cd_aes.o\
8192cd_proc.o\
8192cd_br_ext.o\
8192cd_eeprom.o\
8192cd_mp.o\
8192cd_psk.o\
8192cd_ioctl.o\
1x_kmsm_aes.o\
1x_kmsm_hmac.o\
1x_md5c.o\
1x_rc4.o\
8192cd_mib.o\
8192cd_dmem.o\
8192cd_host.o\
8192cd_led.o\
8192cd_dfs.o\
8192cd_dfs_det.o\
8812_vht_gen.o\
romeperf.o\
HalDMOutSrc.o\
Beamforming.o\
8192cd_11h.o\
sha256.o\
$(obj-mesh)
ifeq ($(CONFIG_RTL_SIMPLE_CONFIG),y)
$(MODULE_NAME)-objs += 8192cd_profile.o
endif
ifeq ($(CONFIG_RTL_COMAPI_CFGFILE),y)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
ifeq ($(CONFIG_RTL_P2P_SUPPORT),y)
$(MODULE_NAME)-objs += 8192cd_p2p.o
endif
ifeq ($(CONFIG_RTL_COMAPI_WLTOOLS),y)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
ifeq ($(CONFIG_PACP_SUPPORT),y)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
ifeq ($(CONFIG_WPAS_CLI),1)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
#For Hostapd
ifeq ($(CONFIG_RTL_HOSTAPD_SUPPORT),y)
$(MODULE_NAME)-objs += 8192cd_comapi.o
endif
ifeq ($(CONFIG_RTL8672),y)
$(MODULE_NAME)-objs += rtl8672_port.o
endif
$(MODULE_NAME)-objs += 8192cd_net80211.o
$(MODULE_NAME)-objs += 8192cd_psk_hapd.o
$(MODULE_NAME)-objs += 8192cd_cfg80211.o
ifeq ($(CONFIG_WLAN_HAL),y)
EXTRA_CFLAGS += -I$(src) -I$(src)/WlanHAL/ -I$(src)/WlanHAL/Include -I$(src)/WlanHAL/HalHeader
$(MODULE_NAME)-objs += WlanHAL/HalCommon.o \
WlanHAL/HalCfg.o \
WlanHAL/HalDbgCmd.o
endif
ifeq ($(CONFIG_WLAN_HAL_88XX),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/Hal88XXFirmware.o \
WlanHAL/RTL88XX/Hal88XXGen.o \
WlanHAL/RTL88XX/Hal88XXIsr.o \
WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.o \
WlanHAL/RTL88XX/Hal88XXRxDesc.o \
WlanHAL/RTL88XX/Hal88XXTxDesc.o \
WlanHAL/RTL88XX/Hal88XXPhyCfg.o
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8881A
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8881A/Hal8881AFirmware.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AGen.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AIsr.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.o \
8812_hw.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8192E/RTL8192EE -I$(src)/WlanHAL/RTL88XX/RTL8192E
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8192E/Hal8192EGen.o \
WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.o \
WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.o
ifeq ($(CONFIG_PCI_HCI), y)
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEGen.o
endif
ifeq ($(CONFIG_SDIO_HCI), y)
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8192E/RTL8192ES/Hal8192ESGen.o
ifneq ($(origin CONFIG_AP_PS), undefined)
ifeq ($(CONFIG_AP_PS),1)
EXTRA_CFLAGS += -DSDIO_AP_OFFLOAD -DSOFTAP_PS_DURATION
endif
ifeq ($(CONFIG_AP_PS),2)
EXTRA_CFLAGS += -DSDIO_AP_OFFLOAD
endif
endif
endif
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8814A/RTL8814AE -I$(src)/WlanHAL/RTL88XX/RTL8814A
$(MODULE_NAME)-objs += WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEGen.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814AGen.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.o
endif
ifeq ($(CONFIG_WPA_NL80211),y)
EXTRA_CFLAGS += -I$(src)/nl80211
endif
ifeq ($(CONFIG_RTL8672),y)
EXTRA_CFLAGS += -DCONFIG_RTL8196B -DCONFIG_RTL8196C -DCONFIG_RTL8196B_GW -DCONFIG_RTL8196C_TESTCHIP_PATCH -D_MP_TELNET_SUPPORT_
EXTRA_CFLAGS += -DCONFIG_COMPAT_NET_DEV_OPS
endif
#CONFIG_SINUX_SUPPORT=1
ifeq ($(CONFIG_SINUX_SUPPORT),1)
EXTRA_CFLAGS += -DOPENSSL_FIPS -D__linux__ -DRSDK_BUILT -DOPENSSL_NO_SPEED -DOPENSSL_THREADS -D_REENTRANT \
-DDSO_DLFCN -DHAVE_DLFCN_H -DOPENSSL_NO_KRB5 -DB_ENDIAN -DTERMIO \
-fomit-frame-pointer
# -save-temps
$(MODULE_NAME)-objs += wps/ssl/mem.o wps/ssl/mem_clr.o wps/ssl/bn_add.o wps/ssl/bn_lib.o \
wps/ssl/bn_asm.o wps/ssl/bn_const.o wps/ssl/bn_ctx.o \
wps/ssl/bn_div.o wps/ssl/bn_exp.o wps/ssl/bn_gcd.o \
wps/ssl/bn_mod.o wps/ssl/bn_mont.o \
wps/ssl/bn_mul.o wps/ssl/bn_prime.o wps/ssl/bn_rand.o \
wps/ssl/bn_recp.o wps/ssl/bn_shift.o wps/ssl/bn_sqr.o \
wps/ssl/bn_word.o wps/ssl/dh_check.o wps/ssl/dh_gen.o \
wps/ssl/dh_key.o wps/ssl/dh_lib.o wps/ssl/digest.o \
wps/ssl/m_sha1.o wps/ssl/hmac.o wps/ssl/md_rand.o \
wps/ssl/rand_lib.o wps/ssl/sha1dgst.o wps/ssl/sha256.o \
wps/ssl/aes_cbc.o wps/ssl/fips_aes_core.o
#EXTRA_CFLAGS += -I../../../lib
$(MODULE_NAME)-objs += wps/8192cd_wscd.o
$(MODULE_NAME)-objs += wps/sercomm_intf.o
endif
ifneq ($(origin DIR_BOARD), undefined)
EXTRA_CFLAGS += -I$(DIR_BOARD)
#EXTRA_CFLAGS += -I$(DIR_BOARD) -Werror
#EXTRA_CFLAGS += -I$(DIR_LINUX)/drivers/net/rtl819x/
endif
###############################################################################
#EXTRA_CFLAGS += -D"KBUILD_MODNAME=KBUILD_STR(rtl8192cd)" -DMODULE -D__KERNEL__
.PHONY: all debug clean install install_dev install_target FORCE
all: $(TARGET)
$(TARGET): FORCE replace_parm
@echo '--- build the $(TARGET) module'
make ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(PWD) modules
$(CROSS_COMPILE)strip --strip-debug $(TARGET)
#cp $(TARGET) $(RTK_WIFI_LIB)/modules
#mv Module.symvers rtl8192cd.symvers
debug: EXTRA_CFLAGS +=-DDEBUG -g -O0
debug: all
replace_parm:
@if [ "$(CONFIG_WLAN_HAL_8192EE)" = "y" ]; then \
if [ "$(CONFIG_EXT_LNA)" = "y" ] && [ "$(CONFIG_EXT_PA)" = "y" ]; then\
echo "copy HP data from $(EXT_PA_LNA_DATA) to $(RTL_WLAN_DATA_DIR_92E)"; \
if [ "$(CONFIG_SDIO_HCI)" = "y" ]; then \
cp $(EXT_PA_LNA_DATA)/AGC_TAB.txt $(RTL_WLAN_DATA_DIR_92E)/AGC_TAB_8192ES_hp.txt; \
cp $(EXT_PA_LNA_DATA)/PHY_REG.txt $(RTL_WLAN_DATA_DIR_92E)/PHY_REG_8192ES_hp.txt; \
cp $(EXT_PA_LNA_DATA)/RadioA.txt $(RTL_WLAN_DATA_DIR_92E)/RadioA_8192ES_hp.txt; \
cp $(EXT_PA_LNA_DATA)/RadioB.txt $(RTL_WLAN_DATA_DIR_92E)/RadioB_8192ES_hp.txt; \
else \
cp $(EXT_PA_LNA_DATA)/AGC_TAB.txt $(RTL_WLAN_DATA_DIR_92E)/AGC_TAB_8192E_hp.txt; \
cp $(EXT_PA_LNA_DATA)/PHY_REG.txt $(RTL_WLAN_DATA_DIR_92E)/PHY_REG_8192E_hp.txt; \
cp $(EXT_PA_LNA_DATA)/RadioA.txt $(RTL_WLAN_DATA_DIR_92E)/RadioA_8192E_hp.txt; \
cp $(EXT_PA_LNA_DATA)/RadioB.txt $(RTL_WLAN_DATA_DIR_92E)/RadioB_8192E_hp.txt; \
fi \
elif [ "$(CONFIG_EXT_LNA)" = "y" ] && [ "$(CONFIG_EXT_PA)" = "n" ]; then \
echo "copy LNA data from $(EXT_LNA_DATA) to $(RTL_WLAN_DATA_DIR_92E)"; \
if [ "$(CONFIG_SDIO_HCI)" = "y" ]; then \
cp $(EXT_LNA_DATA)/AGC_TAB.txt $(RTL_WLAN_DATA_DIR_92E)/AGC_TAB_8192ES_extlna.txt; \
cp $(EXT_LNA_DATA)/PHY_REG.txt $(RTL_WLAN_DATA_DIR_92E)/PHY_REG_8192ES_extlna.txt; \
cp $(EXT_LNA_DATA)/RadioA.txt $(RTL_WLAN_DATA_DIR_92E)/RadioA_8192ES_extlna.txt; \
cp $(EXT_LNA_DATA)/RadioB.txt $(RTL_WLAN_DATA_DIR_92E)/RadioB_8192ES_extlna.txt; \
else \
cp $(EXT_LNA_DATA)/AGC_TAB.txt $(RTL_WLAN_DATA_DIR_92E)/AGC_TAB_8192E_extlna.txt; \
cp $(EXT_LNA_DATA)/PHY_REG.txt $(RTL_WLAN_DATA_DIR_92E)/PHY_REG_8192E_extlna; \
cp $(EXT_LNA_DATA)/RadioA.txt $(RTL_WLAN_DATA_DIR_92E)/RadioA_8192E_extlna.txt; \
cp $(EXT_LNA_DATA)/RadioB.txt $(RTL_WLAN_DATA_DIR_92E)/RadioB_8192E_extlna.txt; \
fi \
fi \
fi
clean:
# @if [ -e $(KSRC) ] ; then \
# make -C $(KSRC) M=$(PWD) MODFLAGS="$(EXTRA_CFLAGS)" clean; \
# fi
find . -name ".*.cmd" | xargs rm -f
rm -rf Module.symvers rtl8192cd.symvers
find . -name "*.o" | xargs rm -f
rm -f *.mod.c
rm -f modules.order
rm -f *.ko
rm -rf .tmp_versions
rm -f data_*.c
release_clean: clean
rm -rf usb/
rm -rf data/
rm -rf data_92d/
rm -rf data_8812/
rm -rf OUTSRC/rtl8812a
rm -rf OUTSRC/rtl8821a
rm -rf OUTSRC/rtl8814a
rm -rf WlanHAL/Data/8814A
rm -rf WlanHAL/Data/8881A
rm -rf WlanHAL/RTL88XX/RTL8192E/RTL8192EE
rm -rf WlanHAL/RTL88XX/RTL8814A
rm -rf WlanHAL/RTL88XX/RTL8881A
rm -f Hal8812*
rm -f Hal8821A*
rm -f wapi*
rm -f svn_mapping.xlsx
rm -f RateAdaptive.c
find ./ -name ".svn" | xargs rm -Rf
find ./OUTSRC -name "*_CE.[ch]" | xargs rm -Rf
find ./OUTSRC/ -name "*_WIN.[ch]" | xargs rm -Rf
install: install_dev install_target
install_dev:
install_target:
#mkdir -p $(FSROOT)/lib/modules
#cp -pd $(TARGET) $(FSROOT)/lib/modules
#mkdir -p $(BUILD_DEST)/kernel/module.symvers/
#cp -pd rtl8192cd.symvers $(BUILD_DEST)/kernel/module.symvers/rtl8192cd
#
#Build C code for TXT or BIN file
#
$(obj)/8192cd_hw.o : $(SRCS_TXT) $(SRCS_BIN) $(SRCS_BIN_U) $(TXPWR_HEADER)
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.txt FORCE
rm -f $(obj)/TXPWR_92C.h
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.txt FORCE
rm -f $(obj)/TXPWR_92D.h
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.txt FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.txt FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.txt FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.txt FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.bin FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.BIN FORCE
@perl -f $(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/TXPWR_92C.h: $(TXPWR_LMT_TXT_92C) FORCE
@echo $(TXPWR_LMT_FNAME_92C) > $(obj)/tmp_TXPWR
@perl -f $(obj)/tplmt2h.pl < $(obj)/tmp_TXPWR > $@
rm -f $(obj)/tmp_TXPWR
$(obj)/TXPWR_92D.h: $(TXPWR_LMT_TXT_92D) FORCE
@echo $(TXPWR_LMT_FNAME_92D) > $(obj)/tmp_TXPWR
@perl -f $(obj)/tplmt2h.pl < $(obj)/tmp_TXPWR > $@
rm -f $(obj)/tmp_TXPWR
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/Makefile_rtk
Executable
+392
View File
@@ -0,0 +1,392 @@
#
# drivers/net/rtl8192cd
#
# Makefile for the Linux Wireless network device drivers.
#
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
RTL_WLAN_DATA_DIR := data
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
RTL_WLAN_DATA_DIR_D := data_92d
endif
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
RTL_WLAN_DATA_DIR_E := data_88e
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
RTL_WLAN_DATA_DIR_8812 := data_8812
endif
ifeq ($(CONFIG_WLAN_HAL),y)
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
RTL_WLAN_DATA_DIR_8814 := WlanHAL/Data/8814A
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
RTL_WLAN_DATA_DIR_92E := WlanHAL/Data/8192E
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V700),y)
RTL_WLAN_DATA_DIR_8881A := WlanHAL/Data/8881A/V700
endif
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B),y)
RTL_WLAN_DATA_DIR_8881A := WlanHAL/Data/8881A/V702B
endif
ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B_Skyworth),y)
RTL_WLAN_DATA_DIR_8881A := WlanHAL/Data/8881A/V702B_Skyworth
endif
# ifeq ($(CONFIG_MAC_PHY_RF_Parameter_V702B_MP),y)
# RTL_WLAN_DATA_DIR_8881A := WlanHAL/Data/8881A/V702B_MP
# endif
RTL_WLAN_DATA_DIR_8812 := WlanHAL/Data/8881A/V702B_MP
endif
endif
ifeq ($(CONFIG_RTL_MESH_SUPPORT),y)
EXTRA_CFLAGS += -DCONFIG_RTK_MESH #-DMESH_USE_METRICOP
# ifeq ($(CONFIG_11S_TEST_MODE),y)
# EXTRA_CFLAGS += -D_11s_TEST_MODE_
# endif
obj-mesh = ../mesh_ext/mesh_proc.o\
../mesh_ext/mesh_route.o\
../mesh_ext/mesh_rx.o\
../mesh_ext/mesh_sme.o\
../mesh_ext/mesh_security.o\
../mesh_ext/mesh_tx.o\
../mesh_ext/mesh_util.o\
../mesh_ext/mesh_11kv.o\
../mesh_ext/hash_table.o
endif
SRCS_TXT = $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.txt))))
SRCS_BIN = $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.bin))))
SRCS_BIN_U = $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_E)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8812)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_92E)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8881A)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8881A)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8881A)/*.BIN))))
SRCS_TXT += $(addprefix $(src)/data_,$(notdir $(patsubst %.txt,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.txt))))
SRCS_BIN += $(addprefix $(src)/data_,$(notdir $(patsubst %.bin,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.bin))))
SRCS_BIN_U += $(addprefix $(src)/data_,$(notdir $(patsubst %.BIN,%.c,$(wildcard $(src)/$(RTL_WLAN_DATA_DIR_8814)/*.BIN))))
TXPWR_HEADER =
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
TXPWR_LMT_TXT_92C = $(addprefix $(src)/data/,$(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/TXPWR*.txt)))
TXPWR_LMT_FNAME_92C = $(basename $(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR)/TXPWR*.txt)))
TXPWR_HEADER += $(obj)/TXPWR_92C.h
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
TXPWR_LMT_TXT_92D = $(addprefix $(src)/data_92d/,$(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/TXPWR*.txt)))
TXPWR_LMT_FNAME_92D = $(basename $(notdir $(wildcard $(src)/$(RTL_WLAN_DATA_DIR_D)/TXPWR*.txt)))
TXPWR_HEADER += $(obj)/TXPWR_92D.h
endif
obj-$(CONFIG_RTL_WAPI_SUPPORT) += wapi_wai.o wapiCrypto.o wapiRandom.o
obj-$(CONFIG_RTL8192CD) += rtl8192cd.o
ifeq ($(CONFIG_RTL_88E_SUPPORT),y)
rtl8192cd-objs += HalPwrSeqCmd.o\
Hal8188EPwrSeq.o\
8188e_hw.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += \
OUTSRC/rtl8188e/HalHWImg8188E_BB.o\
OUTSRC/rtl8188e/HalHWImg8188E_MAC.o\
OUTSRC/rtl8188e/HalHWImg8188E_RF.o\
OUTSRC/rtl8188e/phydm_RegConfig8188E.o\
OUTSRC/rtl8188e/Hal8188ERateAdaptive.o\
OUTSRC/rtl8188e/phydm_RTL8188E.o\
OUTSRC/rtl8188e/HalPhyRf_8188e.o
else
rtl8192cd-objs += Hal8192CDMOutSrc.o \
rtl8192cd-objs += RateAdaptive.o
endif
endif
ifeq ($(CONFIG_RTL_8812_SUPPORT),y)
rtl8192cd-objs += HalPwrSeqCmd.o\
Hal8812PwrSeq.o\
8812_hw.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += ./OUTSRC/rtl8812a/HalPhyRf_8812A.o
# rtl8192cd-objs += ./OUTSRC/rtl8812a/HalPhyRf_8812A.o\
# OUTSRC/rtl8812a/HalHWImg8812A_BB.o\
# OUTSRC/rtl8812a/HalHWImg8812A_MAC.o\
# OUTSRC/rtl8812a/HalHWImg8812A_RF.o\
# OUTSRC/rtl8812a/odm_RegConfig8812A.o
endif
endif
ifeq ($(CONFIG_RTL_92C_SUPPORT),y)
rtl8192cd-objs += Hal8192CDMOutSrc.o
endif
ifeq ($(CONFIG_RTL_92D_SUPPORT),y)
rtl8192cd-objs += Hal8192CDMOutSrc.o
endif
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += \
OUTSRC/phydm.o \
OUTSRC/phydm_DIG.o\
OUTSRC/phydm_EdcaTurboCheck.o\
OUTSRC/phydm_AntDiv.o\
OUTSRC/phydm_DynamicBBPowerSaving.o\
OUTSRC/phydm_PathDiv.o\
OUTSRC/phydm_RaInfo.o\
OUTSRC/phydm_DynamicTxPower.o\
OUTSRC/phydm_PowerTracking.o\
OUTSRC/PhyDM_Adaptivity.o\
OUTSRC/phydm_debug.o\
OUTSRC/phydm_interface.o\
OUTSRC/phydm_HWConfig.o\
OUTSRC/HalPhyRf.o\
OUTSRC/phydm_CfoTracking.o\
OUTSRC/phydm_ACS.o\
EdcaTurboCheck.o
EXTRA_CFLAGS += -I$(src) -I$(src)/OUTSRC
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
rtl8192cd-objs += OUTSRC/rtl8821a/PhyDM_IQK_8821A.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
rtl8192cd-objs += \
OUTSRC/rtl8192e/HalPhyRf_8192e.o\
OUTSRC/rtl8192e/phydm_RTL8192E.o
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
rtl8192cd-objs += OUTSRC/rtl8814a/HalPhyRf_8814A.o
rtl8192cd-objs += OUTSRC/rtl8814a/PhyDM_IQK_8814A.o
ifeq ($(CONFIG_RTL_ODM_WLAN_DRIVER),y)
rtl8192cd-objs += \
OUTSRC/rtl8814a/HalHWImg8814A_BB.o\
OUTSRC/rtl8814a/HalHWImg8814A_MAC.o\
OUTSRC/rtl8814a/HalHWImg8814A_RF.o\
OUTSRC/rtl8814a/phydm_RegConfig8814A.o
endif
endif
rtl8192cd-objs +=\
8192cd_tx.o\
8192cd_rx.o\
8192cd_osdep.o\
8192cd_sme.o\
8192cd_util.o\
8192d_hw.o\
8192cd_hw.o\
8192cd_security.o\
8192cd_tkip.o\
8192cd_aes.o\
8192cd_proc.o\
8192cd_br_ext.o\
8192cd_eeprom.o\
8192cd_mp.o\
8192cd_psk.o\
8192cd_ioctl.o\
1x_kmsm_aes.o\
1x_kmsm_hmac.o\
1x_md5c.o\
1x_rc4.o\
8192cd_mib.o\
8192cd_dmem.o\
8192cd_host.o\
8192cd_led.o\
8192cd_dfs.o\
8192cd_dfs_det.o\
8812_vht_gen.o\
romeperf.o\
HalDMOutSrc.o\
Beamforming.o\
8192cd_11h.o\
$(obj-mesh)
ifeq ($(CONFIG_RTL_SIMPLE_CONFIG),y)
obj-y += 8192cd_profile.o
endif
ifeq ($(CONFIG_RTL_COMAPI_CFGFILE),y)
obj-y += 8192cd_comapi.o
endif
ifeq ($(CONFIG_RTL_P2P_SUPPORT),y)
obj-y += 8192cd_p2p.o
endif
ifeq ($(CONFIG_RTL_COMAPI_WLTOOLS),y)
obj-y += 8192cd_comapi.o
endif
ifeq ($(CONFIG_PACP_SUPPORT),y)
obj-y += 8192cd_comapi.o
endif
#For Hostapd
ifeq ($(CONFIG_RTL_HOSTAPD_SUPPORT),y)
obj-y += 8192cd_comapi.o
endif
ifeq ($(CONFIG_RTL8672),y)
obj-y += rtl8672_port.o
endif
rtl8192cd-objs += 8192cd_net80211.o
rtl8192cd-objs += 8192cd_psk_hapd.o
rtl8192cd-objs += 8192cd_cfg80211.o
ifeq ($(CONFIG_WLAN_HAL),y)
EXTRA_CFLAGS += -I$(src) -I$(src)/WlanHAL/ -I$(src)/WlanHAL/Include -I$(src)/WlanHAL/HalHeader
rtl8192cd-objs += WlanHAL/HalCommon.o \
WlanHAL/HalCfg.o \
WlanHAL/HalDbgCmd.o
endif
ifeq ($(CONFIG_WLAN_HAL_88XX),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX
rtl8192cd-objs += WlanHAL/RTL88XX/Hal88XXFirmware.o \
WlanHAL/RTL88XX/Hal88XXGen.o \
WlanHAL/RTL88XX/Hal88XXHWImg.o \
WlanHAL/RTL88XX/Hal88XXIsr.o \
WlanHAL/RTL88XX/Hal88XXPwrSeqCmd.o \
WlanHAL/RTL88XX/Hal88XXRxDesc.o \
WlanHAL/RTL88XX/Hal88XXTxDesc.o \
WlanHAL/RTL88XX/Hal88XXVerify.o \
WlanHAL/RTL88XX/Hal88XXPhyCfg.o \
WlanHAL/RTL88XX/Hal88XXDM.o
endif
ifeq ($(CONFIG_WLAN_HAL_8881A),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8881A
rtl8192cd-objs += WlanHAL/RTL88XX/RTL8881A/Hal8881AFirmware.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AGen.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AHWImg.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AIsr.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881APwrSeqCmd.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881ARxDesc.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881ATxDesc.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881AVerify.o \
WlanHAL/RTL88XX/RTL8881A/Hal8881APhyCfg.o \
8812_hw.o
endif
ifeq ($(CONFIG_WLAN_HAL_8192EE),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8192E/RTL8192EE -I$(src)/WlanHAL/RTL88XX/RTL8192E
rtl8192cd-objs += WlanHAL/RTL88XX/RTL8192E/RTL8192EE/Hal8192EEGen.o \
WlanHAL/RTL88XX/RTL8192E/Hal8192EGen.o \
WlanHAL/RTL88XX/RTL8192E/Hal8192EPhyCfg.o \
WlanHAL/RTL88XX/RTL8192E/Hal8192EPwrSeqCmd.o
endif
ifeq ($(CONFIG_WLAN_HAL_8814AE),y)
EXTRA_CFLAGS += -I$(src)/WlanHAL/RTL88XX/RTL8814A/RTL8814AE -I$(src)/WlanHAL/RTL88XX/RTL8814A
rtl8192cd-objs += WlanHAL/RTL88XX/RTL8814A/RTL8814AE/Hal8814AEGen.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814AGen.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814APhyCfg.o \
WlanHAL/RTL88XX/RTL8814A/Hal8814APwrSeqCmd.o
endif
ifeq ($(CONFIG_RTL8672),y)
EXTRA_CFLAGS += -DCONFIG_RTL8196B -DCONFIG_RTL8196C -DCONFIG_RTL8196B_GW -DCONFIG_RTL8196C_TESTCHIP_PATCH -D_MP_TELNET_SUPPORT_
ifeq ($(CONFIG_DEFAULTS_KERNEL_2_6),y)
EXTRA_CFLAGS += -DCONFIG_COMPAT_NET_DEV_OPS
endif
endif
#CONFIG_SINUX_SUPPORT=1
ifeq ($(CONFIG_SINUX_SUPPORT),1)
EXTRA_CFLAGS += -DOPENSSL_FIPS -D__linux__ -DRSDK_BUILT -DOPENSSL_NO_SPEED -DOPENSSL_THREADS -D_REENTRANT \
-DDSO_DLFCN -DHAVE_DLFCN_H -DOPENSSL_NO_KRB5 -DB_ENDIAN -DTERMIO \
-fomit-frame-pointer
# -save-temps
obj-y += wps/ssl/mem.o wps/ssl/mem_clr.o wps/ssl/bn_add.o wps/ssl/bn_lib.o \
wps/ssl/bn_asm.o wps/ssl/bn_const.o wps/ssl/bn_ctx.o \
wps/ssl/bn_div.o wps/ssl/bn_exp.o wps/ssl/bn_gcd.o \
wps/ssl/bn_mod.o wps/ssl/bn_mont.o \
wps/ssl/bn_mul.o wps/ssl/bn_prime.o wps/ssl/bn_rand.o \
wps/ssl/bn_recp.o wps/ssl/bn_shift.o wps/ssl/bn_sqr.o \
wps/ssl/bn_word.o wps/ssl/dh_check.o wps/ssl/dh_gen.o \
wps/ssl/dh_key.o wps/ssl/dh_lib.o wps/ssl/digest.o \
wps/ssl/m_sha1.o wps/ssl/hmac.o wps/ssl/md_rand.o \
wps/ssl/rand_lib.o wps/ssl/sha1dgst.o wps/ssl/sha256.o \
wps/ssl/aes_cbc.o wps/ssl/fips_aes_core.o
#EXTRA_CFLAGS += -I../../../lib
obj-y += wps/8192cd_wscd.o
obj-y += wps/sercomm_intf.o
endif
EXTRA_CFLAGS += -I$(DIR_BOARD) -D'SVN_REV="$(shell svnversion -n $(src))"'
#EXTRA_CFLAGS += -I$(DIR_BOARD) -Werror
#EXTRA_CFLAGS += -I$(DIR_LINUX)/drivers/net/rtl819x/
#
#Build C code for TXT or BIN file
#
$(obj)/8192cd_hw.o : $(SRCS_TXT) $(SRCS_BIN) $(SRCS_BIN_U) $(TXPWR_HEADER)
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.txt FORCE
rm -f $(obj)/TXPWR_92C.h
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.bin FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR)/%.BIN FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.txt FORCE
rm -f $(obj)/TXPWR_92D.h
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.bin FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_D)/%.BIN FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.txt FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.bin FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_E)/%.BIN FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.txt FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.bin FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8812)/%.BIN FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.txt FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.bin FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_92E)/%.BIN FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8881A)/%.txt FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8881A)/%.bin FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8881A)/%.BIN FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.txt FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.bin FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/data_%.c: $(src)/$(RTL_WLAN_DATA_DIR_8814)/%.BIN FORCE
$(obj)/bin2c.pl $(notdir $(basename $@)) < $< > $@
$(obj)/TXPWR_92C.h: $(TXPWR_LMT_TXT_92C) FORCE
@echo $(TXPWR_LMT_FNAME_92C) > $(obj)/tmp_TXPWR
$(obj)/tplmt2h.pl < $(obj)/tmp_TXPWR > $@
rm -f $(obj)/tmp_TXPWR
$(obj)/TXPWR_92D.h: $(TXPWR_LMT_TXT_92D) FORCE
@echo $(TXPWR_LMT_FNAME_92D) > $(obj)/tmp_TXPWR
$(obj)/tplmt2h.pl < $(obj)/tmp_TXPWR > $@
rm -f $(obj)/tmp_TXPWR
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/HalPhyRf_AP.c
Executable
+2504
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/HalPhyRf_AP.h
Executable
+162
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@@ -0,0 +1,162 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#include "phydm_PowerTracking_AP.h"
#if (RTL8814A_SUPPORT == 1)
#include "rtl8814a/PhyDM_IQK_8814A.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "rtl8822b/phydm_iqk_8822b.h"
#endif
typedef enum _PWRTRACK_CONTROL_METHOD {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE
} PWRTRACK_METHOD;
typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte);
typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte);
typedef VOID (*FuncLCK)(PVOID);
//refine by YuChen for 8814A
typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
typedef struct _TXPWRTRACK_CFG {
u1Byte SwingTableSize_CCK;
u1Byte SwingTableSize_OFDM;
u1Byte Threshold_IQK;
u1Byte Threshold_DPK;
u1Byte AverageThermalNum;
u1Byte RfPathCount;
u4Byte ThermalRegAddr;
FuncSetPwr ODM_TxPwrTrackSetPwr;
FuncIQK DoIQK;
FuncLCK PHY_LCCalibrate;
FuncSwing GetDeltaSwingTable;
FuncSwing8814only GetDeltaSwingTable8814only;
} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
VOID
ConfigureTxpowerTrack(
IN PVOID pDM_VOID,
OUT PTXPWRTRACK_CFG pConfig
);
VOID
ODM_TXPowerTrackingCallback_ThermalMeter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PVOID pDM_VOID
#else
IN PADAPTER Adapter
#endif
);
#if (RTL8192E_SUPPORT==1)
VOID
ODM_TXPowerTrackingCallback_ThermalMeter_92E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PVOID pDM_VOID
#else
IN PADAPTER Adapter
#endif
);
#endif
#if (RTL8814A_SUPPORT == 1)
VOID
ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PVOID pDM_VOID
#else
IN PADAPTER Adapter
#endif
);
#elif ODM_IC_11AC_SERIES_SUPPORT
VOID
ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PVOID pDM_VOID
#else
IN PADAPTER Adapter
#endif
);
#endif
#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M )
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1 //ms
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN BOOLEAN bEnableMonitorMode );
//
// IQ calibrate
//
void
PHY_IQCalibrate_8192C( IN PADAPTER pAdapter,
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8192C( IN PADAPTER pAdapter);
//
// AP calibrate
//
void
PHY_APCalibrate_8192C( IN PADAPTER pAdapter,
IN s1Byte delta);
#endif
#define ODM_TARGET_CHNL_NUM_2G_5G 59
VOID
ODM_ResetIQKResult(
IN PVOID pDM_VOID
);
u1Byte
ODM_GetRightChnlPlaceforIQK(
IN u1Byte chnl
);
void phydm_rf_init(IN PVOID pDM_VOID);
void phydm_rf_watchdog(IN PVOID pDM_VOID);
#endif // #ifndef __HAL_PHY_RF_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/Mp_Precomp.h
Executable
+20
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@@ -0,0 +1,20 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/PhyDM_Adaptivity.c
Executable
+941
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@@ -0,0 +1,941 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if WPP_SOFTWARE_TRACE
#include "PhyDM_Adaptivity.tmh"
#endif
#endif
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) {
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH));
} else
#endif
{
if (Adaptivity->DynamicLinkAdaptivity == TRUE) {
if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) {
Phydm_NHMCounterStatistics(pDM_Odm);
Phydm_CheckEnvironment(pDM_Odm);
} else if (!pDM_Odm->bLinked)
Adaptivity->bCheck = FALSE;
} else {
pDM_Odm->Adaptivity_enable = TRUE;
if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
}
}
} else {
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
BOOLEAN
Phydm_CheckChannelPlan(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
if (pMgntInfo->RegEnableAdaptivity == 2) {
if (pDM_Odm->Carrier_Sense_enable == FALSE) { /*check domain Code for Adaptivity or CarrierSense*/
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
} else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
} else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
}
} else {
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
}
else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
} else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
}
}
}
return FALSE;
}
#endif
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
/*PHY parameters initialize for n series*/
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/
ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/
}
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
/*PHY parameters initialize for ac series*/
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/
}
#endif
}
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
/*Get NHM report*/
Phydm_GetNHMCounterStatistics(pDM_Odm);
/*Reset NHM counter*/
Phydm_NHMCounterStatisticsReset(pDM_Odm);
}
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 = 0;
#if (RTL8195A_SUPPORT == 0)
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
#endif
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8);
}
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
}
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
}
#endif
}
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)L2H|(u1Byte)H2L<<16));
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)L2H|(u1Byte)H2L<<8));
#endif
}
VOID
Phydm_SetLNA(
IN PVOID pDM_VOID,
IN PhyDM_set_LNA type
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E)) {
if (type == PhyDM_disable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
}
} else if (type == PhyDM_enable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
}
}
} else if (pDM_Odm->SupportICType & ODM_RTL8723B) {
if (type == PhyDM_disable_LNA) {
/*S0*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
/*S1*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
} else if (type == PhyDM_enable_LNA) {
/*S0*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
/*S1*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
}
} else if (pDM_Odm->SupportICType & ODM_RTL8812) {
if (type == PhyDM_disable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
}
} else if (type == PhyDM_enable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
}
}
} else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) {
if (type == PhyDM_disable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
} else if (type == PhyDM_enable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
}
}
}
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
}
}
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
}
}
#endif
}
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (State == PhyDM_IGNORE_EDCCA) {
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); /*ignore EDCCA reg520[15]=1*/
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); /*reg524[11]=0*/
} else { /*don't set MAC ignore EDCCA signal*/
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0*/
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); /*reg524[11]=1 */
}
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State));
}
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u2Byte Base = 0;
Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;
if (Base != 0) {
pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;
pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;
}
if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)
return TRUE; /*clean environment*/
else
return FALSE; /*noisy environment*/
}
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
BOOLEAN isCleanEnvironment = FALSE;
if (Adaptivity->bFirstLink == TRUE) {
if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
Adaptivity->bFirstLink = FALSE;
return;
} else {
if (Adaptivity->NHMWait < 3) { /*Start enter NHM after 4 NHMWait*/
Adaptivity->NHMWait++;
Phydm_NHMCounterStatistics(pDM_Odm);
return;
} else {
Phydm_NHMCounterStatistics(pDM_Odm);
isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
if (isCleanEnvironment == TRUE) {
pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup; /*adaptivity mode*/
pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;
pDM_Odm->Adaptivity_enable = TRUE;
if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
} else {
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; /*mode2*/
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
pDM_Odm->adaptivity_flag = FALSE;
pDM_Odm->Adaptivity_enable = FALSE;
}
Adaptivity->NHMWait = 0;
Adaptivity->bFirstLink = TRUE;
Adaptivity->bCheck = TRUE;
}
}
}
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
u4Byte value32 = 0;
u1Byte cnt, IGI = 0x45; /*IGI = 0x50 for cal EDCCA lower bound*/
u1Byte txEdcca1 = 0, txEdcca0 = 0;
BOOLEAN bAdjust = TRUE;
s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
s1Byte Diff;
if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
Phydm_SetLNA(pDM_Odm, PhyDM_disable_LNA);
else {
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
}
Diff = IGI_target - (s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if (TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
ODM_delay_ms(5);
while (bAdjust) {
for (cnt = 0; cnt < 20; cnt++) {
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord);
#endif
if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E)))
txEdcca1 = txEdcca1 + 1;
else if (value32 & BIT29)
txEdcca1 = txEdcca1 + 1;
else
txEdcca0 = txEdcca0 + 1;
}
if (txEdcca1 > 1) {
IGI = IGI - 1;
TH_L2H_dmc = TH_L2H_dmc + 1;
if (TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
if (TH_L2H_dmc == 10) {
bAdjust = FALSE;
Adaptivity->H2L_lb = TH_H2L_dmc;
Adaptivity->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
txEdcca1 = 0;
txEdcca0 = 0;
} else {
bAdjust = FALSE;
Adaptivity->H2L_lb = TH_H2L_dmc;
Adaptivity->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
txEdcca1 = 0;
txEdcca0 = 0;
}
}
pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff;
Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff;
Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff;
if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
Phydm_SetLNA(pDM_Odm, PhyDM_enable_LNA);
else {
Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
}
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); /*resume to no link state*/
}
BOOLEAN
phydm_reSearchCondition(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
/*PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);*/
u1Byte Adaptivity_IGI_upper;
/*s1Byte TH_L2H_dmc, IGI_target = 0x32;*/
/*s1Byte Diff;*/
Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper + pDM_Odm->DCbackoff;
/*TH_L2H_dmc = 10;*/
/*Diff = TH_L2H_dmc - pDM_Odm->TH_L2H_ini;*/
/*lowest_IGI_upper = IGI_target - Diff;*/
/*if ((Adaptivity_IGI_upper - lowest_IGI_upper) <= 5)*/
if (Adaptivity_IGI_upper <= 0x26)
return TRUE;
else
return FALSE;
}
VOID
phydm_adaptivityInfoInit(
IN PVOID pDM_VOID,
IN PHYDM_ADAPINFO_E CmnInfo,
IN u4Byte Value
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
switch (CmnInfo) {
case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
pDM_Odm->Carrier_Sense_enable = (BOOLEAN)Value;
break;
case PHYDM_ADAPINFO_DCBACKOFF:
pDM_Odm->DCbackoff = (u1Byte)Value;
break;
case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)Value;
break;
case PHYDM_ADAPINFO_TH_L2H_INI:
pDM_Odm->TH_L2H_ini = (s1Byte)Value;
break;
case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
pDM_Odm->TH_EDCCA_HL_diff = (s1Byte)Value;
break;
case PHYDM_ADAPINFO_AP_NUM_TH:
Adaptivity->APNumTH = (u1Byte)Value;
break;
default:
break;
}
}
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
s1Byte IGItarget = 0x32;
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
if (pDM_Odm->Carrier_Sense_enable == FALSE) {
if (pDM_Odm->TH_L2H_ini == 0)
pDM_Odm->TH_L2H_ini = 0xf5;
} else
pDM_Odm->TH_L2H_ini = 0xa;
if (pDM_Odm->TH_EDCCA_HL_diff == 0)
pDM_Odm->TH_EDCCA_HL_diff = 7;
pDM_Odm->EDCCA_enable = TRUE; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
prtl8192cd_priv priv = pDM_Odm->priv;
if (pDM_Odm->Carrier_Sense_enable) {
pDM_Odm->TH_L2H_ini = 0xa;
pDM_Odm->TH_EDCCA_HL_diff = 7;
} else {
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_default; /*set by mib*/
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_default;
}
if (priv->pshare->rf_ft_var.adaptivity_enable == 2)
Adaptivity->DynamicLinkAdaptivity = TRUE;
else
Adaptivity->DynamicLinkAdaptivity = FALSE;
#endif
pDM_Odm->Adaptivity_IGI_upper = 0;
pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/
pDM_Odm->TH_L2H_ini_mode2 = 20;
pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;
Adaptivity->IGI_Base = 0x32;
Adaptivity->IGI_target = 0x1c;
Adaptivity->H2L_lb = 0;
Adaptivity->L2H_lb = 0;
Adaptivity->NHMWait = 0;
Adaptivity->bCheck = FALSE;
Adaptivity->bFirstLink = TRUE;
Adaptivity->AdajustIGILevel = 0;
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
/*Search pwdB lower bound*/
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
#endif
if (pDM_Odm->SupportICType & ODM_IC_11N_GAIN_IDX_EDCCA) {
/*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
}
#if (RTL8195A_SUPPORT == 0)
if (pDM_Odm->SupportICType & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/
/*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
}
if (!(pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
Phydm_SearchPwdBLowerBound(pDM_Odm);
if (phydm_reSearchCondition(pDM_Odm))
Phydm_SearchPwdBLowerBound(pDM_Odm);
}
#endif
/*we need to consider PwdB upper bound for 8814 later IC*/
Adaptivity->AdajustIGILevel = (u1Byte)((pDM_Odm->TH_L2H_ini + IGItarget) - PwdBUpperBound + DFIRloss); /*IGI = L2H - PwdB - DFIRloss*/
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x, Adaptivity->AdajustIGILevel = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, Adaptivity->AdajustIGILevel));
}
VOID
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
s1Byte TH_L2H_dmc, TH_H2L_dmc;
s1Byte Diff = 0, IGI_target;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER pAdapter = pDM_Odm->Adapter;
BOOLEAN bFwCurrentInPSMode = FALSE;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
/*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/
if (bFwCurrentInPSMode)
return;
#endif
if (pDM_Odm->EDCCA_enable == FALSE) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n"));
return;
}
if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n"));
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
else{
if (Phydm_CheckChannelPlan(pDM_Odm) || (pDM_Odm->APTotalNum > Adaptivity->APNumTH)) {
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
} else {
pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup;
pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;
}
}
#endif
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",
Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
#if (RTL8195A_SUPPORT == 0)
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
/*fix AC series when enable EDCCA hang issue*/
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/
}
#endif
if (*pDM_Odm->pBandWidth == ODM_BW20M) /*CHANNEL_WIDTH_20*/
IGI_target = Adaptivity->IGI_Base;
else if (*pDM_Odm->pBandWidth == ODM_BW40M)
IGI_target = Adaptivity->IGI_Base + 2;
#if (RTL8195A_SUPPORT == 0)
else if (*pDM_Odm->pBandWidth == ODM_BW80M)
IGI_target = Adaptivity->IGI_Base + 2;
#endif
else
IGI_target = Adaptivity->IGI_Base;
Adaptivity->IGI_target = (u1Byte) IGI_target;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d\n",
(*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity));
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, Adaptivity->AdajustIGILevel= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",
pDM_Odm->RSSI_Min, Adaptivity->AdajustIGILevel, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));
if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));
return;
}
if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
if ((Adaptivity->AdajustIGILevel > IGI) && (pDM_Odm->Adaptivity_enable == TRUE))
Diff = Adaptivity->AdajustIGILevel - IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
}
#if (RTL8195A_SUPPORT == 0)
else {
Diff = IGI_target - (s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if (TH_L2H_dmc > 10 && (pDM_Odm->Adaptivity_enable == TRUE))
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
if (TH_H2L_dmc < Adaptivity->H2L_lb)
TH_H2L_dmc = Adaptivity->H2L_lb;
if (TH_L2H_dmc < Adaptivity->L2H_lb)
TH_L2H_dmc = Adaptivity->L2H_lb;
}
#endif
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
return;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_AdaptivityBSOD(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
u1Byte count = 0;
u4Byte u4Value;
/*
1. turn off RF (TRX Mux in standby mode)
2. H2C mac id drop
3. ignore EDCCA
4. wait for clear FIFO
5. don't ignore EDCCA
6. turn on RF (TRX Mux in TRx mdoe)
7. H2C mac id resume
*/
RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));
pAdapter->dropPktByMacIdCnt++;
pMgntInfo->bDropPktInProgress = TRUE;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
#if 1
/*Standby mode*/
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
/*H2C mac id drop*/
MacIdIndicateDisconnect(pAdapter);
/*Ignore EDCCA*/
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
delay_ms(50);
count = 5;
#else
do {
u8Byte diffTime, curTime, oldestTime;
u1Byte queueIdx
//3 Standby mode
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
//3 H2C mac id drop
MacIdIndicateDisconnect(pAdapter);
//3 Ignore EDCCA
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
count++;
delay_ms(10);
// Check latest packet
curTime = PlatformGetCurrentTime();
oldestTime = 0xFFFFFFFFFFFFFFFF;
for (queueIdx = 0; queueIdx < MAX_TX_QUEUE; queueIdx++) {
if (!IS_DATA_QUEUE(queueIdx))
continue;
if (!pAdapter->bTcbBusyQEmpty[queueIdx]) {
RT_TRACE(COMP_MLME, DBG_WARNING, ("oldestTime = %llu\n", oldestTime));
RT_TRACE(COMP_MLME, DBG_WARNING, ("Q[%d] = %llu\n", queueIdx, pAdapter->firstTcbSysTime[queueIdx]));
if (pAdapter->firstTcbSysTime[queueIdx] < oldestTime)
oldestTime = pAdapter->firstTcbSysTime[queueIdx];
}
}
diffTime = curTime - oldestTime;
RT_TRACE(COMP_MLME, DBG_WARNING, ("diff s = %llu\n", (diffTime / 1000000)));
} while (((diffTime / 1000000) >= 4) && (oldestTime != 0xFFFFFFFFFFFFFFFF));
#endif
/*Resume EDCCA*/
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
/*Turn on TRx mode*/
Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
/*Resume H2C macid*/
MacIdRecoverMediaStatus(pAdapter);
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
pMgntInfo->bDropPktInProgress = FALSE;
RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/PhyDM_Adaptivity.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "9.1" /*20150812 by YuChen*/
#define PwdBUpperBound 7
#define DFIRloss 5
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
typedef enum _tag_PhyDM_REGULATION_Type {
REGULATION_FCC = 0,
REGULATION_MKK = 1,
REGULATION_ETSI = 2,
REGULATION_WW = 3,
MAX_REGULATION_NUM = 4
} PhyDM_REGULATION_TYPE;
#endif
typedef enum _PHYDM_ADAPTIVITY_Info_Definition {
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
PHYDM_ADAPINFO_DCBACKOFF,
PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
PHYDM_ADAPINFO_TH_L2H_INI,
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
PHYDM_ADAPINFO_AP_NUM_TH
} PHYDM_ADAPINFO_E;
typedef enum tag_PhyDM_set_LNA {
PhyDM_disable_LNA = 0,
PhyDM_enable_LNA = 1,
} PhyDM_set_LNA;
typedef enum tag_PhyDM_TRx_MUX_Type
{
PhyDM_SHUTDOWN = 0,
PhyDM_STANDBY_MODE = 1,
PhyDM_TX_MODE = 2,
PhyDM_RX_MODE = 3
}PhyDM_Trx_MUX_Type;
typedef enum tag_PhyDM_MACEDCCA_Type
{
PhyDM_IGNORE_EDCCA = 0,
PhyDM_DONT_IGNORE_EDCCA = 1
}PhyDM_MACEDCCA_Type;
typedef struct _ADAPTIVITY_STATISTICS {
s1Byte TH_L2H_ini_backup;
s1Byte TH_EDCCA_HL_diff_backup;
s1Byte IGI_Base;
u1Byte IGI_target;
u1Byte NHMWait;
s1Byte H2L_lb;
s1Byte L2H_lb;
BOOLEAN bFirstLink;
BOOLEAN bCheck;
BOOLEAN DynamicLinkAdaptivity;
u1Byte APNumTH;
u1Byte AdajustIGILevel;
} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS;
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
);
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
);
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
);
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
);
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
);
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
);
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
);
VOID
phydm_adaptivityInfoInit(
IN PVOID pDM_VOID,
IN PHYDM_ADAPINFO_E CmnInfo,
IN u4Byte Value
);
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
);
VOID
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_DisableEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_DynamicEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_AdaptivityBSOD(
IN PVOID pDM_VOID
);
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm.h
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_ACS.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_ACS.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#define ACS_VERSION "1.1" /*20150729 by YuChen*/
#define CLM_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
// For phydm_AutoChannelSelectSettingAP()
#define STORE_DEFAULT_NHM_SETTING 0
#define RESTORE_DEFAULT_NHM_SETTING 1
#define ACS_NHM_SETTING 2
typedef struct _ACS_
{
BOOLEAN bForceACSResult;
u1Byte CleanChannel_2G;
u1Byte CleanChannel_5G;
u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];
#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
u1Byte ACS_Step;
// NHM Count 0-11
u1Byte NHM_Cnt[14][11];
// AC-Series, for storing previous setting
u4Byte Reg0x990;
u4Byte Reg0x994;
u4Byte Reg0x998;
u4Byte Reg0x99C;
u1Byte Reg0x9A0; // u1Byte
// N-Series, for storing previous setting
u4Byte Reg0x890;
u4Byte Reg0x894;
u4Byte Reg0x898;
u4Byte Reg0x89C;
u1Byte Reg0xE28; // u1Byte
#endif
}ACS, *PACS;
VOID
odm_AutoChannelSelectInit(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelectReset(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelect(
IN PVOID pDM_VOID,
IN u1Byte Channel
);
u1Byte
ODM_GetAutoChannelSelectResult(
IN PVOID pDM_VOID,
IN u1Byte Band
);
#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
VOID
phydm_AutoChannelSelectSettingAP(
IN PVOID pDM_VOID,
IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING
IN u4Byte acs_step
);
VOID
phydm_GetNHMStatisticsAP(
IN PVOID pDM_VOID,
IN u4Byte idx, // @ 2G, Real channel number = idx+1
IN u4Byte acs_step
);
#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
VOID
phydm_CLMInit(
IN PVOID pDM_VOID,
IN u2Byte sampleNum
);
VOID
phydm_CLMtrigger(
IN PVOID pDM_VOID
);
BOOLEAN
phydm_checkCLMready(
IN PVOID pDM_VOID
);
u2Byte
phydm_getCLMresult(
IN PVOID pDM_VOID
);
#endif //#ifndef __PHYDMACS_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_AntDect.c
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
#if(defined(CONFIG_ANT_DETECTION))
//IS_ANT_DETECT_SUPPORT_SINGLE_TONE(Adapter)
//IS_ANT_DETECT_SUPPORT_RSSI(Adapter)
//IS_ANT_DETECT_SUPPORT_PSD(Adapter)
//1 [1. Single Tone Method] ===================================================
//
// Description:
// Set Single/Dual Antenna default setting for products that do not do detection in advance.
//
// Added by Joseph, 2012.03.22
//
VOID
ODM_SingleDualAntennaDefaultSetting(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
PADAPTER pAdapter = pDM_Odm->Adapter;
u1Byte btAntNum=BT_GetPgAntNum(pAdapter);
// Set default antenna A and B status
if(btAntNum == 2)
{
pDM_SWAT_Table->ANTA_ON=TRUE;
pDM_SWAT_Table->ANTB_ON=TRUE;
}
else if(btAntNum == 1)
{// Set antenna A as default
pDM_SWAT_Table->ANTA_ON=TRUE;
pDM_SWAT_Table->ANTB_ON=FALSE;
}
else
{
RT_ASSERT(FALSE, ("Incorrect antenna number!!\n"));
}
}
//2 8723A ANT DETECT
//
// Description:
// Implement IQK single tone for RF DPK loopback and BB PSD scanning.
// This function is cooperated with BB team Neil.
//
// Added by Roger, 2011.12.15
//
BOOLEAN
ODM_SingleDualAntennaDetection(
IN PVOID pDM_VOID,
IN u1Byte mode
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte CurrentChannel,RfLoopReg;
u1Byte n;
u4Byte Reg88c, Regc08, Reg874, Regc50, Reg948, Regb2c, Reg92c, Reg930, Reg064, AFE_rRx_Wait_CCA;
u1Byte initial_gain = 0x5a;
u4Byte PSD_report_tmp;
u4Byte AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
BOOLEAN bResult = TRUE;
u4Byte AFE_Backup[16];
u4Byte AFE_REG_8723A[16] = {
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN,
rFPGA0_XCD_SwitchControl, rBlue_Tooth};
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============>\n"));
if (!(pDM_Odm->SupportICType & ODM_RTL8723B))
return bResult;
// Retrieve antenna detection registry info, added by Roger, 2012.11.27.
if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter))
return bResult;
//1 Backup Current RF/BB Settings
CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
Reg92c = ODM_GetBBReg(pDM_Odm, rDPDT_control, bMaskDWord);
Reg930 = ODM_GetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord);
Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord);
Reg064 = ODM_GetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29);
ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1);
ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77);
ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, 0x1); //dbg 7
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3c0, 0x0);//dbg 8
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x0);
}
ODM_StallExecution(10);
//Store A Path Register 88c, c08, 874, c50
Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
// Store AFE Registers
if (pDM_Odm->SupportICType & ODM_RTL8723B)
AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord);
//Set PSD 128 pts
ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts
// To SET CH1 to do
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401); //Channel 1
// AFE all on step
if (pDM_Odm->SupportICType & ODM_RTL8723B)
ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016);
// 3 wire Disable
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
//BB IQK Setting
ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
//IQK setting tone@ 4.34Mhz
ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
//Page B init
ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150016);
ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150016);
}
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7f, initial_gain);
//IQK Single tone start
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000);
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
ODM_StallExecution(10000);
// PSD report of antenna A
PSD_report_tmp=0x0;
for (n=0;n<2;n++)
{
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
if(PSD_report_tmp >AntA_report)
AntA_report=PSD_report_tmp;
}
// change to Antenna B
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
//ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2);
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280);
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1);
}
ODM_StallExecution(10);
// PSD report of antenna B
PSD_report_tmp=0x0;
for (n=0;n<2;n++)
{
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
if(PSD_report_tmp > AntB_report)
AntB_report=PSD_report_tmp;
}
//Close IQK Single Tone function
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
//1 Return to antanna A
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
// external DPDT
ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c);
//internal S0/S1
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c);
ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord, Reg930);
ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, Reg064);
}
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg);
//Reload AFE Registers
if (pDM_Odm->SupportICType & ODM_RTL8723B)
ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA);
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report));
//2 Test Ant B based on Ant A is ON
if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 135) && (AntB_report <= 135))
{
u1Byte TH1=2, TH2=6;
if((AntA_report - AntB_report < TH1) || (AntB_report - AntA_report < TH1))
{
pDM_SWAT_Table->ANTA_ON=TRUE;
pDM_SWAT_Table->ANTB_ON=TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
}
else if(((AntA_report - AntB_report >= TH1) && (AntA_report - AntB_report <= TH2)) ||
((AntB_report - AntA_report >= TH1) && (AntB_report - AntA_report <= TH2)))
{
pDM_SWAT_Table->ANTA_ON=FALSE;
pDM_SWAT_Table->ANTB_ON=FALSE;
bResult = FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
}
else
{
pDM_SWAT_Table->ANTA_ON = TRUE;
pDM_SWAT_Table->ANTB_ON=FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna\n"));
}
pDM_Odm->AntDetectedInfo.bAntDetected= TRUE;
pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report;
pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report;
pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report;
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n"));
bResult = FALSE;
}
}
return bResult;
}
//1 [2. Scan AP RSSI Method] ==================================================
BOOLEAN
ODM_SwAntDivCheckBeforeLink(
IN PVOID pDM_VOID
)
{
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
s1Byte Score = 0;
PRT_WLAN_BSS pTmpBssDesc, pTestBssDesc;
u1Byte power_target = 10, power_target_L = 9, power_target_H = 16;
u1Byte tmp_power_diff = 0,power_diff = 0,avg_power_diff = 0,max_power_diff = 0,min_power_diff = 0xff;
u2Byte index, counter = 0;
static u1Byte ScanChannel;
u8Byte tStamp_diff = 0;
u4Byte tmp_SWAS_NoLink_BK_Reg948;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d )) \n",pDM_Odm->DM_SWAT_Table.ANTA_ON ,pDM_Odm->DM_SWAT_Table.ANTB_ON ));
//if(HP id)
{
if(pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult==TRUE && pDM_Odm->SupportICType == ODM_RTL8723B)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n"));
return FALSE;
}
if(pDM_Odm->SupportICType == ODM_RTL8723B)
{
if(pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 == 0xff)
pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch );
}
}
if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413
{ // The ODM structure is not initialized.
return FALSE;
}
// Retrieve antenna detection registry info, added by Roger, 2012.11.27.
if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter))
{
return FALSE;
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI Method\n"));
}
// Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
{
PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState));
pDM_SWAT_Table->SWAS_NoLink_State = 0;
return FALSE;
}
else
{
PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State));
//1 Run AntDiv mechanism "Before Link" part.
if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
{
//1 Prepare to do Scan again to check current antenna state.
// Set check state to next step.
pDM_SWAT_Table->SWAS_NoLink_State = 1;
// Copy Current Scan list.
pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc;
PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
// Go back to scan function again.
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n"));
pMgntInfo->ScanStep=0;
pMgntInfo->bScanAntDetect = TRUE;
ScanChannel = odm_SwAntDivSelectScanChnl(Adapter);
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
{
if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
else
ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
if(ScanChannel == 0)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
{
pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
else
{
pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
return FALSE;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")));
} else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) {
/*Switch Antenna to another one.*/
tmp_SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch);
if ((pDM_SWAT_Table->CurAntenna == MAIN_ANT) && (tmp_SWAS_NoLink_BK_Reg948 == 0x200)) {
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280);
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1);
pDM_SWAT_Table->CurAntenna = AUX_ANT;
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_SWAS_NoLink_BK_Reg948));
return FALSE;
}
ODM_StallExecution(10);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to (( %s-ant)) for testing.\n", (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?"MAIN":"AUX"));
}
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
return TRUE;
}
else //pDM_SWAT_Table->SWAS_NoLink_State == 1
{
//1 ScanComple() is called after antenna swiched.
//1 Check scan result and determine which antenna is going
//1 to be used.
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" tmpNumBssDesc= (( %d )) \n",pMgntInfo->tmpNumBssDesc));// debug for Dino
for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++)
{
pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1
pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2
if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n"));
continue;
}
if(pDM_Odm->SupportICType != ODM_RTL8723B)
{
if(pTmpBssDesc->ChannelNumber == ScanChannel)
{
if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n"));
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
Score++;
PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
}
else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n"));
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
Score--;
}
else
{
if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000)
{
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n"));
}
}
}
}
else // 8723B
{
if(pTmpBssDesc->ChannelNumber == ScanChannel)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ChannelNumber == ScanChannel -> (( %d )) \n", pTmpBssDesc->ChannelNumber ));
if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) // Pow(Ant1) > Pow(Ant2)
{
counter++;
tmp_power_diff=(u1Byte)(pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower);
power_diff = power_diff + tmp_power_diff;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d)) \n", tmp_power_diff,max_power_diff,min_power_diff));
if(tmp_power_diff > max_power_diff)
max_power_diff=tmp_power_diff;
if(tmp_power_diff < min_power_diff)
min_power_diff=tmp_power_diff;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d)) \n",max_power_diff,min_power_diff));
PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
}
else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower) // Pow(Ant1) < Pow(Ant2)
{
counter++;
tmp_power_diff=(u1Byte)(pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower);
power_diff = power_diff + tmp_power_diff;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
if(tmp_power_diff > max_power_diff)
max_power_diff=tmp_power_diff;
if(tmp_power_diff < min_power_diff)
min_power_diff=tmp_power_diff;
}
else // Pow(Ant1) = Pow(Ant2)
{
if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp) // Stamp(Ant1) < Stamp(Ant2)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000)
{
counter++;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
min_power_diff = 0;
}
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
}
}
}
}
}
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
{
if(pMgntInfo->NumBssDesc!=0 && Score<0)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
else
ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
}
if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
{
pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
else
{
pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
}
else if(pDM_Odm->SupportICType == ODM_RTL8723B)
{
if(counter == 0)
{
if(pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec == FALSE)
{
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = TRUE;
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again \n"));
//3 [ Scan again ]
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
return TRUE;
}
else// Pre_Aux_FailDetec == TRUE
{
//2 [ Single Antenna ]
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE;
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Still cannot find any AP ]] \n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
}
pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter++;
}
else
{
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE;
if(counter==3)
{
avg_power_diff = ((power_diff-max_power_diff - min_power_diff)>>1)+ ((max_power_diff + min_power_diff)>>2);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff));
}
else if(counter>=4)
{
avg_power_diff=(power_diff-max_power_diff - min_power_diff) / (counter - 2);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff));
}
else//counter==1,2
{
avg_power_diff=power_diff/counter;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d )) \n", avg_power_diff,counter, power_diff));
}
//2 [ Retry ]
if( (avg_power_diff >=power_target_L) && (avg_power_diff <=power_target_H) )
{
pDM_Odm->DM_SWAT_Table.Retry_Counter++;
if(pDM_Odm->DM_SWAT_Table.Retry_Counter<=3)
{
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]] \n", avg_power_diff));
//3 [ Scan again ]
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
return TRUE;
}
else
{
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( Retry_Counter > 3 )) \n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
}
}
//2 [ Dual Antenna ]
else if( (pMgntInfo->NumBssDesc != 0) && (avg_power_diff < power_target_L) )
{
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
{
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter++;
// set bt coexDM from 1ant coexDM to 2ant coexDM
BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
//3 [ Init antenna diversity ]
pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
ODM_AntDivInit(pDM_Odm);
}
//2 [ Single Antenna ]
else if(avg_power_diff > power_target_H)
{
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
{
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
//BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1);
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
pDM_Odm->DM_SWAT_Table.Single_Ant_Counter++;
}
}
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bResult=(( %d ))\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Dual_Ant_Counter = (( %d )), Single_Ant_Counter = (( %d )) , Retry_Counter = (( %d )) , Aux_FailDetec_Counter = (( %d ))\n\n\n",
pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter,pDM_Odm->DM_SWAT_Table.Single_Ant_Counter,pDM_Odm->DM_SWAT_Table.Retry_Counter,pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter));
//2 recover the antenna setting
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, (pDM_SWAT_Table->SWAS_NoLink_BK_Reg948));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bResult=(( %d )), Recover Reg[948]= (( %x )) \n\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult, pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 ));
}
// Check state reset to default and wait for next time.
pDM_SWAT_Table->SWAS_NoLink_State = 0;
pMgntInfo->bScanAntDetect = FALSE;
return FALSE;
}
#else
return FALSE;
#endif
return FALSE;
}
//1 [3. PSD Method] ==========================================================
u4Byte
odm_GetPSDData(
IN PVOID pDM_VOID,
IN u2Byte point,
IN u1Byte initial_gain)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte psd_report;
ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); //Start PSD calculation, Reg808[22]=0->1
ODM_StallExecution(150);//Wait for HW PSD report
ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);//Stop PSD calculation, Reg808[22]=1->0
psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;//Read PSD report, Reg8B4[15:0]
psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report));//+(u4Byte)(initial_gain);
return psd_report;
}
VOID
ODM_SingleDualAntennaDetection_PSD(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte Channel_ori;
u1Byte initial_gain = 0x36;
u1Byte tone_idx;
u1Byte Tone_lenth_1=7, Tone_lenth_2=4;
u2Byte Tone_idx_1[7]={88, 104, 120, 8, 24, 40, 56};
u2Byte Tone_idx_2[4]={8, 24, 40, 56};
u4Byte PSD_report_Main[11]={0}, PSD_report_Aux[11]={0};
//u1Byte Tone_lenth_1=4, Tone_lenth_2=2;
//u2Byte Tone_idx_1[4]={88, 120, 24, 56};
//u2Byte Tone_idx_2[2]={ 24, 56};
//u4Byte PSD_report_Main[6]={0}, PSD_report_Aux[6]={0};
u4Byte PSD_report_temp,MAX_PSD_report_Main=0,MAX_PSD_report_Aux=0;
u4Byte PSD_power_threshold;
u4Byte Main_psd_result=0, Aux_psd_result=0;
u4Byte Regc50, Reg948, Regb2c,Regc14,Reg908;
u4Byte i=0,test_num=8;
if(pDM_Odm->SupportICType != ODM_RTL8723B)
return;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection_PSD()============> \n"));
//2 [ Backup Current RF/BB Settings ]
Channel_ori = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord);
Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
Regc14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord);
Reg908 = ODM_GetBBReg(pDM_Odm, 0x908, bMaskDWord);
//2 [ Setting for doing PSD function (CH4)]
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); //disable whole CCK block
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // Turn off TX -> Pause TX Queue
ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); // [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA]
// PHYTXON while loop
ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x803);
while (ODM_GetBBReg(pDM_Odm, 0xdf4, BIT6))
{
i++;
if (i > 1000000)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i));
break;
}
}
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH4 & 40M
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf
ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pt //Set PSD 128 ptss
ODM_StallExecution(3000);
//2 [ Doing PSD Function in (CH4)]
//Antenna A
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n"));
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200);
ODM_StallExecution(10);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n"));
for (i=0;i<test_num;i++)
{
for (tone_idx=0;tone_idx<Tone_lenth_1;tone_idx++)
{
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_1[tone_idx], initial_gain);
//if( PSD_report_temp>PSD_report_Main[tone_idx] )
PSD_report_Main[tone_idx]+=PSD_report_temp;
}
}
//Antenna B
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n"));
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280);
ODM_StallExecution(10);
for (i=0;i<test_num;i++)
{
for (tone_idx=0;tone_idx<Tone_lenth_1;tone_idx++)
{
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_1[tone_idx], initial_gain);
//if( PSD_report_temp>PSD_report_Aux[tone_idx] )
PSD_report_Aux[tone_idx]+=PSD_report_temp;
}
}
//2 [ Doing PSD Function in (CH8)]
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0
ODM_StallExecution(3000);
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH8 & 40M
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf
ODM_StallExecution(3000);
//Antenna A
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n"));
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200);
ODM_StallExecution(10);
for (i=0;i<test_num;i++)
{
for (tone_idx=0;tone_idx<Tone_lenth_2;tone_idx++)
{
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_2[tone_idx], initial_gain);
//if( PSD_report_temp>PSD_report_Main[tone_idx] )
PSD_report_Main[Tone_lenth_1+tone_idx]+=PSD_report_temp;
}
}
//Antenna B
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n"));
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280);
ODM_StallExecution(10);
for (i=0;i<test_num;i++)
{
for (tone_idx=0;tone_idx<Tone_lenth_2;tone_idx++)
{
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_2[tone_idx], initial_gain);
//if( PSD_report_temp>PSD_report_Aux[tone_idx] )
PSD_report_Aux[Tone_lenth_1+tone_idx]+=PSD_report_temp;
}
}
//2 [ Calculate Result ]
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL) \n"));
for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Main[tone_idx] ));
Main_psd_result+= PSD_report_Main[tone_idx];
if(PSD_report_Main[tone_idx]>MAX_PSD_report_Main)
MAX_PSD_report_Main=PSD_report_Main[tone_idx];
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", Main_psd_result));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", MAX_PSD_report_Main));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL) \n"));
for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Aux[tone_idx] ));
Aux_psd_result+= PSD_report_Aux[tone_idx];
if(PSD_report_Aux[tone_idx]>MAX_PSD_report_Aux)
MAX_PSD_report_Aux=PSD_report_Aux[tone_idx];
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", Aux_psd_result));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", MAX_PSD_report_Aux));
//Main_psd_result=Main_psd_result-MAX_PSD_report_Main;
//Aux_psd_result=Aux_psd_result-MAX_PSD_report_Aux;
PSD_power_threshold=(Main_psd_result*7)>>3;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result , Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", Main_psd_result, Aux_psd_result,PSD_power_threshold));
//3 [ Dual Antenna ]
if(Aux_psd_result >= PSD_power_threshold )
{
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
{
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
// set bt coexDM from 1ant coexDM to 2ant coexDM
//BT_SetBtCoexAntNum(pAdapter, BT_COEX_ANT_TYPE_DETECTED, 2);
// Init antenna diversity
pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
ODM_AntDivInit(pDM_Odm);
}
//3 [ Single Antenna ]
else
{
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
{
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
}
//2 [ Recover all parameters ]
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,Channel_ori);
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, Regc50);
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c);
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); //enable whole CCK block
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x0); //Turn on TX // Resume TX Queue
ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, Regc14); // [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA]
ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, Reg908);
return;
}
#endif
void
odm_SwAntDetectInit(
IN PVOID pDM_VOID
)
{
#if(defined(CONFIG_ANT_DETECTION))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
//pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c = ODM_Read4Byte(pDM_Odm, rDPDT_control);
//pDM_SWAT_Table->PreAntenna = MAIN_ANT;
//pDM_SWAT_Table->CurAntenna = MAIN_ANT;
pDM_SWAT_Table->SWAS_NoLink_State = 0;
pDM_SWAT_Table->Pre_Aux_FailDetec = FALSE;
pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = 0xff;
#endif
}
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_AntDect.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/
#if(defined(CONFIG_ANT_DETECTION))
//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
//ANT Test
#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/
#define ANTTESTA 0x01 /*Ant A will be Testing*/
#define ANTTESTB 0x02 /*Ant B will be testing*/
#define MAX_ANTENNA_DETECTION_CNT 10
typedef struct _ANT_DETECTED_INFO{
BOOLEAN bAntDetected;
u4Byte dBForAntA;
u4Byte dBForAntB;
u4Byte dBForAntO;
}ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
typedef enum tag_SW_Antenna_Switch_Definition
{
Antenna_A = 1,
Antenna_B = 2,
Antenna_MAX = 3,
}DM_SWAS_E;
//1 [1. Single Tone Method] ===================================================
VOID
ODM_SingleDualAntennaDefaultSetting(
IN PVOID pDM_VOID
);
BOOLEAN
ODM_SingleDualAntennaDetection(
IN PVOID pDM_VOID,
IN u1Byte mode
);
//1 [2. Scan AP RSSI Method] ==================================================
#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink
BOOLEAN
ODM_SwAntDivCheckBeforeLink(
IN PVOID pDM_VOID
);
//1 [3. PSD Method] ==========================================================
VOID
ODM_SingleDualAntennaDetection_PSD(
IN PVOID pDM_VOID
);
#endif
VOID
odm_SwAntDetectInit(
IN PVOID pDM_VOID
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_AntDiv.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_AntDiv.h
Executable
+608
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
/*#define ANTDIV_VERSION "2.0" //2014.11.04*/
/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/
/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/
#define ANTDIV_VERSION "3.3" /*2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT,
because antenna diversity only works when BT is disable or radio off*/
//1 ============================================================
//1 Definition
//1 ============================================================
#define ANTDIV_INIT 0xff
#define MAIN_ANT 1 //Ant A or Ant Main
#define AUX_ANT 2 //AntB or Ant Aux
#define MAX_ANT 3 // 3 for AP using
#define ANT1_2G 0 // = ANT2_5G
#define ANT2_2G 1 // = ANT1_5G
/*smart antenna*/
#define SUPPORT_RF_PATH_NUM 4
#define SUPPORT_BEAM_PATTERN_NUM 4
//Antenna Diversty Control Type
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
#define ODM_ANTDIV_2G BIT0
#define ODM_ANTDIV_5G BIT1
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define FAT_ON 1
#define FAT_OFF 0
#define TX_BY_DESC 1
#define REG 0
#define RSSI_METHOD 0
#define EVM_METHOD 1
#define CRC32_METHOD 2
#define INIT_ANTDIV_TIMMER 0
#define CANCEL_ANTDIV_TIMMER 1
#define RELEASE_ANTDIV_TIMMER 2
#define CRC32_FAIL 1
#define CRC32_OK 0
#define Evm_RSSI_TH_High 25
#define Evm_RSSI_TH_Low 20
#define NORMAL_STATE_MIAN 1
#define NORMAL_STATE_AUX 2
#define TRAINING_STATE 3
#define FORCE_RSSI_DIFF 10
#define CSI_ON 1
#define CSI_OFF 0
#define DIVON_CSIOFF 1
#define DIVOFF_CSION 2
#define BDC_DIV_TRAIN_STATE 0
#define BDC_BFer_TRAIN_STATE 1
#define BDC_DECISION_STATE 2
#define BDC_BF_HOLD_STATE 3
#define BDC_DIV_HOLD_STATE 4
#define BDC_MODE_1 1
#define BDC_MODE_2 2
#define BDC_MODE_3 3
#define BDC_MODE_4 4
#define BDC_MODE_NULL 0xff
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
#define HL_SMTANT_2WIRE_DATA_LEN 24
//1 ============================================================
//1 structure
//1 ============================================================
typedef struct _SW_Antenna_Switch_
{
u1Byte Double_chk_flag;
u1Byte try_flag;
s4Byte PreRSSI;
u1Byte CurAntenna;
u1Byte PreAntenna;
u1Byte RSSI_Trying;
u1Byte TestMode;
u1Byte bTriggerAntennaSwitch;
u1Byte SelectAntennaMap;
u1Byte RSSI_target;
u1Byte reset_idx;
u2Byte Single_Ant_Counter;
u2Byte Dual_Ant_Counter;
u2Byte Aux_FailDetec_Counter;
u2Byte Retry_Counter;
// Before link Antenna Switch check
u1Byte SWAS_NoLink_State;
u4Byte SWAS_NoLink_BK_Reg860;
u4Byte SWAS_NoLink_BK_Reg92c;
u4Byte SWAS_NoLink_BK_Reg948;
BOOLEAN ANTA_ON; //To indicate Ant A is or not
BOOLEAN ANTB_ON; //To indicate Ant B is on or not
BOOLEAN Pre_Aux_FailDetec;
BOOLEAN RSSI_AntDect_bResult;
u1Byte Ant5G;
u1Byte Ant2G;
s4Byte RSSI_sum_A;
s4Byte RSSI_sum_B;
s4Byte RSSI_cnt_A;
s4Byte RSSI_cnt_B;
u8Byte lastTxOkCnt;
u8Byte lastRxOkCnt;
u8Byte TXByteCnt_A;
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte TrafficLoad;
u1Byte Train_time;
u1Byte Train_time_flag;
RT_TIMER SwAntennaSwitchTimer;
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
RT_TIMER SwAntennaSwitchTimer_8723B;
u4Byte PktCnt_SWAntDivByCtrlFrame;
BOOLEAN bSWAntDivByCtrlFrame;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if USE_WORKITEM
RT_WORK_ITEM SwAntennaSwitchWorkitem;
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)
RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B;
#endif
#endif
#endif
/* CE Platform use
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
_timer SwAntennaSwitchTimer;
u8Byte lastTxOkCnt;
u8Byte lastRxOkCnt;
u8Byte TXByteCnt_A;
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte DoubleComfirm;
u1Byte TrafficLoad;
//SW Antenna Switch
#endif
*/
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
//Hybrid Antenna Diversity
u4Byte CCK_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte CCK_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte OFDM_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte OFDM_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant1_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant2_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte TxAnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte TargetSTA;
u1Byte antsel;
u1Byte RxIdleAnt;
#endif
}SWAT_T, *pSWAT_T;
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
typedef struct _BF_DIV_COEX_
{
BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM];
BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte BDCcoexType_wBfer;
u1Byte num_Txbfee_Client;
u1Byte num_Txbfer_Client;
u1Byte BDC_Try_counter;
u1Byte BDC_Hold_counter;
u1Byte BDC_Mode;
u1Byte BDC_active_Mode;
u1Byte BDC_state;
u1Byte BDC_RxIdleUpdate_counter;
u1Byte num_Client;
u1Byte pre_num_Client;
u1Byte num_BfTar;
u1Byte num_DivTar;
BOOLEAN bAll_DivSta_Idle;
BOOLEAN bAll_BFSta_Idle;
BOOLEAN BDC_Try_flag;
BOOLEAN BF_pass;
BOOLEAN DIV_pass;
}BDC_T,*pBDC_T;
#endif
#endif
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
typedef struct _SMART_ANTENNA_TRAINNING_ {
u4Byte latch_time;
BOOLEAN pkt_skip_statistic_en;
u4Byte fix_beam_pattern_en;
u4Byte fix_training_num_en;
u4Byte fix_beam_pattern_codeword;
u4Byte update_beam_codeword;
u4Byte ant_num; /*number of smart beam antenna*/
u4Byte beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/
u4Byte data_codeword_bit_num;
u4Byte per_beam_training_pkt_num;
u4Byte pkt_counter;
u4Byte fast_training_beam_num;
u4Byte pre_fast_training_beam_num;
u4Byte pkt_rssi_sum[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
u4Byte pkt_rssi_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
u4Byte rx_idle_beam[SUPPORT_RF_PATH_NUM];
u4Byte pre_codeword;
BOOLEAN force_update_beam_en;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
RT_WORK_ITEM hl_smart_antenna_workitem;
RT_WORK_ITEM hl_smart_antenna_decision_workitem;
#endif
} SAT_T, *pSAT_T;
#endif
typedef struct _FAST_ANTENNA_TRAINNING_
{
u1Byte Bssid[6];
u1Byte antsel_rx_keep_0;
u1Byte antsel_rx_keep_1;
u1Byte antsel_rx_keep_2;
u1Byte antsel_rx_keep_3;
u4Byte antSumRSSI[7];
u4Byte antRSSIcnt[7];
u4Byte antAveRSSI[7];
u1Byte FAT_State;
u4Byte TrainIdx;
u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte RxIdleAnt;
u1Byte AntDiv_OnOff;
BOOLEAN bBecomeLinked;
u4Byte MinMaxRSSI;
u1Byte idx_AntDiv_counter_2G;
u1Byte idx_AntDiv_counter_5G;
u1Byte AntDiv_2G_5G;
u4Byte CCK_counter_main;
u4Byte CCK_counter_aux;
u4Byte OFDM_counter_main;
u4Byte OFDM_counter_aux;
#ifdef ODM_EVM_ENHANCE_ANTDIV
u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
BOOLEAN EVM_method_enable;
u1Byte TargetAnt_EVM;
u1Byte TargetAnt_CRC32;
u1Byte TargetAnt_enhance;
u1Byte pre_TargetAnt_enhance;
u2Byte Main_MPDU_OK_cnt;
u2Byte Aux_MPDU_OK_cnt;
u4Byte CRC32_Ok_Cnt;
u4Byte CRC32_Fail_Cnt;
u4Byte MainCRC32_Ok_Cnt;
u4Byte AuxCRC32_Ok_Cnt;
u4Byte MainCRC32_Fail_Cnt;
u4Byte AuxCRC32_Fail_Cnt;
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
u4Byte CCK_CtrlFrame_Cnt_main;
u4Byte CCK_CtrlFrame_Cnt_aux;
u4Byte OFDM_CtrlFrame_Cnt_main;
u4Byte OFDM_CtrlFrame_Cnt_aux;
u4Byte MainAnt_CtrlFrame_Sum;
u4Byte AuxAnt_CtrlFrame_Sum;
u4Byte MainAnt_CtrlFrame_Cnt;
u4Byte AuxAnt_CtrlFrame_Cnt;
#endif
BOOLEAN fix_ant_bfee;
BOOLEAN enable_ctrl_frame_antdiv;
BOOLEAN use_ctrl_frame_antdiv;
u1Byte hw_antsw_occur;
}FAT_T,*pFAT_T;
//1 ============================================================
//1 enumeration
//1 ============================================================
typedef enum _FAT_STATE /*Fast antenna training*/
{
FAT_BEFORE_LINK_STATE = 0,
FAT_PREPARE_STATE = 1,
FAT_TRAINING_STATE = 2,
FAT_DECISION_STATE = 3
}FAT_STATE_E, *PFAT_STATE_E;
typedef enum _ANT_DIV_TYPE
{
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/
HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 Ant. entitys, and each Ant. is equipped with 4 antenna patterns*/
}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
//1 ============================================================
//1 function prototype
//1 ============================================================
VOID
ODM_StopAntennaSwitchDm(
IN PVOID pDM_VOID
);
VOID
ODM_SetAntConfig(
IN PVOID pDM_VOID,
IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
);
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
VOID ODM_SwAntDivRestAfterLink(
IN PVOID pDM_VOID
);
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_UpdateRxIdleAnt(
IN PVOID pDM_VOID,
IN u1Byte Ant
);
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_SW_AntDiv_Callback(
IN PRT_TIMER pTimer
);
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
VOID
ODM_SW_AntDiv_Callback(
void *FunctionContext
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_S0S1_SwAntDivByCtrlFrame(
IN PVOID pDM_VOID,
IN u1Byte Step
);
VOID
odm_AntselStatisticsOfCtrlFrame(
IN PVOID pDM_VOID,
IN u1Byte antsel_tr_mux,
IN u4Byte RxPWDBAll
);
VOID
odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
IN PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
#endif
#endif
#ifdef ODM_EVM_ENHANCE_ANTDIV
VOID
odm_EVM_FastAntTrainingCallback(
IN PVOID pDM_VOID
);
#endif
VOID
odm_HW_AntDiv(
IN PVOID pDM_VOID
);
#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
VOID
odm_FastAntTraining(
IN PVOID pDM_VOID
);
VOID
odm_FastAntTrainingCallback(
IN PVOID pDM_VOID
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PVOID pDM_VOID
);
#endif
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
phydm_beam_switch_workitem_callback(
IN PVOID pContext
);
VOID
phydm_beam_decision_workitem_callback(
IN PVOID pContext
);
#endif
VOID
phydm_update_beam_pattern(
IN PVOID pDM_VOID,
IN u4Byte codeword,
IN u4Byte codeword_length
);
void
phydm_set_all_ant_same_beam_num(
IN PVOID pDM_VOID
);
VOID
phydm_hl_smart_ant_cmd(
IN PVOID pDM_VOID,
IN u4Byte *const dm_value,
IN u4Byte *_used,
OUT char *output,
IN u4Byte *_out_len
);
#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/
VOID
ODM_AntDivInit(
IN PVOID pDM_VOID
);
VOID
ODM_AntDiv(
IN PVOID pDM_VOID
);
VOID
odm_AntselStatistics(
IN PVOID pDM_VOID,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u4Byte utility,
IN u1Byte method
);
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
ODM_SetTxAntByTxInfo(
IN PVOID pDM_VOID,
IN pu1Byte pDesc,
IN u1Byte macId
);
#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo(
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
unsigned short aid
);
#endif
VOID
ODM_AntDiv_Config(
IN PVOID pDM_VOID
);
VOID
ODM_UpdateRxIdleAnt_8723B(
IN PVOID pDM_VOID,
IN u1Byte Ant,
IN u4Byte DefaultAnt,
IN u4Byte OptionalAnt
);
VOID
ODM_AntDivTimers(
IN PVOID pDM_VOID,
IN u1Byte state
);
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_AntDivReset(
IN PVOID pDM_VOID
);
VOID
odm_AntennaDiversityInit(
IN PVOID pDM_VOID
);
VOID
odm_AntennaDiversity(
IN PVOID pDM_VOID
);
#endif //#ifndef __ODMANTDIV_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_CfoTracking.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_SetCrystalCap(
IN PVOID pDM_VOID,
IN u1Byte CrystalCap
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
if(pCfoTrack->CrystalCap == CrystalCap)
return;
pCfoTrack->CrystalCap = CrystalCap;
if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) {
/* write 0x24[22:17] = 0x24[16:11] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6)));
} else if (pDM_Odm->SupportICType & ODM_RTL8812) {
/* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6)));
} else if ((pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) {
/* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6)));
} else if (pDM_Odm->SupportICType & ODM_RTL8821B) {
/* write 0x28[6:1] = 0x24[30:25] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7E000000, CrystalCap);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7E, CrystalCap);
} else if (pDM_Odm->SupportICType & ODM_RTL8814A) {
/* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6)));
} else if (pDM_Odm->SupportICType & ODM_RTL8822B) {
/* write 0x24[30:25] = 0x28[6:1] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap);
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n"));
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6)));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap));
#endif
}
u1Byte
odm_GetDefaultCrytaltalCap(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte CrystalCap = 0x20;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
CrystalCap = pHalData->CrystalCap;
#else
prtl8192cd_priv priv = pDM_Odm->priv;
if(priv->pmib->dot11RFEntry.xcap > 0)
CrystalCap = priv->pmib->dot11RFEntry.xcap;
#endif
CrystalCap = CrystalCap & 0x3f;
return CrystalCap;
}
VOID
odm_SetATCStatus(
IN PVOID pDM_VOID,
IN BOOLEAN ATCStatus
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
if(pCfoTrack->bATCStatus == ATCStatus)
return;
ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus);
pCfoTrack->bATCStatus = ATCStatus;
}
BOOLEAN
odm_GetATCStatus(
IN PVOID pDM_VOID
)
{
BOOLEAN ATCStatus;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm));
return ATCStatus;
}
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap)
{
odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap - 1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap));
} else if (pCfoTrack->CrystalCap < pCfoTrack->DefXCap)
{
odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap + 1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap));
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
odm_SetATCStatus(pDM_Odm, TRUE);
#endif
}
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========> \n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x \n",pCfoTrack->bATCStatus, pCfoTrack->DefXCap));
}
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
int CFO_kHz_A, CFO_kHz_B, CFO_ave = 0;
int CFO_ave_diff;
int CrystalCap = (int)pCfoTrack->CrystalCap;
u1Byte Adjust_Xtal = 1;
//4 Support ability
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n"));
return;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n"));
if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly)
{
//4 No link or more than one entry
ODM_CfoTrackingReset(pDM_Odm);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n",
pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly));
}
else
{
//3 1. CFO Tracking
//4 1.1 No new packet
if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n"));
return;
}
pCfoTrack->packetCount_pre = pCfoTrack->packetCount;
//4 1.2 Calculate CFO
CFO_kHz_A = (int)((pCfoTrack->CFO_tail[0] * 3125) / 10)>>7; /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */
CFO_kHz_B = (int)((pCfoTrack->CFO_tail[1] * 3125) / 10)>>7;
if(pDM_Odm->RFType < ODM_2T2R)
CFO_ave = CFO_kHz_A;
else
CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n",
CFO_kHz_A, CFO_kHz_B, CFO_ave));
//4 1.3 Avoid abnormal large CFO
CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre);
if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n"));
pCfoTrack->largeCFOHit = 1;
return;
}
else
pCfoTrack->largeCFOHit = 0;
pCfoTrack->CFO_ave_pre = CFO_ave;
//4 1.4 Dynamic Xtal threshold
if(pCfoTrack->bAdjust == FALSE)
{
if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH))
pCfoTrack->bAdjust = TRUE;
}
else
{
if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW))
pCfoTrack->bAdjust = FALSE;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
//4 1.5 BT case: Disable CFO tracking
if(pDM_Odm->bBtEnabled)
{
pCfoTrack->bAdjust = FALSE;
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n"));
}
/*
//4 1.6 Big jump
if(pCfoTrack->bAdjust)
{
if(CFO_ave > CFO_TH_XTAL_LOW)
Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2);
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal));
}
*/
#endif
//4 1.7 Adjust Crystal Cap.
if(pCfoTrack->bAdjust)
{
if(CFO_ave > CFO_TH_XTAL_LOW)
CrystalCap = CrystalCap + Adjust_Xtal;
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
CrystalCap = CrystalCap - Adjust_Xtal;
if(CrystalCap > 0x3f)
CrystalCap = 0x3f;
else if (CrystalCap < 0)
CrystalCap = 0;
odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
pCfoTrack->CrystalCap, pCfoTrack->DefXCap));
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
return;
//3 2. Dynamic ATC switch
if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC)
{
odm_SetATCStatus(pDM_Odm, FALSE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n"));
}
else
{
odm_SetATCStatus(pDM_Odm, TRUE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n"));
}
#endif
}
}
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
return;
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pPktinfo->bPacketMatchBSSID)
#else
if(pPktinfo->StationID != 0)
#endif
{
//3 Update CFO report for path-A & path-B
// Only paht-A and path-B have CFO tail and short CFO
for(i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++)
{
pCfoTrack->CFO_tail[i] = (int)pcfotail[i];
}
//3 Update packet counter
if(pCfoTrack->packetCount == 0xffffffff)
pCfoTrack->packetCount = 0;
else
pCfoTrack->packetCount++;
}
}
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_CfoTracking.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#define CFO_TRACKING_VERSION "1.3" /*2015.07.29 by YuChen*/
#define CFO_TH_XTAL_HIGH 20 // kHz
#define CFO_TH_XTAL_LOW 10 // kHz
#define CFO_TH_ATC 80 // kHz
typedef struct _CFO_TRACKING_
{
BOOLEAN bATCStatus;
BOOLEAN largeCFOHit;
BOOLEAN bAdjust;
u1Byte CrystalCap;
u1Byte DefXCap;
int CFO_tail[2];
int CFO_ave_pre;
u4Byte packetCount;
u4Byte packetCount_pre;
BOOLEAN bForceXtalCap;
BOOLEAN bReset;
}CFO_TRACKING, *PCFO_TRACKING;
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
);
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DIG.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DIG.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDIG_H__
#define __PHYDMDIG_H__
#define DIG_VERSION "1.10" /*2015.08.11 Stanley, modify IGI upper bound when coverage mode*/
/* Pause DIG & CCKPD */
#define DM_DIG_MAX_PAUSE_TYPE 0x7
typedef struct _Dynamic_Initial_Gain_Threshold_
{
BOOLEAN bStopDIG; // for debug
BOOLEAN bIgnoreDIG;
BOOLEAN bPSDInProgress;
u1Byte Dig_Enable_Flag;
u1Byte Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
u4Byte FALowThresh;
u4Byte FAHighThresh;
u1Byte CurSTAConnectState;
u1Byte PreSTAConnectState;
u1Byte CurMultiSTAConnectState;
u1Byte PreIGValue;
u1Byte CurIGValue;
u1Byte BackupIGValue; //MP DIG
u1Byte BT30_CurIGI;
u1Byte IGIBackup;
s1Byte BackoffVal;
s1Byte BackoffVal_range_max;
s1Byte BackoffVal_range_min;
u1Byte rx_gain_range_max;
u1Byte rx_gain_range_min;
u1Byte Rssi_val_min;
u1Byte PreCCK_CCAThres;
u1Byte CurCCK_CCAThres;
u1Byte PreCCKPDState;
u1Byte CurCCKPDState;
u1Byte CCKPDBackup;
u1Byte pause_cckpd_level;
u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
u1Byte LargeFAHit;
u1Byte ForbiddenIGI;
u4Byte Recover_cnt;
u1Byte DIG_Dynamic_MIN_0;
u1Byte DIG_Dynamic_MIN_1;
BOOLEAN bMediaConnect_0;
BOOLEAN bMediaConnect_1;
u4Byte AntDiv_RSSI_max;
u4Byte RSSI_max;
u1Byte *bP2PInProcess;
u1Byte pause_dig_level;
u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
BOOLEAN bTpTarget;
BOOLEAN bNoiseEst;
u4Byte TpTrainTH_min;
u1Byte IGIOffset_A;
u1Byte IGIOffset_B;
#endif
}DIG_T,*pDIG_T;
typedef struct _FALSE_ALARM_STATISTICS{
u4Byte Cnt_Parity_Fail;
u4Byte Cnt_Rate_Illegal;
u4Byte Cnt_Crc8_fail;
u4Byte Cnt_Mcs_fail;
u4Byte Cnt_Ofdm_fail;
u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A
u4Byte Cnt_Cck_fail;
u4Byte Cnt_all;
u4Byte Cnt_Fast_Fsync;
u4Byte Cnt_SB_Search_fail;
u4Byte Cnt_OFDM_CCA;
u4Byte Cnt_CCK_CCA;
u4Byte Cnt_CCA_all;
u4Byte Cnt_BW_USC; //Gary
u4Byte Cnt_BW_LSC; //Gary
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
/*
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
{
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_PD_STAGE_MAX = 3,
}DM_CCK_PDTH_E;
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
{
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
}DM_DIG_EXT_PORT_ALG_E;
typedef enum tag_DIG_Connect_Definition
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
DIG_STA_BEFORE_CONNECT = 2,
DIG_MultiSTA_DISCONNECT = 3,
DIG_MultiSTA_CONNECT = 4,
DIG_CONNECT_MAX
}DM_DIG_CONNECT_E;
#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
*/
typedef enum tag_PHYDM_Pause_Type {
PHYDM_PAUSE = BIT0,
PHYDM_RESUME = BIT1
} PHYDM_PAUSE_TYPE;
typedef enum tag_PHYDM_Pause_Level {
/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
PHYDM_PAUSE_LEVEL_0 = 0,
PHYDM_PAUSE_LEVEL_1 = 1,
PHYDM_PAUSE_LEVEL_2 = 2,
PHYDM_PAUSE_LEVEL_3 = 3,
PHYDM_PAUSE_LEVEL_4 = 4,
PHYDM_PAUSE_LEVEL_5 = 5,
PHYDM_PAUSE_LEVEL_6 = 6,
PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
} PHYDM_PAUSE_LEVEL;
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX_NIC 0x3e
/*define 8814 2G lower bound*/
#define DM_DIG_MIN_8194A 0x28
#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c
#define DM_DIG_MAX_OF_MIN_NIC 0x3e
#ifdef CONFIG_PCI_HCI
#define DM_DIG_MAX_AP 0x3e
#else
#define DM_DIG_MAX_AP 0x50
#endif
#define DM_DIG_MIN_AP 0x1c
#define DM_DIG_MAX_OF_MIN 0x2A //0x32
#define DM_DIG_MIN_AP_DFS 0x20
#define DM_DIG_MAX_NIC_HP 0x46
#define DM_DIG_MIN_NIC_HP 0x2e
#define DM_DIG_MAX_AP_HP 0x42
#define DM_DIG_MIN_AP_HP 0x30
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#define DM_DIG_MAX_AP_COVERAGR 0x26
#define DM_DIG_MIN_AP_COVERAGE 0x1c
#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22
#define DM_DIG_TP_Target_TH0 500
#define DM_DIG_TP_Target_TH1 1000
#define DM_DIG_TP_Training_Period 10
#endif
//vivi 92c&92d has different definition, 20110504
//this is for 92c
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
#define DM_DIG_FA_TH0 0x80//0x20
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#define DM_DIG_FA_TH1 0x300
#define DM_DIG_FA_TH2 0x400
//this is for 92d
#define DM_DIG_FA_TH0_92D 0x100
#define DM_DIG_FA_TH1_92D 0x400
#define DM_DIG_FA_TH2_92D 0x600
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps
#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps
#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps
#define RSSI_OFFSET_DIG 0x05
VOID
ODM_ChangeDynamicInitGainThresh(
IN PVOID pDM_VOID,
IN u4Byte DM_Type,
IN u4Byte DM_Value
);
VOID
ODM_Write_DIG(
IN PVOID pDM_VOID,
IN u1Byte CurrentIGI
);
VOID
odm_PauseDIG(
IN PVOID pDM_VOID,
IN PHYDM_PAUSE_TYPE PauseType,
IN PHYDM_PAUSE_LEVEL pause_level,
IN u1Byte IGIValue
);
VOID
odm_DIGInit(
IN PVOID pDM_VOID
);
VOID
odm_DIG(
IN PVOID pDM_VOID
);
VOID
odm_DIGbyRSSI_LPS(
IN PVOID pDM_VOID
);
VOID
odm_FalseAlarmCounterStatistics(
IN PVOID pDM_VOID
);
VOID
odm_PauseCCKPacketDetection(
IN PVOID pDM_VOID,
IN PHYDM_PAUSE_TYPE PauseType,
IN PHYDM_PAUSE_LEVEL pause_level,
IN u1Byte CCKPDThreshold
);
VOID
odm_CCKPacketDetectionThresh(
IN PVOID pDM_VOID
);
VOID
ODM_Write_CCK_CCA_Thres(
IN PVOID pDM_VOID,
IN u1Byte CurCCK_CCAThres
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_MPT_DIGCallback(
PRT_TIMER pTimer
);
VOID
odm_MPT_DIGWorkItemCallback(
IN PVOID pContext
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
VOID
odm_MPT_DIGCallback(
IN PVOID pDM_VOID
);
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
VOID
ODM_MPT_DIG(
IN PVOID pDM_VOID
);
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DynamicBBPowerSaving.c
Executable
+121
View File
@@ -0,0 +1,121 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_DynamicBBPowerSavingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
pDM_PSTable->PreCCAState = CCA_MAX;
pDM_PSTable->CurCCAState = CCA_MAX;
pDM_PSTable->PreRFState = RF_MAX;
pDM_PSTable->CurRFState = RF_MAX;
pDM_PSTable->Rssi_val_min = 0;
pDM_PSTable->initialize = 0;
}
void
ODM_RF_Saving(
IN PVOID pDM_VOID,
IN u1Byte bForceInNormal
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
u1Byte Rssi_Up_bound = 30 ;
u1Byte Rssi_Low_bound = 25;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
{
Rssi_Up_bound = 50 ;
Rssi_Low_bound = 45;
}
#endif
if(pDM_PSTable->initialize == 0){
pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
//Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
pDM_PSTable->initialize = 1;
}
if(!bForceInNormal)
{
if(pDM_Odm->RSSI_Min != 0xFF)
{
if(pDM_PSTable->PreRFState == RF_Normal)
{
if(pDM_Odm->RSSI_Min >= Rssi_Up_bound)
pDM_PSTable->CurRFState = RF_Save;
else
pDM_PSTable->CurRFState = RF_Normal;
}
else{
if(pDM_Odm->RSSI_Min <= Rssi_Low_bound)
pDM_PSTable->CurRFState = RF_Normal;
else
pDM_PSTable->CurRFState = RF_Save;
}
}
else
pDM_PSTable->CurRFState=RF_MAX;
}
else
{
pDM_PSTable->CurRFState = RF_Normal;
}
if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
{
if(pDM_PSTable->CurRFState == RF_Save)
{
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
}
else
{
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874);
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
}
pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
}
#endif
}

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