538 lines
22 KiB
C
Executable File
538 lines
22 KiB
C
Executable File
/*
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* Header file of 8188E register
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*
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* $Id: 8188e_reg.h,v 1.1 2011/06/30 11:02:56 victoryman Exp $
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*
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* Copyright (c) 2011 Realtek Semiconductor Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _8192E_REG_H_
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#define _8192E_REG_H_
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//============================================================
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// 8188E Regsiter offset definition
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//============================================================
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/*
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* Project RTL8188E follows most of registers in Project RTL8192c
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* This file includes additional registers for RTL8188E only
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* Header file of RTL8192C registers should always be included
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*/
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//
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// 1. System Configure Register. (Offset 0x000 - 0x0FFh)
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//
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#define REG_92E_BB_PAD_CTRL 0x64
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#define REG_92E_HMEBOX_E0 0x88
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#define REG_92E_HMEBOX_E1 0x8A
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#define REG_92E_HMEBOX_E2 0x8C
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#define REG_92E_HMEBOX_E3 0x8E
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#define REG_92E_WLLPS_CTRL 0x90
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#define REG_92E_RPWM2 0x9E
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#define REG_92E_HIMR 0xB0
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#define REG_92E_HISR 0xB4
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#define REG_92E_HIMRE 0xB8
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#define REG_92E_HISRE 0xBC
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#define REG_92E_EFUSE_DATA1 0xCC
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#define REG_92E_EFUSE_DATA0 0xCD
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#define REG_92E_EPPR 0xCF
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#define REG_92E_TQPNT1 0x218
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#define REG_92E_TQPNT2 0x21C
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#define REG_92E_TDECTRL1 0x228
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#define REG_92E_WATCHDOG 0x35C
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#define REG_92E_VOQ_IDX 0x310
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#define REG_92E_VIQ_IDX 0x314
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#define REG_92E_MGQ_DESA 0x318
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#define REG_92E_VOQ_DESA 0x320
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#define REG_92E_VIQ_DESA 0x328
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#define REG_92E_BEQ_DESA 0x330
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#define REG_92E_BKQ_DESA 0x338
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#define REG_92E_PCIE_HRPWM 0x361
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#define REG_92E_PCIE_CLK_RECOVER 0x362
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#define REG_92E_PCIE_HCPWM 0x363
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#define REG_92E_BEQ_IDX 0x364
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#define REG_92E_BKQ_IDX 0x368
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#define REG_92E_MGQ_IDX 0x36C
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#define REG_92E_HI0Q_IDX 0x370
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#define REG_92E_HI1Q_IDX 0x374
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#define REG_92E_HI2Q_IDX 0x378
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#define REG_92E_HI3Q_IDX 0x37C
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#define REG_92E_PCIE_HRPWM2 0x380
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#define REG_92E_PCIE_HCPWM2 0x382
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#define REG_92E_HCI_PCIE_H2C_MSG 0x384
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#define REG_92E_HCI_PCIE_C2H_MSG 0x388
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#define REG_92E_RXQ_IDX 0x38C
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#define REG_92E_HI4Q_IDX 0x390
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#define REG_92E_HI5Q_IDX 0x394
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#define REG_92E_HI6Q_IDX 0x398
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#define REG_92E_HI7Q_IDX 0x39C
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#define REG_92E_HQ_DES_NUM0 0x3A0
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#define REG_92E_HQ_DES_NUM1 0x3A4
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#define REG_92E_HQ_DES_NUM2 0x3A8
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#define REG_92E_HQ_DES_NUM3 0x3AC
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#define REG_92E_TSFT_CLRQ 0x3B0
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#define REG_92E_ACQ_DES_NUM0 0x3B4
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#define REG_92E_ACQ_DES_NUM1 0x3B8
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#define REG_92E_ACQ_DES_NUM2 0x3BC
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#define REG_92E_HI0Q_DESA 0x3C0
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#define REG_92E_HI1Q_DESA 0x3C8
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#define REG_92E_HI2Q_DESA 0x3D0
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#define REG_92E_HI3Q_DESA 0x3D8
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#define REG_92E_HI4Q_DESA 0x3E0
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#define REG_92E_HI5Q_DESA 0x3E8
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#define REG_92E_HI6Q_DESA 0x3F0
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#define REG_92E_HI7Q_DESA 0x3F8
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#define REG_92E_TXPKTBUF_BCNQ_BDNY1 0x457
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#define REG_92E_MACID_NOLINK 0x484
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#define REG_92E_MACID_PAUSE 0x48C
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#define REG_92E_TXRPT_CTRL 0x4EC
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#define REG_92E_TXRPT_TIM 0x4F0
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#define REG_92E_TXRPT_STSSET 0x4F2
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#define REG_92E_TXRPT_STSVLD 0x4F4
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#define REG_92E_TXRPT_STSINF 0x4F8
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#define REG_92E_MBSSID_CTRL 0x526
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#define REG_92E_PKT_LIFETIME_CTRL 0x528
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#define REG_92E_ATIMWND1 0x570
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#define REG_92E_PRE_DL_BCN_ITV 0x58F
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#define REG_92E_ATIMWND2 0x5A0
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#define REG_92E_ATIMWND3 0x5A1
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#define REG_92E_ATIMWND4 0x5A2
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#define REG_92E_ATIMWND5 0x5A3
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#define REG_92E_ATIMWND6 0x5A4
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#define REG_92E_ATIMWND7 0x5A5
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#define REG_92E_ATIMUGT 0x5A6
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#define REG_92E_HIQ_NO_LMT_EN 0x5A7
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#define REG_92E_DTIM_COUNT_ROOT 0x5A8
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#define REG_92E_DTIM_COUNT_VAP1 0x5A9
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#define REG_92E_DTIM_COUNT_VAP2 0x5AA
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#define REG_92E_DTIM_COUNT_VAP3 0x5AB
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#define REG_92E_DTIM_COUNT_VAP4 0x5AC
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#define REG_92E_DTIM_COUNT_VAP5 0x5AD
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#define REG_92E_DTIM_COUNT_VAP6 0x5AE
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#define REG_92E_DTIM_COUNT_VAP7 0x5AF
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#define REG_92E_DIS_ATIM 0x5B0
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#define REG_92E_UPD_HGQMD 0x604
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//----------------------------------------------------------------------------
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// 8192E REG_92E_HIMR bits (Offset 0xB0-B3, 32 bits)
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// 8192E REG_92E_HISR bits (Offset 0xB4-B7, 32 bits)
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//----------------------------------------------------------------------------
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#define HIMR_92E_TXCCK BIT(30) // TXRPT interrupt when CCX bit of the packet is set
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#define HIMR_92E_PSTIMEOUT BIT(29) // Power Save Time Out Interrupt
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#define HIMR_92E_GTINT4 BIT(28) // When GTIMER4 expires, this bit is set to 1
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#define HIMR_92E_GTINT3 BIT(27) // When GTIMER3 expires, this bit is set to 1
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#define HIMR_92E_TBDER BIT(26) // Transmit Beacon0 Error
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#define HIMR_92E_TBDOK BIT(25) // Transmit Beacon0 OK, ad hoc only
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#define HIMR_92E_TSF_BIT32_TOGGLE BIT(24) // TSF Timer BIT32 toggle indication interrupt
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#define HIMR_92E_BcnInt BIT(20) // Beacon DMA Interrupt 0
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#define HIMR_92E_BDERR0 BIT(16) // Beacon Queue DMA OK0
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#define HIMR_92E_HSISR_IND_ON_INT BIT(15) // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
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#define HIMR_92E_BCNDMAINT_E BIT(14) // Beacon DMA Interrupt Extension for Win7
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#define HIMR_92E_ATIMEND BIT(12) // CTWidnow End or ATIM Window End
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#define HIMR_92E_HISR1_IND_INT BIT(11) // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)
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#define HIMR_92E_C2HCMD BIT(10) // CPU to Host Command INT Status, Write 1 clear
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#define HIMR_92E_CPWM2 BIT(9) // CPU power Mode exchange INT Status, Write 1 clear
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#define HIMR_92E_CPWM BIT(8) // CPU power Mode exchange INT Status, Write 1 clear
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#define HIMR_92E_HIGHDOK BIT(7) // High Queue DMA OK
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#define HIMR_92E_MGNTDOK BIT(6) // Management Queue DMA OK
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#define HIMR_92E_BKDOK BIT(5) // AC_BK DMA OK
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#define HIMR_92E_BEDOK BIT(4) // AC_BE DMA OK
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#define HIMR_92E_VIDOK BIT(3) // AC_VI DMA OK
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#define HIMR_92E_VODOK BIT(2) // AC_VO DMA OK
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#define HIMR_92E_RDU BIT(1) // Rx Descriptor Unavailable
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#define HIMR_92E_ROK BIT(0) // Receive DMA OK
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//----------------------------------------------------------------------------
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// 8192E REG_92E_HIMRE bits (Offset 0xB8-BB, 32 bits)
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// 8192E REG_92E_HIMSE bits (Offset 0xBC-BF, 32 bits)
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//----------------------------------------------------------------------------
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#define HIMRE_92E_BCNDMAINT7 BIT(27) // Beacon DMA Interrupt 7
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#define HIMRE_92E_BCNDMAINT6 BIT(26) // Beacon DMA Interrupt 6
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#define HIMRE_92E_BCNDMAINT5 BIT(25) // Beacon DMA Interrupt 5
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#define HIMRE_92E_BCNDMAINT4 BIT(24) // Beacon DMA Interrupt 4
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#define HIMRE_92E_BCNDMAINT3 BIT(23) // Beacon DMA Interrupt 3
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#define HIMRE_92E_BCNDMAINT2 BIT(22) // Beacon DMA Interrupt 2
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#define HIMRE_92E_BCNDMAINT1 BIT(21) // Beacon DMA Interrupt 1
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#define HIMRE_92E_BCNDOK7 BIT(20) // Beacon Queue DMA OK Interrup 7
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#define HIMRE_92E_BCNDOK6 BIT(19) // Beacon Queue DMA OK Interrup 6
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#define HIMRE_92E_BCNDOK5 BIT(18) // Beacon Queue DMA OK Interrup 5
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#define HIMRE_92E_BCNDOK4 BIT(17) // Beacon Queue DMA OK Interrup 4
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#define HIMRE_92E_BCNDOK3 BIT(16) // Beacon Queue DMA OK Interrup 3
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#define HIMRE_92E_BCNDOK2 BIT(15) // Beacon Queue DMA OK Interrup 2
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#define HIMRE_92E_BCNDOK1 BIT(14) // Beacon Queue DMA OK Interrup 1
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#define HIMRE_92E_ATIMEND_E BIT(13) // ATIM Window End Extension for Win7
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#define HIMRE_92E_TXERR BIT(11) // Tx Error Flag Interrupt Status, write 1 clear.
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#define HIMRE_92E_RXERR BIT(10) // Rx Error Flag INT Status, Write 1 clear
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#define HIMRE_92E_TXFOVW BIT(9) // Transmit FIFO Overflow
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#define HIMRE_92E_RXFOVW BIT(8) // Receive FIFO Overflow
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//----------------------------------------------------------------------------
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// 8192E REG_92E_HQ_DES_NUM0 bits (Offset 0x3A0-3A3, 32 bits)
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//----------------------------------------------------------------------------
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#define ACQ_92E_H1Q_DESCS_MODE_8SEG BIT(31)
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#define ACQ_92E_H1Q_DESC_NUM_MASK 0xfff
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#define ACQ_92E_H1Q_DESC_NUM_SHIFT 16
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#define ACQ_92E_H0Q_DESCS_MODE_8SEG BIT(15)
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#define ACQ_92E_H0Q_DESC_NUM_MASK 0xfff
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#define ACQ_92E_H0Q_DESC_NUM_SHIFT 0
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//----------------------------------------------------------------------------
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// 8192E REG_92E_HQ_DES_NUM1 bits (Offset 0x3A4-3A7, 32 bits)
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//----------------------------------------------------------------------------
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#define ACQ_92E_H3Q_DESCS_MODE_8SEG BIT(31)
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#define ACQ_92E_H3Q_DESC_NUM_MASK 0xfff
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#define ACQ_92E_H3Q_DESC_NUM_SHIFT 16
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#define ACQ_92E_H2Q_DESCS_MODE_8SEG BIT(15)
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#define ACQ_92E_H2Q_DESC_NUM_MASK 0xfff
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#define ACQ_92E_H2Q_DESC_NUM_SHIFT 0
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//----------------------------------------------------------------------------
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// 8192E REG_92E_HQ_DES_NUM2 bits (Offset 0x3A8-3AB, 32 bits)
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//----------------------------------------------------------------------------
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#define ACQ_92E_H5Q_DESCS_MODE_8SEG BIT(31)
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#define ACQ_92E_H5Q_DESC_NUM_MASK 0xfff
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#define ACQ_92E_H5Q_DESC_NUM_SHIFT 16
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#define ACQ_92E_H4Q_DESCS_MODE_8SEG BIT(15)
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#define ACQ_92E_H4Q_DESC_NUM_MASK 0xfff
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#define ACQ_92E_H4Q_DESC_NUM_SHIFT 0
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//----------------------------------------------------------------------------
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// 8192E REG_92E_HQ_DES_NUM3 bits (Offset 0x3AC-3AF, 32 bits)
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//----------------------------------------------------------------------------
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#define ACQ_92E_H7Q_DESCS_MODE_8SEG BIT(31)
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#define ACQ_92E_H7Q_DESC_NUM_MASK 0xfff
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#define ACQ_92E_H7Q_DESC_NUM_SHIFT 16
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#define ACQ_92E_H6Q_DESCS_MODE_8SEG BIT(15)
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#define ACQ_92E_H6Q_DESC_NUM_MASK 0xfff
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#define ACQ_92E_H6Q_DESC_NUM_SHIFT 0
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//----------------------------------------------------------------------------
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// 8192E REG_92E_CLRQ bits (Offset 0x3B0-3B4, 32 bits)
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//----------------------------------------------------------------------------
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#define CLRQ_92E_ALL_IDX 0x3FFF3FFF
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#define CLRQ_92E_HI7Q_HW_IDX BIT(29)
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#define CLRQ_92E_HI6Q_HW_IDX BIT(28)
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#define CLRQ_92E_HI5Q_HW_IDX BIT(27)
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#define CLRQ_92E_HI4Q_HW_IDX BIT(26)
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#define CLRQ_92E_HI3Q_HW_IDX BIT(25)
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#define CLRQ_92E_HI2Q_HW_IDX BIT(24)
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#define CLRQ_92E_HI1Q_HW_IDX BIT(23)
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#define CLRQ_92E_HI0Q_HW_IDX BIT(22)
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#define CLRQ_92E_BKQ_HW_IDX BIT(21)
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#define CLRQ_92E_BEQ_HW_IDX BIT(20)
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#define CLRQ_92E_VIQ_HW_IDX BIT(19)
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#define CLRQ_92E_VOQ_HW_IDX BIT(18)
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#define CLRQ_92E_MGQ_HW_IDX BIT(17)
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#define CLRQ_92E_RXQ_HW_IDX BIT(16)
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#define CLRQ_92E_HI7Q_HOST_IDX BIT(13)
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#define CLRQ_92E_HI6Q_HOST_IDX BIT(12)
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#define CLRQ_92E_HI5Q_HOST_IDX BIT(11)
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#define CLRQ_92E_HI4Q_HOST_IDX BIT(10)
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#define CLRQ_92E_HI3Q_HOST_IDX BIT(9)
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#define CLRQ_92E_HI2Q_HOST_IDX BIT(8)
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#define CLRQ_92E_HI1Q_HOST_IDX BIT(7)
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#define CLRQ_92E_HI0Q_HOST_IDX BIT(6)
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#define CLRQ_92E_BKQ_HOST_IDX BIT(5)
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#define CLRQ_92E_BEQ_HOST_IDX BIT(4)
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#define CLRQ_92E_VIQ_HOST_IDX BIT(3)
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#define CLRQ_92E_VOQ_HOST_IDX BIT(2)
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#define CLRQ_92E_MGQ_HOST_IDX BIT(1)
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#define CLRQ_92E_RXQ_HOST_IDX BIT(0)
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//----------------------------------------------------------------------------
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// 8192E REG_92E_ACQ_DES_NUM0 bits (Offset 0x3B4-3B7, 32 bits)
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//----------------------------------------------------------------------------
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#define ACQ_92E_VIQ_DESCS_MODE_8SEG BIT(31)
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#define ACQ_92E_VIQ_DESC_NUM_MASK 0xfff
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#define ACQ_92E_VIQ_DESC_NUM_SHIFT 16
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#define ACQ_92E_VOQ_DESCS_MODE_8SEG BIT(15)
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#define ACQ_92E_VOQ_DESC_NUM_MASK 0xfff
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#define ACQ_92E_VOQ_DESC_NUM_SHIFT 0
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//----------------------------------------------------------------------------
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// 8192E REG_92E_ACQ_DES_NUM1 bits (Offset 0x3B8-3BB, 32 bits)
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//----------------------------------------------------------------------------
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#define ACQ_92E_BKQ_DESCS_MODE_8SEG BIT(31)
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#define ACQ_92E_BKQ_DESC_NUM_MASK 0xfff
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#define ACQ_92E_BKQ_DESC_NUM_SHIFT 16
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#define ACQ_92E_BEQ_DESCS_MODE_8SEG BIT(15)
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#define ACQ_92E_BEQ_DESC_NUM_MASK 0xfff
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#define ACQ_92E_BEQ_DESC_NUM_SHIFT 0
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//----------------------------------------------------------------------------
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// 8192E REG_92E_ACQ_DES_NUM2 bits (Offset 0x3BC-3BF, 32 bits)
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//----------------------------------------------------------------------------
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#define ACQ_92E_RXQ_DESC_NUM_MASK 0xfff
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#define ACQ_92E_RXQ_DESC_NUM_SHIFT 16
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#define ACQ_92E_MGQ_DESCS_MODE_8SEG BIT(15)
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#define ACQ_92E_MGQ_DESC_NUM_MASK 0xfff
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#define ACQ_92E_MGQ_DESC_NUM_SHIFT 0
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//----------------------------------------------------------------------------
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// 8192E MBID_NUM bits (Offset 0x552, 8 bits)
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//----------------------------------------------------------------------------
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#define MBID_NUM_92E_EN_PREDOWN_BCN BIT(3)
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//----------------------------------------------------------------------------
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// 8192E REG_EFUSE_ACCESS (Offset 0xCF, 8 bits)
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//----------------------------------------------------------------------------
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#define EFUSE_ACCESS_ON_8192E 0x69
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#define EFUSE_ACCESS_OFF_8192E 0x00
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//====================================================
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// EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES
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//====================================================
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#if defined(EN_EFUSE)
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#define PATHA_OFFSET 0x10
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#define PATHB_OFFSET 0x3A
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#define PATHC_OFFSET 0x64
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#define PATHD_OFFSET 0x8E
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/*2.4 GHz, PATH A, 1T*/
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#define EEPROM_2G_CCK1T_TxPower 0x0 // CCK Tx Power base
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#define EEPROM_2G_HT401S_TxPower 0x6 // HT40 Tx Power base
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#define EEPROM_2G_HT201S_TxPowerDiff 0xB // HT20 Tx Power Diff [7:4]
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#define EEPROM_2G_OFDM1T_TxPowerDiff 0xB // OFDM Tx Power Diff [3:0]
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/*2.4 GHz, PATH A, 2T*/
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#define EEPROM_2G_HT402S_TxPowerDiff 0xC // HT40 Tx Power Diff [7:4]
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#define EEPROM_2G_HT202S_TxPowerDiff 0xC // HT20 Tx Power Diff [3:0]
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#define EEPROM_2G_OFDM2T_TxPowerDiff 0xD // OFDM Tx Power Diff [7:4]
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#define EEPROM_2G_CCK2T_TxPowerDiff 0xD // CCK Tx Power Diff [3:0]
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/*2.4 GHz, PATH A, 3T*/
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#define EEPROM_2G_HT403S_TxPowerDiff 0xE // HT40 Tx Power Diff [7:4]
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#define EEPROM_2G_HT203S_TxPowerDiff 0xE // HT40 Tx Power Diff [3:0]
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#define EEPROM_2G_OFDM3T_TxPowerDiff 0xF // OFDM Tx Power Diff [7:4]
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#define EEPROM_2G_CCK3T_TxPowerDiff 0xF // CCK Tx Power Diff [3:0]
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/*2.4 GHz, PATH A, 4T*/
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#define EEPROM_2G_HT404S_TxPowerDiff 0x10 // HT40 Tx Power Diff [7:4]
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#define EEPROM_2G_HT204S_TxPowerDiff 0x10 // HT20 Tx Power Diff [0:3]
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#define EEPROM_2G_OFDM4T_TxPowerDiff 0x11 // OFDM Tx Power Diff [7:4]
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#define EEPROM_2G_CCK4T_TxPowerDiff 0x11 // CCK Tx Power Diff [3:0]
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/*5 GHz, PATH A, 1T*/
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#define EEPROM_5G_HT401S_TxPower 0x12 // HT40 Tx Power Base
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#define EEPROM_5G_HT201S_TxPowerDiff 0x20 // HT20 Tx Power Diff [7:4]
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#define EEPROM_5G_OFDM1T_TxPowerDiff 0x20 // OFDM Tx Power Diff [3:0]
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#define EEPROM_5G_HT801S_TxPowerDiff 0x26 // HT80 Tx Power Diff [7:4]
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#define EEPROM_5G_HT1601S_TxPowerDiff 0x26 // HT160 Tx Power Diff [3:0]
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/*5 GHz, PATH A, 2T*/
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#define EEPROM_5G_HT402S_TxPowerDiff 0x21 // HT40 Tx Power Diff [7:4]
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#define EEPROM_5G_HT202S_TxPowerDiff 0x21 // HT20 Tx Power Diff [3:0]
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#define EEPROM_5G_OFDM2T_TxPowerDiff 0x24 // OFDM Tx Power Diff [7:4]
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#define EEPROM_5G_HT802S_TxPowerDiff 0x27 // HT80 Tx Power Diff [7:4]
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/*5 GHz, PATH A, 3T*/
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#define EEPROM_5G_OFDM3T_TxPowerDiff 0x24 // OFDM Tx Power Diff [3:0]
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#define EEPROM_5G_HT403S_TxPowerDiff 0x22 // HT40 Tx Power Diff [7:4]
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#define EEPROM_5G_HT203S_TxPowerDiff 0x22 // HT20 Tx Power Diff [3:0]
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#define EEPROM_5G_HT803S_TxPowerDiff 0x28 // HT80 Tx Power Diff [7:4]
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#define EEPROM_5G_HT1603S_TxPowerDiff 0x28 // HT160 Tx Power Diff [3:0]
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/*5 GHz, PATH A, 4T*/
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#define EEPROM_5G_HT404S_TxPowerDiff 0x23 // HT40 Tx Power Diff [7:4]
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#define EEPROM_5G_HT204S_TxPowerDiff 0x23 // HT20 Tx Power Diff [3:0]
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#define EEPROM_5G_OFDM4T_TxPowerDiff 0x25 // OFDM Tx Power Diff [3:0]
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#define EEPROM_5G_HT804S_TxPowerDiff 0x29 // HT80 Tx Power Diff [7:4]
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#define EEPROM_5G_HT1604S_TxPowerDiff 0x29 // HT160 Tx Power Diff [3:0]
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#define EEPROM_92E_XTAL_K 0xB9 //Crystal Calibration [5:0]
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#define EEPROM_92E_THERMAL_METER 0xBA //Thermal meter
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#ifdef CONFIG_SDIO_HCI
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#define EEPROM_92E_SDIOTYPE 0xD0
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#define EEPROM_92E_MACADDRESS 0x11A
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#else
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#define EEPROM_92E_MACADDRESS 0xD0 // MAC Address
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#endif
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#endif
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#if 0
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#define PATHA_OFFSET 0x10
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#define PATHB_OFFSET 0x3A
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// 0x10 ~ 0x63 = TX power area.
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#define EEPROM_TX_PWR_INX_8192E 0x0
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#define EEPROM_ChannelPlan_8192E 0xB8
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#define EEPROM_XTAL_8192E 0xB9
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#define EEPROM_THERMAL_METER_8192E 0xBA
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#define EEPROM_IQK_LCK_8192E 0xBB
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#define EEPROM_2G_5G_PA_TYPE_8192E 0xBC
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#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD
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#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF
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#define EEPROM_RF_BOARD_OPTION_8192E 0xC1
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#define EEPROM_RF_FEATURE_OPTION_8192E 0xC2
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#define EEPROM_RF_BT_SETTING_8192E 0xC3
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#define EEPROM_VERSION_8192E 0xC4
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#define EEPROM_CustomID_8192E 0xC5
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#define EEPROM_TX_BBSWING_2G_8192E 0xC6
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#define EEPROM_TX_BBSWING_5G_8192E 0xC7
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#define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8
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#define EEPROM_RF_ANTENNA_OPT_8192E 0xC9
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// RTL8192EE
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#define EEPROM_MAC_ADDR_8192EE 0xD0
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#define EEPROM_VID_8192EE 0xD6
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#define EEPROM_DID_8192EE 0xD8
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#define EEPROM_SVID_8192EE 0xDA
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#define EEPROM_SMID_8192EE 0xDC
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//RTL8192EU
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#define EEPROM_MAC_ADDR_8192EU 0xD7
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#define EEPROM_VID_8192EU 0xD0
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#define EEPROM_PID_8192EU 0xD2
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#define EEPROM_PA_TYPE_8192EU 0xBC
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#define EEPROM_LNA_TYPE_2G_8192EU 0xBD
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#define EEPROM_LNA_TYPE_5G_8192EU 0xBF
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// RTL8192ES
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#define EEPROM_MAC_ADDR_8192ES 0x11B
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#endif
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//-----------------------------------------------------
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//
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// RTL8192E SDIO Configuration
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//
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//-----------------------------------------------------
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// I/O bus domain address mapping
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#define SDIO_LOCAL_BASE 0x10250000
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#define WLAN_IOREG_BASE 0x10260000
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#define FIRMWARE_FIFO_BASE 0x10270000
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#define TX_HIQ_BASE 0x10310000
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#define TX_MIQ_BASE 0x10320000
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#define TX_LOQ_BASE 0x10330000
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#define TX_EXQ_BASE 0x10350000 // 92E Add
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#define RX_RX0FF_BASE 0x10340000
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// SDIO host local register space mapping.
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#define SDIO_LOCAL_MSK 0x0FFF
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#define WLAN_IOREG_MSK 0x7FFF
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#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0]
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#define WLAN_RX0FF_MSK 0x0003
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#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID
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#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13]
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#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13]
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#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13]
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#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13]
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#define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13] (False map) // 0b[16], 111b[15:13] (True map)(92E New)
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#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13]
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#define WLAN_IOREG_DEVICE_ID 8 // 1b[16]
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// SDIO Tx Free Page Index (This order must match SDIO_REG_FREE_TXPG)
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#define HI_QUEUE_IDX 0
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#define MID_QUEUE_IDX 1
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#define LOW_QUEUE_IDX 2
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#define PUBLIC_QUEUE_IDX 3
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#define EXTRA_QUEUE_IDX 4 // 92E New
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#define SDIO_MAX_TX_QUEUE 4 // HIQ, MIQ, LOQ and EXQ
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#define SDIO_MAX_RX_QUEUE 1
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#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control
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#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask
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#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine
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#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
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#define SDIO_REG_OQT_FREE_SPACE 0x001E // OQT Free Space
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#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page
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#define SDIO_REG_HCPWM1 0x0025 // HCI Current Power Mode 1
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#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2
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#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion
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#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1
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#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2
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#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control
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#define SDIO_HIMR_DISABLED 0
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// RTL8188E SDIO Host Interrupt Mask Register
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#define SDIO_HIMR_RX_REQUEST_MSK BIT0
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#define SDIO_HIMR_AVAL_MSK BIT1
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#define SDIO_HIMR_TXERR_MSK BIT2
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#define SDIO_HIMR_RXERR_MSK BIT3
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#define SDIO_HIMR_TXFOVW_MSK BIT4
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#define SDIO_HIMR_RXFOVW_MSK BIT5
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#define SDIO_HIMR_TXBCNOK_MSK BIT6
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#define SDIO_HIMR_TXBCNERR_MSK BIT7
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#define SDIO_HIMR_BCNERLY_INT_MSK BIT16
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#define SDIO_HIMR_C2HCMD_MSK BIT17
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#define SDIO_HIMR_CPWM1_MSK BIT18
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#define SDIO_HIMR_CPWM2_MSK BIT19
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#define SDIO_HIMR_HSISR_IND_MSK BIT20
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#define SDIO_HIMR_GTINT3_IND_MSK BIT21
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#define SDIO_HIMR_GTINT4_IND_MSK BIT22
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#define SDIO_HIMR_PSTIMEOUT_MSK BIT23
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#define SDIO_HIMR_OCPINT_MSK BIT24
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#define SDIO_HIMR_ATIMEND_MSK BIT25
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#define SDIO_HIMR_ATIMEND_E_MSK BIT26
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#define SDIO_HIMR_CTWEND_MSK BIT27
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//RTL8188E SDIO Specific
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#define SDIO_HIMR_MCU_ERR_MSK BIT28
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#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29
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// SDIO Host Interrupt Service Routine
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#define SDIO_HISR_RX_REQUEST BIT0
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#define SDIO_HISR_AVAL BIT1
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#define SDIO_HISR_TXERR BIT2
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#define SDIO_HISR_RXERR BIT3
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#define SDIO_HISR_TXFOVW BIT4
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#define SDIO_HISR_RXFOVW BIT5
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#define SDIO_HISR_TXBCNOK BIT6
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#define SDIO_HISR_TXBCNERR BIT7
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#define SDIO_HISR_BCNERLY_INT BIT16
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#define SDIO_HISR_C2HCMD BIT17
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#define SDIO_HISR_CPWM1 BIT18
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#define SDIO_HISR_CPWM2 BIT19
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#define SDIO_HISR_HSISR_IND BIT20
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#define SDIO_HISR_GTINT3_IND BIT21
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#define SDIO_HISR_GTINT4_IND BIT22
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#define SDIO_HISR_PSTIMEOUT BIT23
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#define SDIO_HISR_OCPINT BIT24
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#define SDIO_HISR_ATIMEND BIT25
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#define SDIO_HISR_ATIMEND_E BIT26
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#define SDIO_HISR_CTWEND BIT27
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//RTL8188E SDIO Specific
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#define SDIO_HISR_MCU_ERR BIT28
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#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29
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#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\
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SDIO_HISR_RXERR |\
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SDIO_HISR_TXFOVW |\
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SDIO_HISR_RXFOVW |\
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SDIO_HISR_TXBCNOK |\
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SDIO_HISR_TXBCNERR |\
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SDIO_HISR_C2HCMD |\
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SDIO_HISR_CPWM1 |\
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SDIO_HISR_CPWM2 |\
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SDIO_HISR_HSISR_IND |\
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SDIO_HISR_GTINT3_IND |\
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SDIO_HISR_GTINT4_IND |\
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SDIO_HISR_PSTIMEOUT |\
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SDIO_HISR_OCPINT)
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// SDIO HCI Suspend Control Register
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#define HCI_RESUME_PWR_RDY BIT1
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#define HCI_SUS_CTRL BIT0
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// SDIO Tx FIFO related
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#define SDIO_TX_FREE_PG_QUEUE 5 // The number of Tx FIFO free page
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#define SDIO_TX_FIFO_PAGE_SZ 256
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#endif
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