110 lines
3.4 KiB
C
Executable File
110 lines
3.4 KiB
C
Executable File
#ifndef __HAL_PWRSEQCMD_H__
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#define __HAL_PWRSEQCMD_H__
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//#if defined(CONFIG_RTL_88E_SUPPORT)|| defined(CONFIG_RTL_8812_SUPPORT) || defined(CONFIG_RTL_92E_SUPPORT)
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/*---------------------------------------------*/
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//3 The value of cmd: 4 bits
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/*---------------------------------------------*/
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#define PWR_CMD_READ 0x00
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// offset: the read register offset
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// msk: the mask of the read value
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// value: N/A, left by 0
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// note: dirver shall implement this function by read & msk
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#define PWR_CMD_WRITE 0x01
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// offset: the read register offset
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// msk: the mask of the write bits
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// value: write value
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// note: driver shall implement this cmd by read & msk after write
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#define PWR_CMD_POLLING 0x02
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// offset: the read register offset
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// msk: the mask of the polled value
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// value: the value to be polled, masked by the msd field.
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// note: driver shall implement this cmd by
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// do{
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// if( (Read(offset) & msk) == (value & msk) )
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// break;
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// } while(not timeout);
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#define PWR_CMD_DELAY 0x03
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// offset: the value to delay
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// msk: N/A
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// value: the unit of delay, 0: us, 1: ms
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#define PWR_CMD_END 0x04
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// offset: N/A
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// msk: N/A
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// value: N/A
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/*---------------------------------------------*/
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//3 The value of base: 4 bits
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/*---------------------------------------------*/
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// define the base address of each block
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#define PWR_BASEADDR_MAC 0x00
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#define PWR_BASEADDR_USB 0x01
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#define PWR_BASEADDR_PCIE 0x02
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#define PWR_BASEADDR_SDIO 0x03
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/*---------------------------------------------*/
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//3 The value of interface_msk: 4 bits
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/*---------------------------------------------*/
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#define PWR_INTF_SDIO_MSK BIT(0)
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#define PWR_INTF_USB_MSK BIT(1)
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#define PWR_INTF_PCI_MSK BIT(2)
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#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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/*---------------------------------------------*/
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//3 The value of fab_msk: 4 bits
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/*---------------------------------------------*/
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#define PWR_FAB_TSMC_MSK BIT(0)
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#define PWR_FAB_UMC_MSK BIT(1)
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#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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/*---------------------------------------------*/
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//3The value of cut_msk: 8 bits
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/*---------------------------------------------*/
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#define PWR_CUT_TESTCHIP_MSK BIT(0)
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#define PWR_CUT_A_MSK BIT(1)
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#define PWR_CUT_B_MSK BIT(2)
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#define PWR_CUT_C_MSK BIT(3)
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#define PWR_CUT_D_MSK BIT(4)
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#define PWR_CUT_E_MSK BIT(5)
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#define PWR_CUT_F_MSK BIT(6)
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#define PWR_CUT_G_MSK BIT(7)
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#define PWR_CUT_ALL_MSK 0xFF
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typedef enum _PWRSEQ_CMD_DELAY_UNIT_
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{
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PWRSEQ_DELAY_US,
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PWRSEQ_DELAY_MS,
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} PWRSEQ_DELAY_UNIT;
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typedef struct _WL_PWR_CFG_
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{
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unsigned short offset;
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unsigned char cut_msk;
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unsigned char fab_msk:4;
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unsigned char interface_msk:4;
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unsigned char base:4;
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unsigned char cmd:4;
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unsigned char msk;
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unsigned char value;
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} WLAN_PWR_CFG, *PWLAN_PWR_CFG;
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#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
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#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
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#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
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#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
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#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
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#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
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#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
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#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
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//#endif
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#endif //__HAL_PWRSEQCMD_H__
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