60 lines
2.7 KiB
Plaintext
60 lines
2.7 KiB
Plaintext
Qualcomm Global Distributed Switch Controller (GDSC) Regulator Driver
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The GDSC driver, implemented under the regulator framework, is responsible for
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safely collapsing and restoring power to peripheral cores on chipsets like
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msm8974 for power savings.
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Required properties:
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- compatible: Must be "qcom,gdsc"
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- regulator-name: A string used as a descriptive name for regulator outputs
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- reg: The address of the GDSCR register
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Optional properties:
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- parent-supply: phandle to the parent supply/regulator node
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- clock-names: List of string names for core clocks
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- qcom,retain-mem: Presence denotes a hardware requirement to leave the
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forced core memory retention signals in the core's clock
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branch control registers asserted.
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- qcom,retain-periph: Presence denotes a hardware requirement to leave the
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forced periph memory retention signal in the core's clock
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branch control registers asserted.
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- qcom,skip-logic-collapse: Presence denotes a requirement to leave power to
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the core's logic enabled.
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- qcom,support-hw-trigger: Presence denotes a hardware feature to switch
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on/off this regulator based on internal HW signals
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to save more power.
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- qcom,enable-root-clk: Presence denotes that the clocks in the "clocks"
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property are required to be enabled before gdsc is
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turned on and disabled before turning off gdsc. This
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will be used in subsystems where reset is synchronous
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and root clk is active without sw being aware of its
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state. The clock-name which denotes the root clock
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should be named as "core_root_clk".
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- qcom,force-enable-root-clk: If set, denotes that the root clock should be
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force enabled before turning on the GDSC and then be
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immediately force disabled. Likewise for GDSC disable.
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This is used in cases where the core root clock needs
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to be force-enabled prior to turning on the core. The
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clock-name which denotes the root clock should be
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"core_root_clk".
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- qcom,clk-dis-wait-val: Input value for CLK_DIS_WAIT controls state transition
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delay after halting clock in the collapsible core.
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- reg-names: Names of the bases for the above "reg" registers.
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Ex. "base", "domain_addr".
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- qcom,no-status-check-on-disable: Do not poll the status bit when GDSC
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is disabled.
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- qcom,disallow-clear: Presence denotes the periph & core memory will not be
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cleared, unless the required subsystem does not invoke
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the api which will allow clearing the bits.
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- qcom,gds-timeout: Maximum time (in usecs) that might be taken by a GDSC
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to enable.
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Example:
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gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
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compatible = "qcom,gdsc";
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regulator-name = "gdsc_oxili_gx";
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parent-supply = <&pm8841_s4>;
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reg = <0xfd8c4024 0x4>;
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clock-names = "core_clk";
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};
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