560 lines
12 KiB
C
560 lines
12 KiB
C
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <err.h>
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#include <assert.h>
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#include <debug.h>
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#include <reg.h>
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#include <platform/timer.h>
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#include <platform/iomap.h>
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#include <mmc.h>
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#include <clock.h>
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#include <platform/clock.h>
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void hsusb_clock_init(void)
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{
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int ret;
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struct clk *iclk, *cclk;
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ret = clk_get_set_enable("usb_iface_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Wait for the clocks to be stable since we are disabling soon after. */
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mdelay(1);
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iclk = clk_get("usb_iface_clk");
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cclk = clk_get("usb_core_clk");
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clk_disable(iclk);
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clk_disable(cclk);
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/* Wait for the clock disable to complete. */
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mdelay(1);
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/* Start the block reset for usb */
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writel(1, USB_HS_BCR);
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/* Wait for reset to complete. */
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mdelay(1);
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/* Take usb block out of reset */
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writel(0, USB_HS_BCR);
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/* Wait for the block to be brought out of reset. */
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mdelay(1);
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ret = clk_enable(iclk);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_enable(cclk);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
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ASSERT(0);
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}
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}
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void clock_init_mmc(uint32_t interface)
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{
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char clk_name[64];
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int ret;
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snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
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/* enable interface clock */
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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/* Configure MMC clock */
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void clock_config_mmc(uint32_t interface, uint32_t freq)
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{
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int ret;
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char clk_name[64];
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snprintf(clk_name, 64, "sdc%u_core_clk", interface);
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if(freq == MMC_CLK_400KHZ)
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{
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ret = clk_get_set_enable(clk_name, 400000, 1);
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}
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else if(freq == MMC_CLK_50MHZ)
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{
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ret = clk_get_set_enable(clk_name, 50000000, 1);
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}
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else if(freq == MMC_CLK_200MHZ)
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{
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ret = clk_get_set_enable(clk_name, 200000000, 1);
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}
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else
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{
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dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
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ASSERT(0);
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}
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if(ret)
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{
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dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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/* Configure UART clock based on the UART block id*/
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void clock_config_uart_dm(uint8_t id)
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{
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int ret;
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ret = clk_get_set_enable("uart2_iface_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("uart2_core_clk", 7372800, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set uart2_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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/* Configure MDP clock */
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void mdp_clock_enable(void)
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{
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int ret;
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ret = clk_get_set_enable("axi_clk_src", 200000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set axi_clk_src ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mmss_mmssnoc_axi_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mmss_mmssnoc_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mmss_s0_axi_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mmss_s0_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdp_ahb_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_ahb_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdp_axi_clk" , 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdp_vsync_clk" , 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_vsync_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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void mdp_clock_disable(void)
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{
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clk_disable(clk_get("mdp_vsync_clk"));
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clk_disable(clk_get("mdp_axi_clk"));
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clk_disable(clk_get("mdp_ahb_clk"));
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clk_disable(clk_get("mmss_s0_axi_clk"));
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clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
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}
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int dsi_vco_set_rate(uint32_t rate)
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{
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uint32_t temp, val;
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unsigned long fb_divider;
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temp = rate / 10;
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val = VCO_PARENT_RATE / 10;
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fb_divider = (temp * VCO_PREF_DIV_RATIO) / val;
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fb_divider = fb_divider / 2 - 1;
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temp = readl(DSIPHY_PLL_CTRL(1));
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val = (temp & 0xFFFFFF00) | (fb_divider & 0xFF);
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writel(val, DSIPHY_PLL_CTRL(1));
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temp = readl(DSIPHY_PLL_CTRL(2));
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val = (temp & 0xFFFFFFF8) | ((fb_divider >> 8) & 0x07);
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writel(val, DSIPHY_PLL_CTRL(2));
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temp = readl(DSIPHY_PLL_CTRL(3));
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val = (temp & 0xFFFFFFC0) | (VCO_PREF_DIV_RATIO - 1);
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writel(val, DSIPHY_PLL_CTRL(3));
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return 0;
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}
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uint32_t dsi_vco_round_rate(uint32_t rate)
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{
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uint32_t vco_rate = rate;
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if (rate < VCO_MIN_RATE)
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vco_rate = VCO_MIN_RATE;
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else if (rate > VCO_MAX_RATE)
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vco_rate = VCO_MAX_RATE;
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return vco_rate;
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}
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int dsi_byte_clk_set(uint32_t *vcoclk_rate, uint32_t rate)
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{
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int div, ret;
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uint32_t vco_rate, bitclk_rate;
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uint32_t temp, val;
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bitclk_rate = 8 * rate;
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for (div = 1; div < VCO_MAX_DIVIDER; div++)
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{
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vco_rate = dsi_vco_round_rate(bitclk_rate * div);
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if (vco_rate == bitclk_rate * div)
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break;
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if (vco_rate < bitclk_rate * div)
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return -1;
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}
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if (vco_rate != bitclk_rate * div)
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return -1;
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ret = dsi_vco_set_rate(vco_rate);
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if (ret)
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{
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dprintf(CRITICAL, "fail to set vco rate, ret = %d\n", ret);
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return ret;
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}
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*vcoclk_rate = vco_rate;
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/* set the bit clk divider */
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temp = readl(DSIPHY_PLL_CTRL(8));
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val = (temp & 0xFFFFFFF0) | (div - 1);
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writel(val, DSIPHY_PLL_CTRL(8));
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/* set the byte clk divider */
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temp = readl(DSIPHY_PLL_CTRL(9));
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val = (temp & 0xFFFFFF00) | (vco_rate / rate - 1);
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writel(val, DSIPHY_PLL_CTRL(9));
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return 0;
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}
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int dsi_dsi_clk_set(uint32_t vco_rate, uint32_t rate)
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{
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uint32_t temp, val;
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if (vco_rate % rate != 0)
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{
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dprintf(CRITICAL, "dsiclk_set_rate invalid rate\n");
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return -1;
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}
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temp = readl(DSIPHY_PLL_CTRL(10));
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val = (temp & 0xFFFFFF00) | (vco_rate / rate - 1);
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writel(val, DSIPHY_PLL_CTRL(10));
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return 0;
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}
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void dsi_setup_dividers(uint32_t val, uint32_t cfg_rcgr,
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uint32_t cmd_rcgr)
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{
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uint32_t i = 0;
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uint32_t term_cnt = 5000;
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int32_t reg;
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writel(val, cfg_rcgr);
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writel(0x1, cmd_rcgr);
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reg = readl(cmd_rcgr);
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while (reg & 0x1)
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{
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i++;
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if (i > term_cnt)
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{
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dprintf(CRITICAL, "some dsi clock not enabled"
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"exceeded polling TIMEOUT!\n");
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break;
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}
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udelay(1);
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reg = readl(cmd_rcgr);
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}
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}
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void vco_enable(int enable)
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{
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if (enable)
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{
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writel(0x1, DSIPHY_PLL_CTRL(0));
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while (!(readl(DSIPHY_PLL_READY) & 0x01))
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udelay(1);
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} else {
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writel(0x0, DSIPHY_PLL_CTRL(0));
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}
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}
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void dsi_clock_enable(uint32_t dsiclk_rate, uint32_t byteclk_rate)
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{
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uint32_t vcoclk_rate;
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int ret;
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ret = clk_get_set_enable("dsi_ahb_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set dsi_ahb_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = dsi_byte_clk_set(&vcoclk_rate, byteclk_rate);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set byteclk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = dsi_dsi_clk_set(vcoclk_rate, dsiclk_rate);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set dsiclk ret = %d\n", ret);
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ASSERT(0);
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}
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vco_enable(1);
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dsi_setup_dividers(0x105, DSI_PCLK_CFG_RCGR, DSI_PCLK_CMD_RCGR);
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dsi_setup_dividers(0x101, DSI_BYTE_CFG_RCGR, DSI_BYTE_CMD_RCGR);
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dsi_setup_dividers(0x101, DSI_CFG_RCGR, DSI_CMD_RCGR);
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ret = clk_get_set_enable("dsi_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set dsi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("dsi_byte_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set dsi_byte_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("dsi_esc_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set dsi_esc_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("dsi_pclk_clk", 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set dsi_pclk_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdp_lcdc_clk" , 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_lcdc_clk ret = %d\n", ret);
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ASSERT(0);
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}
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ret = clk_get_set_enable("mdp_dsi_clk" , 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set mdp_dsi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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}
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void dsi_clock_disable(void)
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{
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clk_disable(clk_get("mdp_dsi_clk"));
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clk_disable(clk_get("mdp_lcdc_clk"));
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clk_disable(clk_get("dsi_pclk_clk"));
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clk_disable(clk_get("dsi_esc_clk"));
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clk_disable(clk_get("dsi_byte_clk"));
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clk_disable(clk_get("dsi_clk"));
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vco_enable(0);
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clk_disable(clk_get("dsi_ahb_clk"));
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}
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void clock_ce_enable(uint8_t instance)
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{
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int ret;
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char clk_name[64];
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snprintf(clk_name, 64, "ce%u_src_clk", instance);
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ret = clk_get_set_enable(clk_name, 100000000, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_core_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
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ASSERT(0);
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}
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snprintf(clk_name, 64, "ce%u_axi_clk", instance);
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ret = clk_get_set_enable(clk_name, 0, 1);
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if(ret)
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{
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dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
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ASSERT(0);
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}
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/* Wait for 48 * #pipes cycles.
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* This is necessary as immediately after an access control reset (boot up)
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* or a debug re-enable, the Crypto core sequentially clears its internal
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* pipe key storage memory. If pipe key initialization writes are attempted
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* during this time, they may be overwritten by the internal clearing logic.
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*/
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udelay(1);
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}
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void clock_ce_disable(uint8_t instance)
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{
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struct clk *ahb_clk;
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struct clk *cclk;
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struct clk *axi_clk;
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struct clk *src_clk;
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char clk_name[64];
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snprintf(clk_name, 64, "ce%u_src_clk", instance);
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src_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
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ahb_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_axi_clk", instance);
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axi_clk = clk_get(clk_name);
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snprintf(clk_name, 64, "ce%u_core_clk", instance);
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cclk = clk_get(clk_name);
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clk_disable(ahb_clk);
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clk_disable(axi_clk);
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clk_disable(cclk);
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clk_disable(src_clk);
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/* Some delay for the clocks to stabalize. */
|
|
udelay(1);
|
|
}
|
|
|
|
/* Function to asynchronously reset CE.
|
|
* Function assumes that all the CE clocks are off.
|
|
*/
|
|
static void ce_async_reset(uint8_t instance)
|
|
{
|
|
if (instance == 1)
|
|
{
|
|
/* Start the block reset for CE */
|
|
writel(1, GCC_CE1_BCR);
|
|
|
|
udelay(2);
|
|
|
|
/* Take CE block out of reset */
|
|
writel(0, GCC_CE1_BCR);
|
|
|
|
udelay(2);
|
|
}
|
|
else
|
|
{
|
|
dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
|
|
ASSERT(0);
|
|
}
|
|
}
|
|
|
|
void clock_config_ce(uint8_t instance)
|
|
{
|
|
/* Need to enable the clock before disabling since the clk_disable()
|
|
* has a check to default to nop when the clk_enable() is not called
|
|
* on that particular clock.
|
|
*/
|
|
clock_ce_enable(instance);
|
|
|
|
clock_ce_disable(instance);
|
|
|
|
ce_async_reset(instance);
|
|
|
|
clock_ce_enable(instance);
|
|
|
|
}
|