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2024-09-09 08:52:07 +00:00
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bootable/bootloader/lk/platform/msm7k/acpuclock.c
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include <kernel/thread.h>
#include <platform/iomap.h>
#include <reg.h>
#include <debug.h>
#include <mmc.h>
#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
#define VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
#define PLL2_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x33C)
#define SRC_SEL_PLL1 1 /* PLL1. */
#define SRC_SEL_PLL2 2 /* PLL2. */
#define SRC_SEL_PLL3 3 /* PLL3. Used for 7x25. */
#define DIV_4 3
#define DIV_2 1
#define WAIT_CNT 100
#define VDD_LEVEL 7
#define MIN_AXI_HZ 120000000
#define ACPU_800MHZ 41
void pll_request(unsigned pll, unsigned enable);
void axi_clock_init(unsigned rate);
/* The stepping frequencies have been choosen to make sure the step
* is <= 256 MHz for both turbo mode and normal mode targets. The
* table also assumes the ACPU is running at TCXO freq and AHB div is
* set to DIV_1.
*
* To use the tables:
* - Start at location 0/1 depending on clock source sel bit.
* - Set values till end of table skipping every other entry.
* - When you reach the end of the table, you are done scaling.
*
* TODO: Need to fix SRC_SEL_PLL1 for 7x25.
*/
uint32_t const clk_cntl_reg_val_7625[] = {
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
(WAIT_CNT << 16) | (SRC_SEL_PLL3 << 4) | DIV_2,
(WAIT_CNT << 16) | (SRC_SEL_PLL3 << 12) | (DIV_2 << 8),
};
uint32_t const clk_cntl_reg_val_7627[] = {
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_2,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
};
uint32_t const clk_cntl_reg_val_7627T[] = {
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4),
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12),
};
/* Using DIV_4 for all cases to avoid worrying about turbo vs. normal
* mode. Able to use DIV_4 for all steps because it's the largest AND
* the final value. */
uint32_t const clk_sel_reg_val[] = {
DIV_4 << 1 | 1,
DIV_4 << 1 | 0,
DIV_4 << 1 | 0,
DIV_4 << 1 | 1,
DIV_4 << 1 | 1,
DIV_4 << 1 | 0,
};
/* enum for SDC CLK IDs */
enum
{
SDC1_CLK = 19,
SDC1_PCLK = 20,
SDC2_CLK = 21,
SDC2_PCLK = 22,
SDC3_CLK = 23,
SDC3_PCLK = 24,
SDC4_CLK = 25,
SDC4_PCLK = 26
};
/* Zero'th entry is dummy */
static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
void mdelay(unsigned msecs);
void acpu_clock_init(void)
{
unsigned i,clk;
#if (!ENABLE_NANDWRITE)
int *modem_stat_check = (MSM_SHARED_BASE + 0x14);
/* Wait for modem to be ready before clock init */
while (readl(modem_stat_check) != 1);
#endif
/* Increase VDD level to the final value. */
writel((1 << 7) | (VDD_LEVEL << 3), VDD_SVS_PLEVEL_ADDR);
#if (!ENABLE_NANDWRITE)
thread_sleep(1);
#else
mdelay(1);
#endif
/* Read clock source select bit. */
i = readl(A11S_CLK_SEL_ADDR) & 1;
clk = readl(PLL2_L_VAL_ADDR) & 0x3F;
/* Jump into table and set every other entry. */
for(; i < ARRAY_SIZE(clk_cntl_reg_val_7627); i += 2) {
#ifdef ENABLE_PLL3
writel(clk_cntl_reg_val_7625[i], A11S_CLK_CNTL_ADDR);
#else
if(clk == ACPU_800MHZ)
writel(clk_cntl_reg_val_7627T[i], A11S_CLK_CNTL_ADDR);
else
writel(clk_cntl_reg_val_7627[i], A11S_CLK_CNTL_ADDR);
#endif
/* Would need a dmb() here but the whole address space is
* strongly ordered, so it should be fine.
*/
writel(clk_sel_reg_val[i], A11S_CLK_SEL_ADDR);
#if (!ENABLE_NANDWRITE)
thread_sleep(1);
#else
mdelay(1);
#endif
}
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
uint32_t reg = 0;
if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 )
{
dprintf(CRITICAL, "Failure setting clock rate for MCLK - "
"clk_rate: %d\n!", freq);
ASSERT(0);
}
/* enable clock */
if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 )
{
dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
ASSERT(0);
}
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
writel( reg, MMC_BOOT_MCI_CLK );
/* Wait for the MMC_BOOT_MCI_CLK write to go through. */
mmc_mclk_reg_wr_delay();
/* Wait 1 ms to provide the free running SD CLK to the card. */
mdelay(1);
}
/* Intialize MMC clock */
void clock_init_mmc(uint32_t interface)
{
if( mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0 )
{
dprintf(CRITICAL, "Failure enabling PCLK!\n");
ASSERT(0);
}
}
bootable/bootloader/lk/platform/msm7k/gpio.c
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
#include <dev/gpio.h>
#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
/* output value */
#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
/* same pin map as above, output enable */
#define GPIO_OE_0 GPIO1_REG(0x10)
#define GPIO_OE_1 GPIO2_REG(0x08)
#define GPIO_OE_2 GPIO1_REG(0x14)
#define GPIO_OE_3 GPIO1_REG(0x18)
#define GPIO_OE_4 GPIO1_REG(0x1C)
/* same pin map as above, input read */
#define GPIO_IN_0 GPIO1_REG(0x34)
#define GPIO_IN_1 GPIO2_REG(0x20)
#define GPIO_IN_2 GPIO1_REG(0x38)
#define GPIO_IN_3 GPIO1_REG(0x3C)
#define GPIO_IN_4 GPIO1_REG(0x40)
/* same pin map as above, 1=edge 0=level interrup */
#define GPIO_INT_EDGE_0 GPIO1_REG(0x60)
#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
#define GPIO_INT_EDGE_2 GPIO1_REG(0x64)
#define GPIO_INT_EDGE_3 GPIO1_REG(0x68)
#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C)
/* same pin map as above, 1=positive 0=negative */
#define GPIO_INT_POS_0 GPIO1_REG(0x70)
#define GPIO_INT_POS_1 GPIO2_REG(0x58)
#define GPIO_INT_POS_2 GPIO1_REG(0x74)
#define GPIO_INT_POS_3 GPIO1_REG(0x78)
#define GPIO_INT_POS_4 GPIO1_REG(0x7C)
/* same pin map as above, interrupt enable */
#define GPIO_INT_EN_0 GPIO1_REG(0x80)
#define GPIO_INT_EN_1 GPIO2_REG(0x60)
#define GPIO_INT_EN_2 GPIO1_REG(0x84)
#define GPIO_INT_EN_3 GPIO1_REG(0x88)
#define GPIO_INT_EN_4 GPIO1_REG(0x8C)
/* same pin map as above, write 1 to clear interrupt */
#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90)
#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94)
#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98)
#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C)
/* same pin map as above, 1=interrupt pending */
#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0)
#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4)
#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8)
#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC)
typedef struct gpioregs gpioregs;
struct gpioregs
{
unsigned out;
unsigned in;
unsigned int_status;
unsigned int_clear;
unsigned int_en;
unsigned int_edge;
unsigned int_pos;
unsigned oe;
};
static gpioregs GPIO_REGS[] = {
{
.out = GPIO_OUT_0,
.in = GPIO_IN_0,
.int_status = GPIO_INT_STATUS_0,
.int_clear = GPIO_INT_CLEAR_0,
.int_en = GPIO_INT_EN_0,
.int_edge = GPIO_INT_EDGE_0,
.int_pos = GPIO_INT_POS_0,
.oe = GPIO_OE_0,
},
{
.out = GPIO_OUT_1,
.in = GPIO_IN_1,
.int_status = GPIO_INT_STATUS_1,
.int_clear = GPIO_INT_CLEAR_1,
.int_en = GPIO_INT_EN_1,
.int_edge = GPIO_INT_EDGE_1,
.int_pos = GPIO_INT_POS_1,
.oe = GPIO_OE_1,
},
{
.out = GPIO_OUT_2,
.in = GPIO_IN_2,
.int_status = GPIO_INT_STATUS_2,
.int_clear = GPIO_INT_CLEAR_2,
.int_en = GPIO_INT_EN_2,
.int_edge = GPIO_INT_EDGE_2,
.int_pos = GPIO_INT_POS_2,
.oe = GPIO_OE_2,
},
{
.out = GPIO_OUT_3,
.in = GPIO_IN_3,
.int_status = GPIO_INT_STATUS_3,
.int_clear = GPIO_INT_CLEAR_3,
.int_en = GPIO_INT_EN_3,
.int_edge = GPIO_INT_EDGE_3,
.int_pos = GPIO_INT_POS_3,
.oe = GPIO_OE_3,
},
{
.out = GPIO_OUT_4,
.in = GPIO_IN_4,
.int_status = GPIO_INT_STATUS_4,
.int_clear = GPIO_INT_CLEAR_4,
.int_en = GPIO_INT_EN_4,
.int_edge = GPIO_INT_EDGE_4,
.int_pos = GPIO_INT_POS_4,
.oe = GPIO_OE_4,
},
};
static gpioregs *find_gpio(unsigned n, unsigned *bit)
{
if(n > 106)
return 0;
if(n > 94) {
*bit = 1 << (n - 95);
return GPIO_REGS + 4;
}
if(n > 67) {
*bit = 1 << (n - 68);
return GPIO_REGS + 3;
}
if(n > 42) {
*bit = 1 << (n - 43);
return GPIO_REGS + 2;
}
if(n > 15) {
*bit = 1 << (n - 16);
return GPIO_REGS + 1;
}
*bit = 1 << n;
return GPIO_REGS + 0;
}
int gpio_config(unsigned n, unsigned flags)
{
gpioregs *r;
unsigned b;
unsigned v;
if ((r = find_gpio(n, &b)) == 0)
return -1;
v = readl(r->oe);
if (flags & GPIO_OUTPUT) {
writel(v | b, r->oe);
} else {
writel(v & (~b), r->oe);
}
return 0;
}
void gpio_set(unsigned n, unsigned on)
{
gpioregs *r;
unsigned b;
unsigned v;
if((r = find_gpio(n, &b)) == 0)
return;
v = readl(r->out);
if(on) {
writel(v | b, r->out);
} else {
writel(v & (~b), r->out);
}
}
int gpio_get(unsigned n)
{
gpioregs *r;
unsigned b;
if((r = find_gpio(n, &b)) == 0) return 0;
return (readl(r->in) & b) ? 1 : 0;
}
bootable/bootloader/lk/platform/msm7k/include/platform/iomap.h
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _PLATFORM_MSM7K_IOMAP_H_
#define _PLATFORM_MSM7K_IOMAP_H_
#define MSM_GPIO1_BASE 0xA9200000
#define MSM_GPIO2_BASE 0xA9300000
#define MSM_UART1_BASE 0xA9A00000
#define MSM_UART2_BASE 0xA9B00000
#define MSM_UART3_BASE 0xA9C00000
#define MSM_VIC_BASE 0xC0000000
#define MSM_GPT_BASE 0xC0100000
#define GPT_REG(off) (MSM_GPT_BASE + (off))
#define GPT_MATCH_VAL GPT_REG(0x0000)
#define GPT_COUNT_VAL GPT_REG(0x0004)
#define GPT_ENABLE GPT_REG(0x0008)
#define GPT_CLEAR GPT_REG(0x000C)
#define DGT_MATCH_VAL GPT_REG(0x0010)
#define DGT_COUNT_VAL GPT_REG(0x0014)
#define DGT_ENABLE GPT_REG(0x0018)
#define DGT_CLEAR GPT_REG(0x001C)
#define SPSS_TIMER_STATUS GPT_REG(0x0034)
#define MSM_CSR_BASE 0xC0100000
#define MSM_CLK_CTL_BASE 0xA8600000
#define MSM_SHARED_BASE 0x00100000
#define MSM_SDC1_BASE 0xA0400000
#define MSM_SDC2_BASE 0xA0500000
#define MSM_SDC3_BASE 0xA0600000
#define MSM_SDC4_BASE 0xA0700000
#endif
bootable/bootloader/lk/platform/msm7k/include/platform/irqs.h
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _PLATFORM_MSM7K_IRQS_H_
#define _PLATFORM_MSM7K_IRQS_H_
#define INT_A9_M2A_0 0
#define INT_A9_M2A_1 1
#define INT_A9_M2A_2 2
#define INT_A9_M2A_3 3
#define INT_A9_M2A_4 4
#define INT_A9_M2A_5 5
#define INT_A9_M2A_6 6
#define INT_GP_TIMER_EXP 7
#define INT_DEBUG_TIMER_EXP 8
#define INT_UART1 9
#define INT_UART2 10
#define INT_UART3 11
#define INT_UART1_RX 12
#define INT_UART2_RX 13
#define INT_UART3_RX 14
#define INT_USB_OTG 15
#define INT_MDDI_PRI 16
#define INT_MDDI_EXT 17
#define INT_MDDI_CLIENT 18
#define INT_MDP 19
#define INT_GRAPHICS 20
#define INT_ADM_AARM 21
#define INT_ADSP_A11 22
#define INT_ADSP_A9_A11 23
#define INT_SDC1_0 24
#define INT_SDC1_1 25
#define INT_SDC2_0 26
#define INT_SDC2_1 27
#define INT_KEYSENSE 28
#define INT_TCHSCRN_SSBI 29
#define INT_TCHSCRN1 30
#define INT_TCHSCRN2 31
#define INT_GPIO_GROUP1 (32 + 0)
#define INT_GPIO_GROUP2 (32 + 1)
#define INT_PWB_I2C (32 + 2)
#define INT_NAND_WR_ER_DONE (32 + 3)
#define INT_NAND_OP_DONE (32 + 4)
#define INT_SOFTRESET (32 + 5)
#define INT_PBUS_ARM11 (32 + 6)
#define INT_AXI_MPU_SMI (32 + 7)
#define INT_AXI_MPU_EBI1 (32 + 8)
#define INT_AD_HSSD (32 + 9)
#define INT_ARM11_PM (32 + 10)
#define INT_ARM11_DMA (32 + 11)
#define INT_TSIF_IRQ (32 + 12)
#define INT_UART1DM_IRQ (32 + 13)
#define INT_UART1DM_RX (32 + 14)
#define INT_USB_HS (32 + 15)
#define INT_SDC3_0 (32 + 16)
#define INT_SDC3_1 (32 + 17)
#define INT_SDC4_0 (32 + 18)
#define INT_SDC4_1 (32 + 19)
#define INT_UART2DM_RX (32 + 20)
#define INT_UART2DM_IRQ (32 + 21)
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
#define NR_IRQS 54
#endif
bootable/bootloader/lk/platform/msm7k/interrupts.c
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <debug.h>
#include <arch/arm.h>
#include <reg.h>
#include <kernel/thread.h>
#include <platform/interrupts.h>
#include <platform/irqs.h>
#include <platform/iomap.h>
#define VIC_REG(off) (MSM_VIC_BASE + (off))
#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
#define VIC_INT_EN0 VIC_REG(0x0010)
#define VIC_INT_EN1 VIC_REG(0x0014)
#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
#define VIC_INT_ENSET0 VIC_REG(0x0030)
#define VIC_INT_ENSET1 VIC_REG(0x0034)
#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
#define VIC_NO_PEND_VAL VIC_REG(0x0060)
#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
#define VIC_SOFTINT0 VIC_REG(0x00C0)
#define VIC_SOFTINT1 VIC_REG(0x00C4)
#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
struct ihandler {
int_handler func;
void *arg;
};
static struct ihandler handler[NR_IRQS];
void platform_init_interrupts(void)
{
writel(0xffffffff, VIC_INT_CLEAR0);
writel(0xffffffff, VIC_INT_CLEAR1);
writel(0, VIC_INT_SELECT0);
writel(0, VIC_INT_SELECT1);
writel(0xffffffff, VIC_INT_TYPE0);
writel(0xffffffff, VIC_INT_TYPE1);
writel(0, VIC_CONFIG);
writel(1, VIC_INT_MASTEREN);
}
enum handler_return platform_irq(struct arm_iframe *frame)
{
unsigned num;
enum handler_return ret;
num = readl(VIC_IRQ_VEC_RD);
num = readl(VIC_IRQ_VEC_PEND_RD);
if (num > NR_IRQS)
return 0;
writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
ret = handler[num].func(handler[num].arg);
writel(0, VIC_IRQ_VEC_WR);
return ret;
}
void platform_fiq(struct arm_iframe *frame)
{
PANIC_UNIMPLEMENTED;
}
status_t mask_interrupt(unsigned int vector)
{
unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
unsigned bit = 1 << (vector & 31);
writel(bit, reg);
return 0;
}
status_t unmask_interrupt(unsigned int vector)
{
unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
unsigned bit = 1 << (vector & 31);
writel(bit, reg);
return 0;
}
void register_int_handler(unsigned int vector, int_handler func, void *arg)
{
if (vector >= NR_IRQS)
return;
enter_critical_section();
handler[vector].func = func;
handler[vector].arg = arg;
exit_critical_section();
}
bootable/bootloader/lk/platform/msm7k/panel.c
+471
View File
@@ -0,0 +1,471 @@
/* Copyright 2007, Google Inc. */
#include <debug.h>
#include <dev/gpio.h>
#include <kernel/thread.h>
#include <mddi.h>
#define MDDI_CLIENT_CORE_BASE 0x108000
#define LCD_CONTROL_BLOCK_BASE 0x110000
#define SPI_BLOCK_BASE 0x120000
#define I2C_BLOCK_BASE 0x130000
#define PWM_BLOCK_BASE 0x140000
#define GPIO_BLOCK_BASE 0x150000
#define SYSTEM_BLOCK1_BASE 0x160000
#define SYSTEM_BLOCK2_BASE 0x170000
#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
#define START (LCD_CONTROL_BLOCK_BASE|0x08)
#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
#define SSICTL (SPI_BLOCK_BASE|0x00)
#define SSITIME (SPI_BLOCK_BASE|0x04)
#define SSITX (SPI_BLOCK_BASE|0x08)
#define SSIRX (SPI_BLOCK_BASE|0x0C)
#define SSIINTC (SPI_BLOCK_BASE|0x10)
#define SSIINTS (SPI_BLOCK_BASE|0x14)
#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
#define SSIID (SPI_BLOCK_BASE|0x20)
#define I2CSETUP (I2C_BLOCK_BASE|0x00)
#define I2CCTRL (I2C_BLOCK_BASE|0x04)
#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
#define TIMERITCR (PWM_BLOCK_BASE|0x60)
#define TIMERITOP (PWM_BLOCK_BASE|0x64)
#define PWMCR (PWM_BLOCK_BASE|0x68)
#define PWMID (PWM_BLOCK_BASE|0x6C)
#define PWMMON (PWM_BLOCK_BASE|0x70)
#define GPIODATA (GPIO_BLOCK_BASE|0x00)
#define GPIODIR (GPIO_BLOCK_BASE|0x04)
#define GPIOIS (GPIO_BLOCK_BASE|0x08)
#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
#define GPIOIE (GPIO_BLOCK_BASE|0x14)
#define GPIORIS (GPIO_BLOCK_BASE|0x18)
#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
#define GPIOIC (GPIO_BLOCK_BASE|0x20)
#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
#define GPIOPC (GPIO_BLOCK_BASE|0x28)
#define GPIOID (GPIO_BLOCK_BASE|0x30)
#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
struct init_table {
unsigned int reg;
unsigned int val;
};
static struct init_table toshiba_480x640_init_table[] = {
{ DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
{ DPSET1, 0x00000113 }, // # MDC.DPSET1
{ DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
{ DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
{ 0, 14 }, // wait_ms(14);
{ SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
{ CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
{ GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
{ GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
{ SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
{ GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
{ SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
{ GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
{ GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
{ GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
{ GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
{ GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
{ GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
{ DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
{ TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
{ PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
//{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
#if 0
{ PWM0OFF, 0x00001387 }, // SURF 100% backlight
{ PWM0OFF, 0x00000000 }, // FFA 100% backlight
#endif
{ PWM0OFF, 0x000009C3 }, // 50% BL
{ TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
{ TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
//{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
{ PWM1OFF, 0x00001387 },
{ TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
{ TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
{ PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
{ 0, 1 }, // wait_ms(1);
{ SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
{ SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
{ SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
{ SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
{ 0, 1 }, // wait_ms(1);
{ SSITX, 0x00000000 }, // # SPI.SSITX
{ 0, 1 }, // wait_ms(1);
{ SSITX, 0x00000000 }, // # SPI.SSITX
{ 0, 1 }, // wait_ms(1);
{ SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
{ SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
{ SSITX, 0x00080036 }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Memory access control
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800BB }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Display mode setup(2)
{ SSITX, 0x0008003A }, // # Command setting of SPI block
{ SSITX, 0x00000160 }, // # RGB Interface data format
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800BF }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Drivnig method
{ SSITX, 0x000800B1 }, // # Command setting of SPI block
{ SSITX, 0x0000015D }, // # Booster operation setup
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B2 }, // # Command setting of SPI block
{ SSITX, 0x00000133 }, // # Booster mode setup
{ SSITX, 0x000800B3 }, // # Command setting of SPI block
{ SSITX, 0x00000122 }, // # Booster frequencies setup
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B4 }, // # Command setting of SPI block
{ SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
{ SSITX, 0x000800B5 }, // # Command setting of SPI block
{ SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B6 }, // # Command setting of SPI block
{ SSITX, 0x00000128 }, // # VCOM Voltage adjustment
{ SSITX, 0x000800B7 }, // # Command setting of SPI block
{ SSITX, 0x00000103 }, // # Configure an external display signal
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B9 }, // # Command setting of SPI block
{ SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
{ SSITX, 0x000800BD }, // # Command setting of SPI block
{ SSITX, 0x00000102 }, // # ASW signal control
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800BE }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
{ SSITX, 0x000800C0 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C1 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
{ SSITX, 0x000800C2 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C3 }, // # Command setting of SPI block
{ SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
{ SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C4 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
{ SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C5 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
{ SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C6 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
{ SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C7 }, // # Command setting of SPI block
{ SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
{ SSITX, 0x00000143 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C8 }, // # Command setting of SPI block
{ SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
{ SSITX, 0x000800C9 }, // # Command setting of SPI block
{ SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800CA }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800EC }, // # Command setting of SPI block
{ SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
{ SSITX, 0x00000118 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800CF }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D0 }, // # Command setting of SPI block
{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
{ SSITX, 0x00000104 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D1 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D2 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
{ SSITX, 0x0000013A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D3 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
{ SSITX, 0x0000013A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D4 }, // # Command setting of SPI block
{ SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
{ SSITX, 0x0000016E }, //
{ 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
{ SSITX, 0x000800D5 }, // # Command setting of SPI block
{ SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800ED }, // # Command setting of SPI block
{ SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
{ SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D6 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D7 }, // # Command setting of SPI block
{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D8 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D9 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x00000114 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800DE }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x00000114 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800DF }, // # Command setting of SPI block
{ SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x0000013F }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E0 }, // # Command setting of SPI block
{ SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x000800E2 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E3 }, // # Command setting of SPI block
{ SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E4 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
{ SSITX, 0x00000103 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E5 }, // # Command setting of SPI block
{ SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
{ SSITX, 0x00000104 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E6 }, // # Command setting of SPI block
{ SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E7 }, // # Command setting of SPI block
{ SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
{ SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E8 }, // # Command setting of SPI block
{ SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
{ CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
{ START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
{ WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
{ RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
{ PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
{ VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
{ ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ ASY_DATB, 0x00000001 }, // # Oscillator start
{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
{ 0, 10 }, // wait_ms(10);
{ ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(�@*NOTE2
{ ASY_DATB, 0x80000000 }, //
{ ASY_DATC, 0x80000000 }, //
{ ASY_DATD, 0x80000000 }, //
{ ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
{ ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
{ ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ ASY_DATB, 0x00004005 }, // # LCD driver control
{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
{ 0, 20 }, // wait_ms(20);
{ ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ ASY_DATB, 0x00000000 }, // # LTPS I/F control
{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
{ VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
{ PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
/******************************/
{ VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
{ PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
{ BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
{ BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
{ BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
{ BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
{ CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
{ PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
{ PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
{ PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
{ MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
{ HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
{ HSW, 0x00000003 }, // LCD.HSW
{ HDE_START, 0x00000007 }, // LCD.HDE_START
{ HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
{ VCYCLE, 0x00000285 }, // LCD.VCYCLE
{ VSW, 0x00000001 }, // LCD.VSW
{ VDE_START, 0x00000003 }, // LCD.VDE_START
{ VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
{ START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
{ 0, 10 }, // wait_ms( 10 );
{ SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
{ SSITX, 0x00000180 }, // Display data setup
{ SSITX, 0x0008003B }, // Command setting of SPI block
{ SSITX, 0x00000100 }, // Quad Data configuration - VGA
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
{ SSITX, 0x000800B0 }, // Command setting of SPI block
{ SSITX, 0x00000116 }, // Power supply ON/OFF control
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
{ SSITX, 0x000800B8 }, // Command setting of SPI block
{ SSITX, 0x000801FF }, // Output control
{ SSITX, 0x000001F5 },
{ 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
{ SSITX, 0x00000011 }, // wait_ms(-out (Command only)
{ SSITX, 0x00000029 }, // Display on (Command only)
{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
{ 0, 0 }
};
static void _panel_init(struct init_table *init_table)
{
unsigned n;
dprintf(INFO, "panel_init()\n");
n = 0;
while (init_table[n].reg != 0 || init_table[n].val != 0) {
if (init_table[n].reg != 0)
mddi_remote_write(init_table[n].val, init_table[n].reg);
else
mdelay(init_table[n].val);
n++;
}
dprintf(INFO, "panel_init() done\n");
}
void panel_init(struct mddi_client_caps *client_caps)
{
switch(client_caps->manufacturer_name) {
case 0xd263: // Toshiba
dprintf(INFO, "Found Toshiba panel\n");
_panel_init(toshiba_480x640_init_table);
break;
case 0x4474: //??
if (client_caps->product_code == 0xc065)
dprintf(INFO, "Found WVGA panel\n");
break;
}
}
void panel_poweron(void)
{
gpio_set(88, 0);
gpio_config(88, GPIO_OUTPUT);
udelay(10);
gpio_set(88, 1);
mdelay(10);
//mdelay(1000); // uncomment for second stage boot
}
void panel_backlight(int on)
{}
bootable/bootloader/lk/platform/msm7k/platform.c
+115
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@@ -0,0 +1,115 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Copyright (c) 2009-2010, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <reg.h>
#include <debug.h>
#include <kernel/thread.h>
#include <platform/debug.h>
#include <platform/iomap.h>
#include <mddi.h>
#include <dev/fbcon.h>
#include <arch/arm/mmu.h>
#define MB (1024*1024)
static struct fbcon_config *fb_config;
static uint32_t ticks_per_sec = 0;
void platform_init_interrupts(void);
void platform_init_timer();
void uart3_clock_init(void);
void uart_init(void);
void acpu_clock_init(void);
void mddi_clock_init(unsigned num, unsigned rate);
void platform_early_init(void)
{
platform_init_interrupts();
platform_init_timer();
}
void platform_init(void)
{
dprintf(INFO, "platform_init()\n");
acpu_clock_init();
}
void display_init(void)
{
#if DISPLAY_TYPE_MDDI
fb_config = mddi_init();
ASSERT(fb_config);
fbcon_setup(fb_config);
#endif
#if DISPLAY_TYPE_LCDC
fb_config = lcdc_init();
ASSERT(fb_config);
fbcon_setup(fb_config);
#endif
}
/* Setup memory for this platform */
void platform_init_mmu_mappings(void)
{
uint32_t sections = 1152;
/* Map io mapped peripherals as device non-shared memory */
while (sections--)
{
arm_mmu_map_section(0x88000000 + sections*MB,
0x88000000 + sections*MB,
(MMU_MEMORY_TYPE_DEVICE_NON_SHARED |
MMU_MEMORY_AP_READ_WRITE));
}
}
/* Initialize DGT timer */
void platform_init_timer(void)
{
/* disable timer */
writel(0, DGT_ENABLE);
ticks_per_sec = 19200000; /* Uses TCXO (19.2 MHz) */
}
/* Returns timer ticks per sec */
uint32_t platform_tick_rate(void)
{
return ticks_per_sec;
}
bootable/bootloader/lk/platform/msm7k/rules.mk
+24
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@@ -0,0 +1,24 @@
LOCAL_DIR := $(GET_LOCAL_DIR)
ARCH := arm
ARM_CPU := arm1136j-s
CPU := generic
MMC_SLOT := 1
DEFINES += MMC_SLOT=$(MMC_SLOT)
INCLUDES += -I$(LOCAL_DIR)/include
MODULES += dev/fbcon
OBJS += \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/interrupts.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/panel.o \
$(LOCAL_DIR)/acpuclock.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
include platform/msm_shared/rules.mk