217 lines
6.5 KiB
C
217 lines
6.5 KiB
C
/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <kernel/thread.h>
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#include <platform/iomap.h>
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#include <reg.h>
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#include <debug.h>
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#include <mmc.h>
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#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
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#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
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#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
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#define VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
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#define PLL2_L_VAL_ADDR (MSM_CLK_CTL_BASE + 0x33C)
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#define SRC_SEL_PLL1 1 /* PLL1. */
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#define SRC_SEL_PLL2 2 /* PLL2. */
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#define SRC_SEL_PLL3 3 /* PLL3. Used for 7x25. */
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#define DIV_4 3
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#define DIV_2 1
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#define WAIT_CNT 100
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#define VDD_LEVEL 7
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#define MIN_AXI_HZ 120000000
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#define ACPU_800MHZ 41
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void pll_request(unsigned pll, unsigned enable);
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void axi_clock_init(unsigned rate);
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/* The stepping frequencies have been choosen to make sure the step
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* is <= 256 MHz for both turbo mode and normal mode targets. The
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* table also assumes the ACPU is running at TCXO freq and AHB div is
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* set to DIV_1.
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*
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* To use the tables:
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* - Start at location 0/1 depending on clock source sel bit.
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* - Set values till end of table skipping every other entry.
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* - When you reach the end of the table, you are done scaling.
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*
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* TODO: Need to fix SRC_SEL_PLL1 for 7x25.
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*/
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uint32_t const clk_cntl_reg_val_7625[] = {
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL3 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL3 << 12) | (DIV_2 << 8),
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};
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uint32_t const clk_cntl_reg_val_7627[] = {
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
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};
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uint32_t const clk_cntl_reg_val_7627T[] = {
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_4,
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_4 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 12) | (DIV_2 << 8),
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(WAIT_CNT << 16) | (SRC_SEL_PLL1 << 4) | DIV_2,
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(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4),
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(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12),
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};
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/* Using DIV_4 for all cases to avoid worrying about turbo vs. normal
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* mode. Able to use DIV_4 for all steps because it's the largest AND
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* the final value. */
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uint32_t const clk_sel_reg_val[] = {
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DIV_4 << 1 | 1,
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DIV_4 << 1 | 0,
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DIV_4 << 1 | 0,
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DIV_4 << 1 | 1,
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DIV_4 << 1 | 1,
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DIV_4 << 1 | 0,
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};
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/* enum for SDC CLK IDs */
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enum
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{
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SDC1_CLK = 19,
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SDC1_PCLK = 20,
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SDC2_CLK = 21,
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SDC2_PCLK = 22,
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SDC3_CLK = 23,
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SDC3_PCLK = 24,
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SDC4_CLK = 25,
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SDC4_PCLK = 26
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};
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/* Zero'th entry is dummy */
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static uint8_t sdc_clk[] = {0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK};
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static uint8_t sdc_pclk[] = {0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK};
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void mdelay(unsigned msecs);
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void acpu_clock_init(void)
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{
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unsigned i,clk;
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#if (!ENABLE_NANDWRITE)
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int *modem_stat_check = (MSM_SHARED_BASE + 0x14);
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/* Wait for modem to be ready before clock init */
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while (readl(modem_stat_check) != 1);
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#endif
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/* Increase VDD level to the final value. */
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writel((1 << 7) | (VDD_LEVEL << 3), VDD_SVS_PLEVEL_ADDR);
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#if (!ENABLE_NANDWRITE)
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thread_sleep(1);
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#else
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mdelay(1);
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#endif
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/* Read clock source select bit. */
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i = readl(A11S_CLK_SEL_ADDR) & 1;
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clk = readl(PLL2_L_VAL_ADDR) & 0x3F;
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/* Jump into table and set every other entry. */
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for(; i < ARRAY_SIZE(clk_cntl_reg_val_7627); i += 2) {
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#ifdef ENABLE_PLL3
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writel(clk_cntl_reg_val_7625[i], A11S_CLK_CNTL_ADDR);
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#else
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if(clk == ACPU_800MHZ)
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writel(clk_cntl_reg_val_7627T[i], A11S_CLK_CNTL_ADDR);
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else
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writel(clk_cntl_reg_val_7627[i], A11S_CLK_CNTL_ADDR);
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#endif
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/* Would need a dmb() here but the whole address space is
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* strongly ordered, so it should be fine.
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*/
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writel(clk_sel_reg_val[i], A11S_CLK_SEL_ADDR);
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#if (!ENABLE_NANDWRITE)
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thread_sleep(1);
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#else
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mdelay(1);
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#endif
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}
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}
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/* Configure MMC clock */
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void clock_config_mmc(uint32_t interface, uint32_t freq)
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{
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uint32_t reg = 0;
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if( mmc_clock_set_rate(sdc_clk[interface], freq) < 0 )
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{
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dprintf(CRITICAL, "Failure setting clock rate for MCLK - "
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"clk_rate: %d\n!", freq);
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ASSERT(0);
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}
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/* enable clock */
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if( mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0 )
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{
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dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
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ASSERT(0);
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}
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reg |= MMC_BOOT_MCI_CLK_ENABLE;
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reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
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reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
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writel( reg, MMC_BOOT_MCI_CLK );
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/* Wait for the MMC_BOOT_MCI_CLK write to go through. */
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mmc_mclk_reg_wr_delay();
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/* Wait 1 ms to provide the free running SD CLK to the card. */
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mdelay(1);
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}
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/* Intialize MMC clock */
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void clock_init_mmc(uint32_t interface)
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{
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if( mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0 )
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{
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dprintf(CRITICAL, "Failure enabling PCLK!\n");
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ASSERT(0);
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}
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}
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