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M7350v7_en_gpl

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T
2024-09-09 08:59:52 +00:00
parent f75098198c
commit 46ba6f09ec
1372 changed files with 1231198 additions and 1184 deletions
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/HalPhyRf_AP.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/HalPhyRf_AP.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
#include "phydm_PowerTracking_AP.h"
#if (RTL8814A_SUPPORT == 1)
#include "rtl8814a/PhyDM_IQK_8814A.h"
#endif
#if (RTL8822B_SUPPORT == 1)
#include "rtl8822b/phydm_iqk_8822b.h"
#endif
typedef enum _PWRTRACK_CONTROL_METHOD {
BBSWING,
TXAGC,
MIX_MODE,
TSSI_MODE
} PWRTRACK_METHOD;
typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte);
typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte);
typedef VOID (*FuncLCK)(PVOID);
//refine by YuChen for 8814A
typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*);
typedef struct _TXPWRTRACK_CFG {
u1Byte SwingTableSize_CCK;
u1Byte SwingTableSize_OFDM;
u1Byte Threshold_IQK;
u1Byte Threshold_DPK;
u1Byte AverageThermalNum;
u1Byte RfPathCount;
u4Byte ThermalRegAddr;
FuncSetPwr ODM_TxPwrTrackSetPwr;
FuncIQK DoIQK;
FuncLCK PHY_LCCalibrate;
FuncSwing GetDeltaSwingTable;
FuncSwing8814only GetDeltaSwingTable8814only;
} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
VOID
ConfigureTxpowerTrack(
IN PVOID pDM_VOID,
OUT PTXPWRTRACK_CFG pConfig
);
VOID
ODM_TXPowerTrackingCallback_ThermalMeter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PVOID pDM_VOID
#else
IN PADAPTER Adapter
#endif
);
#if (RTL8192E_SUPPORT==1)
VOID
ODM_TXPowerTrackingCallback_ThermalMeter_92E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PVOID pDM_VOID
#else
IN PADAPTER Adapter
#endif
);
#endif
#if (RTL8814A_SUPPORT == 1)
VOID
ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PVOID pDM_VOID
#else
IN PADAPTER Adapter
#endif
);
#elif ODM_IC_11AC_SERIES_SUPPORT
VOID
ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PVOID pDM_VOID
#else
IN PADAPTER Adapter
#endif
);
#endif
#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M )
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
#define MAX_TOLERANCE 5
#define IQK_DELAY_TIME 1 //ms
//
// BB/MAC/RF other monitor API
//
void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter,
IN BOOLEAN bEnableMonitorMode );
//
// IQ calibrate
//
void
PHY_IQCalibrate_8192C( IN PADAPTER pAdapter,
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8192C( IN PADAPTER pAdapter);
//
// AP calibrate
//
void
PHY_APCalibrate_8192C( IN PADAPTER pAdapter,
IN s1Byte delta);
#endif
#define ODM_TARGET_CHNL_NUM_2G_5G 59
VOID
ODM_ResetIQKResult(
IN PVOID pDM_VOID
);
u1Byte
ODM_GetRightChnlPlaceforIQK(
IN u1Byte chnl
);
void phydm_rf_init(IN PVOID pDM_VOID);
void phydm_rf_watchdog(IN PVOID pDM_VOID);
#endif // #ifndef __HAL_PHY_RF_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/Mp_Precomp.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/PhyDM_Adaptivity.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if WPP_SOFTWARE_TRACE
#include "PhyDM_Adaptivity.tmh"
#endif
#endif
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) {
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) {
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH));
} else
#endif
{
if (Adaptivity->DynamicLinkAdaptivity == TRUE) {
if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) {
Phydm_NHMCounterStatistics(pDM_Odm);
Phydm_CheckEnvironment(pDM_Odm);
} else if (!pDM_Odm->bLinked)
Adaptivity->bCheck = FALSE;
} else {
pDM_Odm->Adaptivity_enable = TRUE;
if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
}
}
} else {
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
BOOLEAN
Phydm_CheckChannelPlan(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
if (pMgntInfo->RegEnableAdaptivity == 2) {
if (pDM_Odm->Carrier_Sense_enable == FALSE) { /*check domain Code for Adaptivity or CarrierSense*/
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
} else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
} else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n"));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
}
} else {
if ((*pDM_Odm->pBandType == ODM_BAND_5G) &&
!(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
}
else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) &&
!(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
} else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n"));
pDM_Odm->Adaptivity_enable = FALSE;
pDM_Odm->adaptivity_flag = FALSE;
return TRUE;
}
}
}
return FALSE;
}
#endif
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
/*PHY parameters initialize for n series*/
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/
ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/
}
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
/*PHY parameters initialize for ac series*/
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/
ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/
ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/
}
#endif
}
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
return;
/*Get NHM report*/
Phydm_GetNHMCounterStatistics(pDM_Odm);
/*Reset NHM counter*/
Phydm_NHMCounterStatisticsReset(pDM_Odm);
}
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte value32 = 0;
#if (RTL8195A_SUPPORT == 0)
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord);
else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
#endif
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord);
pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0);
pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8);
}
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1);
}
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0);
ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1);
}
#endif
}
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)L2H|(u1Byte)H2L<<16));
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)L2H|(u1Byte)H2L<<8));
#endif
}
VOID
Phydm_SetLNA(
IN PVOID pDM_VOID,
IN PhyDM_set_LNA type
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E)) {
if (type == PhyDM_disable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
}
} else if (type == PhyDM_enable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
}
}
} else if (pDM_Odm->SupportICType & ODM_RTL8723B) {
if (type == PhyDM_disable_LNA) {
/*S0*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
/*S1*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
} else if (type == PhyDM_enable_LNA) {
/*S0*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
/*S1*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
}
} else if (pDM_Odm->SupportICType & ODM_RTL8812) {
if (type == PhyDM_disable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
}
} else if (type == PhyDM_enable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0);
}
}
} else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) {
if (type == PhyDM_disable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
} else if (type == PhyDM_enable_LNA) {
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
}
}
}
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
}
}
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
if (pDM_Odm->RFType > ODM_1T1R) {
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/
}
}
#endif
}
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (State == PhyDM_IGNORE_EDCCA) {
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); /*ignore EDCCA reg520[15]=1*/
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); /*reg524[11]=0*/
} else { /*don't set MAC ignore EDCCA signal*/
ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0*/
ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); /*reg524[11]=1 */
}
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State));
}
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u2Byte Base = 0;
Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1;
if (Base != 0) {
pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base;
pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base;
}
if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100)
return TRUE; /*clean environment*/
else
return FALSE; /*noisy environment*/
}
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
BOOLEAN isCleanEnvironment = FALSE;
if (Adaptivity->bFirstLink == TRUE) {
if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
Adaptivity->bFirstLink = FALSE;
return;
} else {
if (Adaptivity->NHMWait < 3) { /*Start enter NHM after 4 NHMWait*/
Adaptivity->NHMWait++;
Phydm_NHMCounterStatistics(pDM_Odm);
return;
} else {
Phydm_NHMCounterStatistics(pDM_Odm);
isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm);
if (isCleanEnvironment == TRUE) {
pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup; /*adaptivity mode*/
pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;
pDM_Odm->Adaptivity_enable = TRUE;
if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
pDM_Odm->adaptivity_flag = FALSE;
else
pDM_Odm->adaptivity_flag = TRUE;
} else {
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; /*mode2*/
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
pDM_Odm->adaptivity_flag = FALSE;
pDM_Odm->Adaptivity_enable = FALSE;
}
Adaptivity->NHMWait = 0;
Adaptivity->bFirstLink = TRUE;
Adaptivity->bCheck = TRUE;
}
}
}
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
u4Byte value32 = 0;
u1Byte cnt, IGI = 0x45; /*IGI = 0x50 for cal EDCCA lower bound*/
u1Byte txEdcca1 = 0, txEdcca0 = 0;
BOOLEAN bAdjust = TRUE;
s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32;
s1Byte Diff;
if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
Phydm_SetLNA(pDM_Odm, PhyDM_disable_LNA);
else {
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
}
Diff = IGI_target - (s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if (TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
ODM_delay_ms(5);
while (bAdjust) {
for (cnt = 0; cnt < 20; cnt++) {
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord);
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord);
#endif
if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E)))
txEdcca1 = txEdcca1 + 1;
else if (value32 & BIT29)
txEdcca1 = txEdcca1 + 1;
else
txEdcca0 = txEdcca0 + 1;
}
if (txEdcca1 > 1) {
IGI = IGI - 1;
TH_L2H_dmc = TH_L2H_dmc + 1;
if (TH_L2H_dmc > 10)
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
if (TH_L2H_dmc == 10) {
bAdjust = FALSE;
Adaptivity->H2L_lb = TH_H2L_dmc;
Adaptivity->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
}
txEdcca1 = 0;
txEdcca0 = 0;
} else {
bAdjust = FALSE;
Adaptivity->H2L_lb = TH_H2L_dmc;
Adaptivity->L2H_lb = TH_L2H_dmc;
pDM_Odm->Adaptivity_IGI_upper = IGI;
txEdcca1 = 0;
txEdcca0 = 0;
}
}
pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff;
Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff;
Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff;
if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A))
Phydm_SetLNA(pDM_Odm, PhyDM_enable_LNA);
else {
Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
}
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); /*resume to no link state*/
}
BOOLEAN
phydm_reSearchCondition(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
/*PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);*/
u1Byte Adaptivity_IGI_upper;
/*s1Byte TH_L2H_dmc, IGI_target = 0x32;*/
/*s1Byte Diff;*/
Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper + pDM_Odm->DCbackoff;
/*TH_L2H_dmc = 10;*/
/*Diff = TH_L2H_dmc - pDM_Odm->TH_L2H_ini;*/
/*lowest_IGI_upper = IGI_target - Diff;*/
/*if ((Adaptivity_IGI_upper - lowest_IGI_upper) <= 5)*/
if (Adaptivity_IGI_upper <= 0x26)
return TRUE;
else
return FALSE;
}
VOID
phydm_adaptivityInfoInit(
IN PVOID pDM_VOID,
IN PHYDM_ADAPINFO_E CmnInfo,
IN u4Byte Value
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
switch (CmnInfo) {
case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
pDM_Odm->Carrier_Sense_enable = (BOOLEAN)Value;
break;
case PHYDM_ADAPINFO_DCBACKOFF:
pDM_Odm->DCbackoff = (u1Byte)Value;
break;
case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)Value;
break;
case PHYDM_ADAPINFO_TH_L2H_INI:
pDM_Odm->TH_L2H_ini = (s1Byte)Value;
break;
case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
pDM_Odm->TH_EDCCA_HL_diff = (s1Byte)Value;
break;
case PHYDM_ADAPINFO_AP_NUM_TH:
Adaptivity->APNumTH = (u1Byte)Value;
break;
default:
break;
}
}
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
s1Byte IGItarget = 0x32;
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
if (pDM_Odm->Carrier_Sense_enable == FALSE) {
if (pDM_Odm->TH_L2H_ini == 0)
pDM_Odm->TH_L2H_ini = 0xf5;
} else
pDM_Odm->TH_L2H_ini = 0xa;
if (pDM_Odm->TH_EDCCA_HL_diff == 0)
pDM_Odm->TH_EDCCA_HL_diff = 7;
pDM_Odm->EDCCA_enable = TRUE; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/
#elif (DM_ODM_SUPPORT_TYPE & ODM_AP)
prtl8192cd_priv priv = pDM_Odm->priv;
if (pDM_Odm->Carrier_Sense_enable) {
pDM_Odm->TH_L2H_ini = 0xa;
pDM_Odm->TH_EDCCA_HL_diff = 7;
} else {
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_default; /*set by mib*/
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_default;
}
if (priv->pshare->rf_ft_var.adaptivity_enable == 2)
Adaptivity->DynamicLinkAdaptivity = TRUE;
else
Adaptivity->DynamicLinkAdaptivity = FALSE;
#endif
pDM_Odm->Adaptivity_IGI_upper = 0;
pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/
pDM_Odm->TH_L2H_ini_mode2 = 20;
pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8;
Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini;
Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff;
Adaptivity->IGI_Base = 0x32;
Adaptivity->IGI_target = 0x1c;
Adaptivity->H2L_lb = 0;
Adaptivity->L2H_lb = 0;
Adaptivity->NHMWait = 0;
Adaptivity->bCheck = FALSE;
Adaptivity->bFirstLink = TRUE;
Adaptivity->AdajustIGILevel = 0;
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
/*Search pwdB lower bound*/
if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208);
#if (RTL8195A_SUPPORT == 0)
else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209);
#endif
if (pDM_Odm->SupportICType & ODM_IC_11N_GAIN_IDX_EDCCA) {
/*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
}
#if (RTL8195A_SUPPORT == 0)
if (pDM_Odm->SupportICType & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/
/*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/
ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
}
if (!(pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
Phydm_SearchPwdBLowerBound(pDM_Odm);
if (phydm_reSearchCondition(pDM_Odm))
Phydm_SearchPwdBLowerBound(pDM_Odm);
}
#endif
/*we need to consider PwdB upper bound for 8814 later IC*/
Adaptivity->AdajustIGILevel = (u1Byte)((pDM_Odm->TH_L2H_ini + IGItarget) - PwdBUpperBound + DFIRloss); /*IGI = L2H - PwdB - DFIRloss*/
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x, Adaptivity->AdajustIGILevel = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, Adaptivity->AdajustIGILevel));
}
VOID
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
s1Byte TH_L2H_dmc, TH_H2L_dmc;
s1Byte Diff = 0, IGI_target;
PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER pAdapter = pDM_Odm->Adapter;
BOOLEAN bFwCurrentInPSMode = FALSE;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
/*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/
if (bFwCurrentInPSMode)
return;
#endif
if (pDM_Odm->EDCCA_enable == FALSE) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n"));
return;
}
if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) {
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n"));
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
else{
if (Phydm_CheckChannelPlan(pDM_Odm) || (pDM_Odm->APTotalNum > Adaptivity->APNumTH)) {
pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2;
pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2;
} else {
pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup;
pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup;
}
}
#endif
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n"));
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n",
Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff));
#if (RTL8195A_SUPPORT == 0)
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
/*fix AC series when enable EDCCA hang issue*/
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/
ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/
}
#endif
if (*pDM_Odm->pBandWidth == ODM_BW20M) /*CHANNEL_WIDTH_20*/
IGI_target = Adaptivity->IGI_Base;
else if (*pDM_Odm->pBandWidth == ODM_BW40M)
IGI_target = Adaptivity->IGI_Base + 2;
#if (RTL8195A_SUPPORT == 0)
else if (*pDM_Odm->pBandWidth == ODM_BW80M)
IGI_target = Adaptivity->IGI_Base + 2;
#endif
else
IGI_target = Adaptivity->IGI_Base;
Adaptivity->IGI_target = (u1Byte) IGI_target;
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d\n",
(*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity));
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, Adaptivity->AdajustIGILevel= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n",
pDM_Odm->RSSI_Min, Adaptivity->AdajustIGILevel, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable));
if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) {
Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f);
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n"));
return;
}
if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
if ((Adaptivity->AdajustIGILevel > IGI) && (pDM_Odm->Adaptivity_enable == TRUE))
Diff = Adaptivity->AdajustIGILevel - IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
}
#if (RTL8195A_SUPPORT == 0)
else {
Diff = IGI_target - (s1Byte)IGI;
TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
if (TH_L2H_dmc > 10 && (pDM_Odm->Adaptivity_enable == TRUE))
TH_L2H_dmc = 10;
TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
/*replace lower bound to prevent EDCCA always equal 1*/
if (TH_H2L_dmc < Adaptivity->H2L_lb)
TH_H2L_dmc = Adaptivity->H2L_lb;
if (TH_L2H_dmc < Adaptivity->L2H_lb)
TH_L2H_dmc = Adaptivity->L2H_lb;
}
#endif
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc));
ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb));
Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc);
return;
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_AdaptivityBSOD(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo);
u1Byte count = 0;
u4Byte u4Value;
/*
1. turn off RF (TRX Mux in standby mode)
2. H2C mac id drop
3. ignore EDCCA
4. wait for clear FIFO
5. don't ignore EDCCA
6. turn on RF (TRX Mux in TRx mdoe)
7. H2C mac id resume
*/
RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n"));
pAdapter->dropPktByMacIdCnt++;
pMgntInfo->bDropPktInProgress = TRUE;
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value));
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
#if 1
/*Standby mode*/
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
/*H2C mac id drop*/
MacIdIndicateDisconnect(pAdapter);
/*Ignore EDCCA*/
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
delay_ms(50);
count = 5;
#else
do {
u8Byte diffTime, curTime, oldestTime;
u1Byte queueIdx
//3 Standby mode
Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
//3 H2C mac id drop
MacIdIndicateDisconnect(pAdapter);
//3 Ignore EDCCA
Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA);
count++;
delay_ms(10);
// Check latest packet
curTime = PlatformGetCurrentTime();
oldestTime = 0xFFFFFFFFFFFFFFFF;
for (queueIdx = 0; queueIdx < MAX_TX_QUEUE; queueIdx++) {
if (!IS_DATA_QUEUE(queueIdx))
continue;
if (!pAdapter->bTcbBusyQEmpty[queueIdx]) {
RT_TRACE(COMP_MLME, DBG_WARNING, ("oldestTime = %llu\n", oldestTime));
RT_TRACE(COMP_MLME, DBG_WARNING, ("Q[%d] = %llu\n", queueIdx, pAdapter->firstTcbSysTime[queueIdx]));
if (pAdapter->firstTcbSysTime[queueIdx] < oldestTime)
oldestTime = pAdapter->firstTcbSysTime[queueIdx];
}
}
diffTime = curTime - oldestTime;
RT_TRACE(COMP_MLME, DBG_WARNING, ("diff s = %llu\n", (diffTime / 1000000)));
} while (((diffTime / 1000000) >= 4) && (oldestTime != 0xFFFFFFFFFFFFFFFF));
#endif
/*Resume EDCCA*/
Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA);
/*Turn on TRx mode*/
Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE);
ODM_Write_DIG(pDM_Odm, 0x20);
/*Resume H2C macid*/
MacIdRecoverMediaStatus(pAdapter);
pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value));
RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value));
pMgntInfo->bDropPktInProgress = FALSE;
RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10));
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/PhyDM_Adaptivity.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "9.1" /*20150812 by YuChen*/
#define PwdBUpperBound 7
#define DFIRloss 5
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
typedef enum _tag_PhyDM_REGULATION_Type {
REGULATION_FCC = 0,
REGULATION_MKK = 1,
REGULATION_ETSI = 2,
REGULATION_WW = 3,
MAX_REGULATION_NUM = 4
} PhyDM_REGULATION_TYPE;
#endif
typedef enum _PHYDM_ADAPTIVITY_Info_Definition {
PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0,
PHYDM_ADAPINFO_DCBACKOFF,
PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY,
PHYDM_ADAPINFO_TH_L2H_INI,
PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF,
PHYDM_ADAPINFO_AP_NUM_TH
} PHYDM_ADAPINFO_E;
typedef enum tag_PhyDM_set_LNA {
PhyDM_disable_LNA = 0,
PhyDM_enable_LNA = 1,
} PhyDM_set_LNA;
typedef enum tag_PhyDM_TRx_MUX_Type
{
PhyDM_SHUTDOWN = 0,
PhyDM_STANDBY_MODE = 1,
PhyDM_TX_MODE = 2,
PhyDM_RX_MODE = 3
}PhyDM_Trx_MUX_Type;
typedef enum tag_PhyDM_MACEDCCA_Type
{
PhyDM_IGNORE_EDCCA = 0,
PhyDM_DONT_IGNORE_EDCCA = 1
}PhyDM_MACEDCCA_Type;
typedef struct _ADAPTIVITY_STATISTICS {
s1Byte TH_L2H_ini_backup;
s1Byte TH_EDCCA_HL_diff_backup;
s1Byte IGI_Base;
u1Byte IGI_target;
u1Byte NHMWait;
s1Byte H2L_lb;
s1Byte L2H_lb;
BOOLEAN bFirstLink;
BOOLEAN bCheck;
BOOLEAN DynamicLinkAdaptivity;
u1Byte APNumTH;
u1Byte AdajustIGILevel;
} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS;
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
);
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
);
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
);
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
);
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
);
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
);
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
);
VOID
phydm_adaptivityInfoInit(
IN PVOID pDM_VOID,
IN PHYDM_ADAPINFO_E CmnInfo,
IN u4Byte Value
);
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
);
VOID
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_DisableEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_DynamicEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_AdaptivityBSOD(
IN PVOID pDM_VOID
);
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm.h
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_ACS.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_ACS.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#define ACS_VERSION "1.1" /*20150729 by YuChen*/
#define CLM_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
// For phydm_AutoChannelSelectSettingAP()
#define STORE_DEFAULT_NHM_SETTING 0
#define RESTORE_DEFAULT_NHM_SETTING 1
#define ACS_NHM_SETTING 2
typedef struct _ACS_
{
BOOLEAN bForceACSResult;
u1Byte CleanChannel_2G;
u1Byte CleanChannel_5G;
u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];
#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
u1Byte ACS_Step;
// NHM Count 0-11
u1Byte NHM_Cnt[14][11];
// AC-Series, for storing previous setting
u4Byte Reg0x990;
u4Byte Reg0x994;
u4Byte Reg0x998;
u4Byte Reg0x99C;
u1Byte Reg0x9A0; // u1Byte
// N-Series, for storing previous setting
u4Byte Reg0x890;
u4Byte Reg0x894;
u4Byte Reg0x898;
u4Byte Reg0x89C;
u1Byte Reg0xE28; // u1Byte
#endif
}ACS, *PACS;
VOID
odm_AutoChannelSelectInit(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelectReset(
IN PVOID pDM_VOID
);
VOID
odm_AutoChannelSelect(
IN PVOID pDM_VOID,
IN u1Byte Channel
);
u1Byte
ODM_GetAutoChannelSelectResult(
IN PVOID pDM_VOID,
IN u1Byte Band
);
#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
VOID
phydm_AutoChannelSelectSettingAP(
IN PVOID pDM_VOID,
IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING
IN u4Byte acs_step
);
VOID
phydm_GetNHMStatisticsAP(
IN PVOID pDM_VOID,
IN u4Byte idx, // @ 2G, Real channel number = idx+1
IN u4Byte acs_step
);
#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
VOID
phydm_CLMInit(
IN PVOID pDM_VOID,
IN u2Byte sampleNum
);
VOID
phydm_CLMtrigger(
IN PVOID pDM_VOID
);
BOOLEAN
phydm_checkCLMready(
IN PVOID pDM_VOID
);
u2Byte
phydm_getCLMresult(
IN PVOID pDM_VOID
);
#endif //#ifndef __PHYDMACS_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_AntDect.c
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
#if(defined(CONFIG_ANT_DETECTION))
//IS_ANT_DETECT_SUPPORT_SINGLE_TONE(Adapter)
//IS_ANT_DETECT_SUPPORT_RSSI(Adapter)
//IS_ANT_DETECT_SUPPORT_PSD(Adapter)
//1 [1. Single Tone Method] ===================================================
//
// Description:
// Set Single/Dual Antenna default setting for products that do not do detection in advance.
//
// Added by Joseph, 2012.03.22
//
VOID
ODM_SingleDualAntennaDefaultSetting(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
PADAPTER pAdapter = pDM_Odm->Adapter;
u1Byte btAntNum=BT_GetPgAntNum(pAdapter);
// Set default antenna A and B status
if(btAntNum == 2)
{
pDM_SWAT_Table->ANTA_ON=TRUE;
pDM_SWAT_Table->ANTB_ON=TRUE;
}
else if(btAntNum == 1)
{// Set antenna A as default
pDM_SWAT_Table->ANTA_ON=TRUE;
pDM_SWAT_Table->ANTB_ON=FALSE;
}
else
{
RT_ASSERT(FALSE, ("Incorrect antenna number!!\n"));
}
}
//2 8723A ANT DETECT
//
// Description:
// Implement IQK single tone for RF DPK loopback and BB PSD scanning.
// This function is cooperated with BB team Neil.
//
// Added by Roger, 2011.12.15
//
BOOLEAN
ODM_SingleDualAntennaDetection(
IN PVOID pDM_VOID,
IN u1Byte mode
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte CurrentChannel,RfLoopReg;
u1Byte n;
u4Byte Reg88c, Regc08, Reg874, Regc50, Reg948, Regb2c, Reg92c, Reg930, Reg064, AFE_rRx_Wait_CCA;
u1Byte initial_gain = 0x5a;
u4Byte PSD_report_tmp;
u4Byte AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
BOOLEAN bResult = TRUE;
u4Byte AFE_Backup[16];
u4Byte AFE_REG_8723A[16] = {
rRx_Wait_CCA, rTx_CCK_RFON,
rTx_CCK_BBON, rTx_OFDM_RFON,
rTx_OFDM_BBON, rTx_To_Rx,
rTx_To_Tx, rRx_CCK,
rRx_OFDM, rRx_Wait_RIFS,
rRx_TO_Rx, rStandby,
rSleep, rPMPD_ANAEN,
rFPGA0_XCD_SwitchControl, rBlue_Tooth};
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============>\n"));
if (!(pDM_Odm->SupportICType & ODM_RTL8723B))
return bResult;
// Retrieve antenna detection registry info, added by Roger, 2012.11.27.
if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter))
return bResult;
//1 Backup Current RF/BB Settings
CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
Reg92c = ODM_GetBBReg(pDM_Odm, rDPDT_control, bMaskDWord);
Reg930 = ODM_GetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord);
Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord);
Reg064 = ODM_GetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29);
ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1);
ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77);
ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, 0x1); //dbg 7
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3c0, 0x0);//dbg 8
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x0);
}
ODM_StallExecution(10);
//Store A Path Register 88c, c08, 874, c50
Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
// Store AFE Registers
if (pDM_Odm->SupportICType & ODM_RTL8723B)
AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord);
//Set PSD 128 pts
ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts
// To SET CH1 to do
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401); //Channel 1
// AFE all on step
if (pDM_Odm->SupportICType & ODM_RTL8723B)
ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016);
// 3 wire Disable
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
//BB IQK Setting
ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
//IQK setting tone@ 4.34Mhz
ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
//Page B init
ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150016);
ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150016);
}
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7f, initial_gain);
//IQK Single tone start
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000);
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
ODM_StallExecution(10000);
// PSD report of antenna A
PSD_report_tmp=0x0;
for (n=0;n<2;n++)
{
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
if(PSD_report_tmp >AntA_report)
AntA_report=PSD_report_tmp;
}
// change to Antenna B
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
//ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2);
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280);
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1);
}
ODM_StallExecution(10);
// PSD report of antenna B
PSD_report_tmp=0x0;
for (n=0;n<2;n++)
{
PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
if(PSD_report_tmp > AntB_report)
AntB_report=PSD_report_tmp;
}
//Close IQK Single Tone function
ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000);
//1 Return to antanna A
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
// external DPDT
ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c);
//internal S0/S1
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c);
ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord, Reg930);
ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, Reg064);
}
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg);
//Reload AFE Registers
if (pDM_Odm->SupportICType & ODM_RTL8723B)
ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA);
if (pDM_Odm->SupportICType & ODM_RTL8723B) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report));
//2 Test Ant B based on Ant A is ON
if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 135) && (AntB_report <= 135))
{
u1Byte TH1=2, TH2=6;
if((AntA_report - AntB_report < TH1) || (AntB_report - AntA_report < TH1))
{
pDM_SWAT_Table->ANTA_ON=TRUE;
pDM_SWAT_Table->ANTB_ON=TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
}
else if(((AntA_report - AntB_report >= TH1) && (AntA_report - AntB_report <= TH2)) ||
((AntB_report - AntA_report >= TH1) && (AntB_report - AntA_report <= TH2)))
{
pDM_SWAT_Table->ANTA_ON=FALSE;
pDM_SWAT_Table->ANTB_ON=FALSE;
bResult = FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
}
else
{
pDM_SWAT_Table->ANTA_ON = TRUE;
pDM_SWAT_Table->ANTB_ON=FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna\n"));
}
pDM_Odm->AntDetectedInfo.bAntDetected= TRUE;
pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report;
pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report;
pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report;
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n"));
bResult = FALSE;
}
}
return bResult;
}
//1 [2. Scan AP RSSI Method] ==================================================
BOOLEAN
ODM_SwAntDivCheckBeforeLink(
IN PVOID pDM_VOID
)
{
#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
s1Byte Score = 0;
PRT_WLAN_BSS pTmpBssDesc, pTestBssDesc;
u1Byte power_target = 10, power_target_L = 9, power_target_H = 16;
u1Byte tmp_power_diff = 0,power_diff = 0,avg_power_diff = 0,max_power_diff = 0,min_power_diff = 0xff;
u2Byte index, counter = 0;
static u1Byte ScanChannel;
u8Byte tStamp_diff = 0;
u4Byte tmp_SWAS_NoLink_BK_Reg948;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d )) \n",pDM_Odm->DM_SWAT_Table.ANTA_ON ,pDM_Odm->DM_SWAT_Table.ANTB_ON ));
//if(HP id)
{
if(pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult==TRUE && pDM_Odm->SupportICType == ODM_RTL8723B)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n"));
return FALSE;
}
if(pDM_Odm->SupportICType == ODM_RTL8723B)
{
if(pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 == 0xff)
pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch );
}
}
if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413
{ // The ODM structure is not initialized.
return FALSE;
}
// Retrieve antenna detection registry info, added by Roger, 2012.11.27.
if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter))
{
return FALSE;
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI Method\n"));
}
// Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
{
PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState));
pDM_SWAT_Table->SWAS_NoLink_State = 0;
return FALSE;
}
else
{
PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State));
//1 Run AntDiv mechanism "Before Link" part.
if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
{
//1 Prepare to do Scan again to check current antenna state.
// Set check state to next step.
pDM_SWAT_Table->SWAS_NoLink_State = 1;
// Copy Current Scan list.
pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc;
PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
// Go back to scan function again.
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n"));
pMgntInfo->ScanStep=0;
pMgntInfo->bScanAntDetect = TRUE;
ScanChannel = odm_SwAntDivSelectScanChnl(Adapter);
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
{
if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
else
ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
if(ScanChannel == 0)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
{
pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
else
{
pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
return FALSE;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")));
} else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) {
/*Switch Antenna to another one.*/
tmp_SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch);
if ((pDM_SWAT_Table->CurAntenna == MAIN_ANT) && (tmp_SWAS_NoLink_BK_Reg948 == 0x200)) {
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280);
ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1);
pDM_SWAT_Table->CurAntenna = AUX_ANT;
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_SWAS_NoLink_BK_Reg948));
return FALSE;
}
ODM_StallExecution(10);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to (( %s-ant)) for testing.\n", (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?"MAIN":"AUX"));
}
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
return TRUE;
}
else //pDM_SWAT_Table->SWAS_NoLink_State == 1
{
//1 ScanComple() is called after antenna swiched.
//1 Check scan result and determine which antenna is going
//1 to be used.
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" tmpNumBssDesc= (( %d )) \n",pMgntInfo->tmpNumBssDesc));// debug for Dino
for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++)
{
pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1
pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2
if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n"));
continue;
}
if(pDM_Odm->SupportICType != ODM_RTL8723B)
{
if(pTmpBssDesc->ChannelNumber == ScanChannel)
{
if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n"));
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
Score++;
PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
}
else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n"));
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
Score--;
}
else
{
if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000)
{
RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n"));
}
}
}
}
else // 8723B
{
if(pTmpBssDesc->ChannelNumber == ScanChannel)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ChannelNumber == ScanChannel -> (( %d )) \n", pTmpBssDesc->ChannelNumber ));
if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) // Pow(Ant1) > Pow(Ant2)
{
counter++;
tmp_power_diff=(u1Byte)(pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower);
power_diff = power_diff + tmp_power_diff;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d)) \n", tmp_power_diff,max_power_diff,min_power_diff));
if(tmp_power_diff > max_power_diff)
max_power_diff=tmp_power_diff;
if(tmp_power_diff < min_power_diff)
min_power_diff=tmp_power_diff;
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d)) \n",max_power_diff,min_power_diff));
PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
}
else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower) // Pow(Ant1) < Pow(Ant2)
{
counter++;
tmp_power_diff=(u1Byte)(pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower);
power_diff = power_diff + tmp_power_diff;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
if(tmp_power_diff > max_power_diff)
max_power_diff=tmp_power_diff;
if(tmp_power_diff < min_power_diff)
min_power_diff=tmp_power_diff;
}
else // Pow(Ant1) = Pow(Ant2)
{
if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp) // Stamp(Ant1) < Stamp(Ant2)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000)
{
counter++;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
min_power_diff = 0;
}
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
}
}
}
}
}
if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
{
if(pMgntInfo->NumBssDesc!=0 && Score<0)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
else
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
else
ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
}
if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
{
pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
else
{
pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
}
}
else if(pDM_Odm->SupportICType == ODM_RTL8723B)
{
if(counter == 0)
{
if(pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec == FALSE)
{
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = TRUE;
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again \n"));
//3 [ Scan again ]
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
return TRUE;
}
else// Pre_Aux_FailDetec == TRUE
{
//2 [ Single Antenna ]
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE;
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Still cannot find any AP ]] \n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
}
pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter++;
}
else
{
pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE;
if(counter==3)
{
avg_power_diff = ((power_diff-max_power_diff - min_power_diff)>>1)+ ((max_power_diff + min_power_diff)>>2);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff));
}
else if(counter>=4)
{
avg_power_diff=(power_diff-max_power_diff - min_power_diff) / (counter - 2);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff));
}
else//counter==1,2
{
avg_power_diff=power_diff/counter;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d )) \n", avg_power_diff,counter, power_diff));
}
//2 [ Retry ]
if( (avg_power_diff >=power_target_L) && (avg_power_diff <=power_target_H) )
{
pDM_Odm->DM_SWAT_Table.Retry_Counter++;
if(pDM_Odm->DM_SWAT_Table.Retry_Counter<=3)
{
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]] \n", avg_power_diff));
//3 [ Scan again ]
odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
return TRUE;
}
else
{
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( Retry_Counter > 3 )) \n"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
}
}
//2 [ Dual Antenna ]
else if( (pMgntInfo->NumBssDesc != 0) && (avg_power_diff < power_target_L) )
{
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
{
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter++;
// set bt coexDM from 1ant coexDM to 2ant coexDM
BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 2);
//3 [ Init antenna diversity ]
pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
ODM_AntDivInit(pDM_Odm);
}
//2 [ Single Antenna ]
else if(avg_power_diff > power_target_H)
{
pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE;
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
{
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
//BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1);
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
pDM_Odm->DM_SWAT_Table.Single_Ant_Counter++;
}
}
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bResult=(( %d ))\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Dual_Ant_Counter = (( %d )), Single_Ant_Counter = (( %d )) , Retry_Counter = (( %d )) , Aux_FailDetec_Counter = (( %d ))\n\n\n",
pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter,pDM_Odm->DM_SWAT_Table.Single_Ant_Counter,pDM_Odm->DM_SWAT_Table.Retry_Counter,pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter));
//2 recover the antenna setting
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, (pDM_SWAT_Table->SWAS_NoLink_BK_Reg948));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bResult=(( %d )), Recover Reg[948]= (( %x )) \n\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult, pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 ));
}
// Check state reset to default and wait for next time.
pDM_SWAT_Table->SWAS_NoLink_State = 0;
pMgntInfo->bScanAntDetect = FALSE;
return FALSE;
}
#else
return FALSE;
#endif
return FALSE;
}
//1 [3. PSD Method] ==========================================================
u4Byte
odm_GetPSDData(
IN PVOID pDM_VOID,
IN u2Byte point,
IN u1Byte initial_gain)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u4Byte psd_report;
ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); //Start PSD calculation, Reg808[22]=0->1
ODM_StallExecution(150);//Wait for HW PSD report
ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);//Stop PSD calculation, Reg808[22]=1->0
psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;//Read PSD report, Reg8B4[15:0]
psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report));//+(u4Byte)(initial_gain);
return psd_report;
}
VOID
ODM_SingleDualAntennaDetection_PSD(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER pAdapter = pDM_Odm->Adapter;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte Channel_ori;
u1Byte initial_gain = 0x36;
u1Byte tone_idx;
u1Byte Tone_lenth_1=7, Tone_lenth_2=4;
u2Byte Tone_idx_1[7]={88, 104, 120, 8, 24, 40, 56};
u2Byte Tone_idx_2[4]={8, 24, 40, 56};
u4Byte PSD_report_Main[11]={0}, PSD_report_Aux[11]={0};
//u1Byte Tone_lenth_1=4, Tone_lenth_2=2;
//u2Byte Tone_idx_1[4]={88, 120, 24, 56};
//u2Byte Tone_idx_2[2]={ 24, 56};
//u4Byte PSD_report_Main[6]={0}, PSD_report_Aux[6]={0};
u4Byte PSD_report_temp,MAX_PSD_report_Main=0,MAX_PSD_report_Aux=0;
u4Byte PSD_power_threshold;
u4Byte Main_psd_result=0, Aux_psd_result=0;
u4Byte Regc50, Reg948, Regb2c,Regc14,Reg908;
u4Byte i=0,test_num=8;
if(pDM_Odm->SupportICType != ODM_RTL8723B)
return;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection_PSD()============> \n"));
//2 [ Backup Current RF/BB Settings ]
Channel_ori = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord);
Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
Regc14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord);
Reg908 = ODM_GetBBReg(pDM_Odm, 0x908, bMaskDWord);
//2 [ Setting for doing PSD function (CH4)]
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); //disable whole CCK block
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // Turn off TX -> Pause TX Queue
ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); // [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA]
// PHYTXON while loop
ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x803);
while (ODM_GetBBReg(pDM_Odm, 0xdf4, BIT6))
{
i++;
if (i > 1000000)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i));
break;
}
}
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH4 & 40M
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf
ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pt //Set PSD 128 ptss
ODM_StallExecution(3000);
//2 [ Doing PSD Function in (CH4)]
//Antenna A
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n"));
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200);
ODM_StallExecution(10);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n"));
for (i=0;i<test_num;i++)
{
for (tone_idx=0;tone_idx<Tone_lenth_1;tone_idx++)
{
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_1[tone_idx], initial_gain);
//if( PSD_report_temp>PSD_report_Main[tone_idx] )
PSD_report_Main[tone_idx]+=PSD_report_temp;
}
}
//Antenna B
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n"));
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280);
ODM_StallExecution(10);
for (i=0;i<test_num;i++)
{
for (tone_idx=0;tone_idx<Tone_lenth_1;tone_idx++)
{
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_1[tone_idx], initial_gain);
//if( PSD_report_temp>PSD_report_Aux[tone_idx] )
PSD_report_Aux[tone_idx]+=PSD_report_temp;
}
}
//2 [ Doing PSD Function in (CH8)]
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0
ODM_StallExecution(3000);
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain);
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH8 & 40M
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf
ODM_StallExecution(3000);
//Antenna A
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n"));
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200);
ODM_StallExecution(10);
for (i=0;i<test_num;i++)
{
for (tone_idx=0;tone_idx<Tone_lenth_2;tone_idx++)
{
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_2[tone_idx], initial_gain);
//if( PSD_report_temp>PSD_report_Main[tone_idx] )
PSD_report_Main[Tone_lenth_1+tone_idx]+=PSD_report_temp;
}
}
//Antenna B
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n"));
ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280);
ODM_StallExecution(10);
for (i=0;i<test_num;i++)
{
for (tone_idx=0;tone_idx<Tone_lenth_2;tone_idx++)
{
PSD_report_temp = odm_GetPSDData(pDM_Odm, Tone_idx_2[tone_idx], initial_gain);
//if( PSD_report_temp>PSD_report_Aux[tone_idx] )
PSD_report_Aux[Tone_lenth_1+tone_idx]+=PSD_report_temp;
}
}
//2 [ Calculate Result ]
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL) \n"));
for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Main[tone_idx] ));
Main_psd_result+= PSD_report_Main[tone_idx];
if(PSD_report_Main[tone_idx]>MAX_PSD_report_Main)
MAX_PSD_report_Main=PSD_report_Main[tone_idx];
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", Main_psd_result));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", MAX_PSD_report_Main));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL) \n"));
for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Aux[tone_idx] ));
Aux_psd_result+= PSD_report_Aux[tone_idx];
if(PSD_report_Aux[tone_idx]>MAX_PSD_report_Aux)
MAX_PSD_report_Aux=PSD_report_Aux[tone_idx];
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", Aux_psd_result));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", MAX_PSD_report_Aux));
//Main_psd_result=Main_psd_result-MAX_PSD_report_Main;
//Aux_psd_result=Aux_psd_result-MAX_PSD_report_Aux;
PSD_power_threshold=(Main_psd_result*7)>>3;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result , Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", Main_psd_result, Aux_psd_result,PSD_power_threshold));
//3 [ Dual Antenna ]
if(Aux_psd_result >= PSD_power_threshold )
{
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
{
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
// set bt coexDM from 1ant coexDM to 2ant coexDM
//BT_SetBtCoexAntNum(pAdapter, BT_COEX_ANT_TYPE_DETECTED, 2);
// Init antenna diversity
pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
ODM_AntDivInit(pDM_Odm);
}
//3 [ Single Antenna ]
else
{
if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
{
pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
}
//2 [ Recover all parameters ]
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,Channel_ori);
ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0
ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, Regc50);
ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c);
ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); //enable whole CCK block
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x0); //Turn on TX // Resume TX Queue
ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, Regc14); // [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA]
ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, Reg908);
return;
}
#endif
void
odm_SwAntDetectInit(
IN PVOID pDM_VOID
)
{
#if(defined(CONFIG_ANT_DETECTION))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
//pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c = ODM_Read4Byte(pDM_Odm, rDPDT_control);
//pDM_SWAT_Table->PreAntenna = MAIN_ANT;
//pDM_SWAT_Table->CurAntenna = MAIN_ANT;
pDM_SWAT_Table->SWAS_NoLink_State = 0;
pDM_SWAT_Table->Pre_Aux_FailDetec = FALSE;
pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = 0xff;
#endif
}
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_AntDect.h
Executable
+98
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@@ -0,0 +1,98 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/
#if(defined(CONFIG_ANT_DETECTION))
//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
//ANT Test
#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/
#define ANTTESTA 0x01 /*Ant A will be Testing*/
#define ANTTESTB 0x02 /*Ant B will be testing*/
#define MAX_ANTENNA_DETECTION_CNT 10
typedef struct _ANT_DETECTED_INFO{
BOOLEAN bAntDetected;
u4Byte dBForAntA;
u4Byte dBForAntB;
u4Byte dBForAntO;
}ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
typedef enum tag_SW_Antenna_Switch_Definition
{
Antenna_A = 1,
Antenna_B = 2,
Antenna_MAX = 3,
}DM_SWAS_E;
//1 [1. Single Tone Method] ===================================================
VOID
ODM_SingleDualAntennaDefaultSetting(
IN PVOID pDM_VOID
);
BOOLEAN
ODM_SingleDualAntennaDetection(
IN PVOID pDM_VOID,
IN u1Byte mode
);
//1 [2. Scan AP RSSI Method] ==================================================
#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink
BOOLEAN
ODM_SwAntDivCheckBeforeLink(
IN PVOID pDM_VOID
);
//1 [3. PSD Method] ==========================================================
VOID
ODM_SingleDualAntennaDetection_PSD(
IN PVOID pDM_VOID
);
#endif
VOID
odm_SwAntDetectInit(
IN PVOID pDM_VOID
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_AntDiv.c
Executable
+4783
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File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_AntDiv.h
Executable
+608
View File
@@ -0,0 +1,608 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
/*#define ANTDIV_VERSION "2.0" //2014.11.04*/
/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/
/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/
/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/
/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/
#define ANTDIV_VERSION "3.3" /*2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT,
because antenna diversity only works when BT is disable or radio off*/
//1 ============================================================
//1 Definition
//1 ============================================================
#define ANTDIV_INIT 0xff
#define MAIN_ANT 1 //Ant A or Ant Main
#define AUX_ANT 2 //AntB or Ant Aux
#define MAX_ANT 3 // 3 for AP using
#define ANT1_2G 0 // = ANT2_5G
#define ANT2_2G 1 // = ANT1_5G
/*smart antenna*/
#define SUPPORT_RF_PATH_NUM 4
#define SUPPORT_BEAM_PATTERN_NUM 4
//Antenna Diversty Control Type
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E)
#define ODM_ANTDIV_2G BIT0
#define ODM_ANTDIV_5G BIT1
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define FAT_ON 1
#define FAT_OFF 0
#define TX_BY_DESC 1
#define REG 0
#define RSSI_METHOD 0
#define EVM_METHOD 1
#define CRC32_METHOD 2
#define INIT_ANTDIV_TIMMER 0
#define CANCEL_ANTDIV_TIMMER 1
#define RELEASE_ANTDIV_TIMMER 2
#define CRC32_FAIL 1
#define CRC32_OK 0
#define Evm_RSSI_TH_High 25
#define Evm_RSSI_TH_Low 20
#define NORMAL_STATE_MIAN 1
#define NORMAL_STATE_AUX 2
#define TRAINING_STATE 3
#define FORCE_RSSI_DIFF 10
#define CSI_ON 1
#define CSI_OFF 0
#define DIVON_CSIOFF 1
#define DIVOFF_CSION 2
#define BDC_DIV_TRAIN_STATE 0
#define BDC_BFer_TRAIN_STATE 1
#define BDC_DECISION_STATE 2
#define BDC_BF_HOLD_STATE 3
#define BDC_DIV_HOLD_STATE 4
#define BDC_MODE_1 1
#define BDC_MODE_2 2
#define BDC_MODE_3 3
#define BDC_MODE_4 4
#define BDC_MODE_NULL 0xff
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
#define HL_SMTANT_2WIRE_DATA_LEN 24
//1 ============================================================
//1 structure
//1 ============================================================
typedef struct _SW_Antenna_Switch_
{
u1Byte Double_chk_flag;
u1Byte try_flag;
s4Byte PreRSSI;
u1Byte CurAntenna;
u1Byte PreAntenna;
u1Byte RSSI_Trying;
u1Byte TestMode;
u1Byte bTriggerAntennaSwitch;
u1Byte SelectAntennaMap;
u1Byte RSSI_target;
u1Byte reset_idx;
u2Byte Single_Ant_Counter;
u2Byte Dual_Ant_Counter;
u2Byte Aux_FailDetec_Counter;
u2Byte Retry_Counter;
// Before link Antenna Switch check
u1Byte SWAS_NoLink_State;
u4Byte SWAS_NoLink_BK_Reg860;
u4Byte SWAS_NoLink_BK_Reg92c;
u4Byte SWAS_NoLink_BK_Reg948;
BOOLEAN ANTA_ON; //To indicate Ant A is or not
BOOLEAN ANTB_ON; //To indicate Ant B is on or not
BOOLEAN Pre_Aux_FailDetec;
BOOLEAN RSSI_AntDect_bResult;
u1Byte Ant5G;
u1Byte Ant2G;
s4Byte RSSI_sum_A;
s4Byte RSSI_sum_B;
s4Byte RSSI_cnt_A;
s4Byte RSSI_cnt_B;
u8Byte lastTxOkCnt;
u8Byte lastRxOkCnt;
u8Byte TXByteCnt_A;
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte TrafficLoad;
u1Byte Train_time;
u1Byte Train_time_flag;
RT_TIMER SwAntennaSwitchTimer;
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
RT_TIMER SwAntennaSwitchTimer_8723B;
u4Byte PktCnt_SWAntDivByCtrlFrame;
BOOLEAN bSWAntDivByCtrlFrame;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if USE_WORKITEM
RT_WORK_ITEM SwAntennaSwitchWorkitem;
#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)
RT_WORK_ITEM SwAntennaSwitchWorkitem_8723B;
#endif
#endif
#endif
/* CE Platform use
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
_timer SwAntennaSwitchTimer;
u8Byte lastTxOkCnt;
u8Byte lastRxOkCnt;
u8Byte TXByteCnt_A;
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
u1Byte DoubleComfirm;
u1Byte TrafficLoad;
//SW Antenna Switch
#endif
*/
#ifdef CONFIG_HW_ANTENNA_DIVERSITY
//Hybrid Antenna Diversity
u4Byte CCK_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte CCK_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte OFDM_Ant1_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte OFDM_Ant2_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant1_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant2_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte TxAnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte TargetSTA;
u1Byte antsel;
u1Byte RxIdleAnt;
#endif
}SWAT_T, *pSWAT_T;
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
typedef struct _BF_DIV_COEX_
{
BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM];
BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte BDCcoexType_wBfer;
u1Byte num_Txbfee_Client;
u1Byte num_Txbfer_Client;
u1Byte BDC_Try_counter;
u1Byte BDC_Hold_counter;
u1Byte BDC_Mode;
u1Byte BDC_active_Mode;
u1Byte BDC_state;
u1Byte BDC_RxIdleUpdate_counter;
u1Byte num_Client;
u1Byte pre_num_Client;
u1Byte num_BfTar;
u1Byte num_DivTar;
BOOLEAN bAll_DivSta_Idle;
BOOLEAN bAll_BFSta_Idle;
BOOLEAN BDC_Try_flag;
BOOLEAN BF_pass;
BOOLEAN DIV_pass;
}BDC_T,*pBDC_T;
#endif
#endif
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
typedef struct _SMART_ANTENNA_TRAINNING_ {
u4Byte latch_time;
BOOLEAN pkt_skip_statistic_en;
u4Byte fix_beam_pattern_en;
u4Byte fix_training_num_en;
u4Byte fix_beam_pattern_codeword;
u4Byte update_beam_codeword;
u4Byte ant_num; /*number of smart beam antenna*/
u4Byte beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/
u4Byte data_codeword_bit_num;
u4Byte per_beam_training_pkt_num;
u4Byte pkt_counter;
u4Byte fast_training_beam_num;
u4Byte pre_fast_training_beam_num;
u4Byte pkt_rssi_sum[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
u4Byte pkt_rssi_cnt[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM];
u4Byte rx_idle_beam[SUPPORT_RF_PATH_NUM];
u4Byte pre_codeword;
BOOLEAN force_update_beam_en;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
RT_WORK_ITEM hl_smart_antenna_workitem;
RT_WORK_ITEM hl_smart_antenna_decision_workitem;
#endif
} SAT_T, *pSAT_T;
#endif
typedef struct _FAST_ANTENNA_TRAINNING_
{
u1Byte Bssid[6];
u1Byte antsel_rx_keep_0;
u1Byte antsel_rx_keep_1;
u1Byte antsel_rx_keep_2;
u1Byte antsel_rx_keep_3;
u4Byte antSumRSSI[7];
u4Byte antRSSIcnt[7];
u4Byte antAveRSSI[7];
u1Byte FAT_State;
u4Byte TrainIdx;
u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte RxIdleAnt;
u1Byte AntDiv_OnOff;
BOOLEAN bBecomeLinked;
u4Byte MinMaxRSSI;
u1Byte idx_AntDiv_counter_2G;
u1Byte idx_AntDiv_counter_5G;
u1Byte AntDiv_2G_5G;
u4Byte CCK_counter_main;
u4Byte CCK_counter_aux;
u4Byte OFDM_counter_main;
u4Byte OFDM_counter_aux;
#ifdef ODM_EVM_ENHANCE_ANTDIV
u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
BOOLEAN EVM_method_enable;
u1Byte TargetAnt_EVM;
u1Byte TargetAnt_CRC32;
u1Byte TargetAnt_enhance;
u1Byte pre_TargetAnt_enhance;
u2Byte Main_MPDU_OK_cnt;
u2Byte Aux_MPDU_OK_cnt;
u4Byte CRC32_Ok_Cnt;
u4Byte CRC32_Fail_Cnt;
u4Byte MainCRC32_Ok_Cnt;
u4Byte AuxCRC32_Ok_Cnt;
u4Byte MainCRC32_Fail_Cnt;
u4Byte AuxCRC32_Fail_Cnt;
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
u4Byte CCK_CtrlFrame_Cnt_main;
u4Byte CCK_CtrlFrame_Cnt_aux;
u4Byte OFDM_CtrlFrame_Cnt_main;
u4Byte OFDM_CtrlFrame_Cnt_aux;
u4Byte MainAnt_CtrlFrame_Sum;
u4Byte AuxAnt_CtrlFrame_Sum;
u4Byte MainAnt_CtrlFrame_Cnt;
u4Byte AuxAnt_CtrlFrame_Cnt;
#endif
BOOLEAN fix_ant_bfee;
BOOLEAN enable_ctrl_frame_antdiv;
BOOLEAN use_ctrl_frame_antdiv;
u1Byte hw_antsw_occur;
}FAT_T,*pFAT_T;
//1 ============================================================
//1 enumeration
//1 ============================================================
typedef enum _FAT_STATE /*Fast antenna training*/
{
FAT_BEFORE_LINK_STATE = 0,
FAT_PREPARE_STATE = 1,
FAT_TRAINING_STATE = 2,
FAT_DECISION_STATE = 3
}FAT_STATE_E, *PFAT_STATE_E;
typedef enum _ANT_DIV_TYPE
{
NO_ANTDIV = 0xFF,
CG_TRX_HW_ANTDIV = 0x01,
CGCS_RX_HW_ANTDIV = 0x02,
FIXED_HW_ANTDIV = 0x03,
CG_TRX_SMART_ANTDIV = 0x04,
CGCS_RX_SW_ANTDIV = 0x05,
S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/
HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 Ant. entitys, and each Ant. is equipped with 4 antenna patterns*/
}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
//1 ============================================================
//1 function prototype
//1 ============================================================
VOID
ODM_StopAntennaSwitchDm(
IN PVOID pDM_VOID
);
VOID
ODM_SetAntConfig(
IN PVOID pDM_VOID,
IN u1Byte antSetting // 0=A, 1=B, 2=C, ....
);
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
VOID ODM_SwAntDivRestAfterLink(
IN PVOID pDM_VOID
);
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_UpdateRxIdleAnt(
IN PVOID pDM_VOID,
IN u1Byte Ant
);
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_SW_AntDiv_Callback(
IN PRT_TIMER pTimer
);
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
VOID
ODM_SW_AntDiv_Callback(
void *FunctionContext
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_S0S1_SwAntDivByCtrlFrame(
IN PVOID pDM_VOID,
IN u1Byte Step
);
VOID
odm_AntselStatisticsOfCtrlFrame(
IN PVOID pDM_VOID,
IN u1Byte antsel_tr_mux,
IN u4Byte RxPWDBAll
);
VOID
odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(
IN PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
#endif
#endif
#ifdef ODM_EVM_ENHANCE_ANTDIV
VOID
odm_EVM_FastAntTrainingCallback(
IN PVOID pDM_VOID
);
#endif
VOID
odm_HW_AntDiv(
IN PVOID pDM_VOID
);
#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
VOID
odm_FastAntTraining(
IN PVOID pDM_VOID
);
VOID
odm_FastAntTrainingCallback(
IN PVOID pDM_VOID
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PVOID pDM_VOID
);
#endif
#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
phydm_beam_switch_workitem_callback(
IN PVOID pContext
);
VOID
phydm_beam_decision_workitem_callback(
IN PVOID pContext
);
#endif
VOID
phydm_update_beam_pattern(
IN PVOID pDM_VOID,
IN u4Byte codeword,
IN u4Byte codeword_length
);
void
phydm_set_all_ant_same_beam_num(
IN PVOID pDM_VOID
);
VOID
phydm_hl_smart_ant_cmd(
IN PVOID pDM_VOID,
IN u4Byte *const dm_value,
IN u4Byte *_used,
OUT char *output,
IN u4Byte *_out_len
);
#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/
VOID
ODM_AntDivInit(
IN PVOID pDM_VOID
);
VOID
ODM_AntDiv(
IN PVOID pDM_VOID
);
VOID
odm_AntselStatistics(
IN PVOID pDM_VOID,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u4Byte utility,
IN u1Byte method
);
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
ODM_SetTxAntByTxInfo(
IN PVOID pDM_VOID,
IN pu1Byte pDesc,
IN u1Byte macId
);
#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo(
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
unsigned short aid
);
#endif
VOID
ODM_AntDiv_Config(
IN PVOID pDM_VOID
);
VOID
ODM_UpdateRxIdleAnt_8723B(
IN PVOID pDM_VOID,
IN u1Byte Ant,
IN u4Byte DefaultAnt,
IN u4Byte OptionalAnt
);
VOID
ODM_AntDivTimers(
IN PVOID pDM_VOID,
IN u1Byte state
);
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_AntDivReset(
IN PVOID pDM_VOID
);
VOID
odm_AntennaDiversityInit(
IN PVOID pDM_VOID
);
VOID
odm_AntennaDiversity(
IN PVOID pDM_VOID
);
#endif //#ifndef __ODMANTDIV_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_CfoTracking.c
Executable
+337
View File
@@ -0,0 +1,337 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_SetCrystalCap(
IN PVOID pDM_VOID,
IN u1Byte CrystalCap
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
if(pCfoTrack->CrystalCap == CrystalCap)
return;
pCfoTrack->CrystalCap = CrystalCap;
if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) {
/* write 0x24[22:17] = 0x24[16:11] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6)));
} else if (pDM_Odm->SupportICType & ODM_RTL8812) {
/* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6)));
} else if ((pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) {
/* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6)));
} else if (pDM_Odm->SupportICType & ODM_RTL8821B) {
/* write 0x28[6:1] = 0x24[30:25] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7E000000, CrystalCap);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7E, CrystalCap);
} else if (pDM_Odm->SupportICType & ODM_RTL8814A) {
/* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6)));
} else if (pDM_Odm->SupportICType & ODM_RTL8822B) {
/* write 0x24[30:25] = 0x28[6:1] = CrystalCap */
CrystalCap = CrystalCap & 0x3F;
ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap);
ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap);
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n"));
ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6)));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap));
#endif
}
u1Byte
odm_GetDefaultCrytaltalCap(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte CrystalCap = 0x20;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
CrystalCap = pHalData->CrystalCap;
#else
prtl8192cd_priv priv = pDM_Odm->priv;
if(priv->pmib->dot11RFEntry.xcap > 0)
CrystalCap = priv->pmib->dot11RFEntry.xcap;
#endif
CrystalCap = CrystalCap & 0x3f;
return CrystalCap;
}
VOID
odm_SetATCStatus(
IN PVOID pDM_VOID,
IN BOOLEAN ATCStatus
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
if(pCfoTrack->bATCStatus == ATCStatus)
return;
ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus);
pCfoTrack->bATCStatus = ATCStatus;
}
BOOLEAN
odm_GetATCStatus(
IN PVOID pDM_VOID
)
{
BOOLEAN ATCStatus;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm));
return ATCStatus;
}
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap)
{
odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap - 1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap));
} else if (pCfoTrack->CrystalCap < pCfoTrack->DefXCap)
{
odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap + 1);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD,
("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap));
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
odm_SetATCStatus(pDM_Odm, TRUE);
#endif
}
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm);
pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm);
pCfoTrack->bAdjust = TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========> \n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x \n",pCfoTrack->bATCStatus, pCfoTrack->DefXCap));
}
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
int CFO_kHz_A, CFO_kHz_B, CFO_ave = 0;
int CFO_ave_diff;
int CrystalCap = (int)pCfoTrack->CrystalCap;
u1Byte Adjust_Xtal = 1;
//4 Support ability
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n"));
return;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n"));
if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly)
{
//4 No link or more than one entry
ODM_CfoTrackingReset(pDM_Odm);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n",
pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly));
}
else
{
//3 1. CFO Tracking
//4 1.1 No new packet
if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n"));
return;
}
pCfoTrack->packetCount_pre = pCfoTrack->packetCount;
//4 1.2 Calculate CFO
CFO_kHz_A = (int)((pCfoTrack->CFO_tail[0] * 3125) / 10)>>7; /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */
CFO_kHz_B = (int)((pCfoTrack->CFO_tail[1] * 3125) / 10)>>7;
if(pDM_Odm->RFType < ODM_2T2R)
CFO_ave = CFO_kHz_A;
else
CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n",
CFO_kHz_A, CFO_kHz_B, CFO_ave));
//4 1.3 Avoid abnormal large CFO
CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre);
if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n"));
pCfoTrack->largeCFOHit = 1;
return;
}
else
pCfoTrack->largeCFOHit = 0;
pCfoTrack->CFO_ave_pre = CFO_ave;
//4 1.4 Dynamic Xtal threshold
if(pCfoTrack->bAdjust == FALSE)
{
if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH))
pCfoTrack->bAdjust = TRUE;
}
else
{
if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW))
pCfoTrack->bAdjust = FALSE;
}
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
//4 1.5 BT case: Disable CFO tracking
if(pDM_Odm->bBtEnabled)
{
pCfoTrack->bAdjust = FALSE;
odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n"));
}
/*
//4 1.6 Big jump
if(pCfoTrack->bAdjust)
{
if(CFO_ave > CFO_TH_XTAL_LOW)
Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2);
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal));
}
*/
#endif
//4 1.7 Adjust Crystal Cap.
if(pCfoTrack->bAdjust)
{
if(CFO_ave > CFO_TH_XTAL_LOW)
CrystalCap = CrystalCap + Adjust_Xtal;
else if(CFO_ave < (-CFO_TH_XTAL_LOW))
CrystalCap = CrystalCap - Adjust_Xtal;
if(CrystalCap > 0x3f)
CrystalCap = 0x3f;
else if (CrystalCap < 0)
CrystalCap = 0;
odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n",
pCfoTrack->CrystalCap, pCfoTrack->DefXCap));
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
return;
//3 2. Dynamic ATC switch
if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC)
{
odm_SetATCStatus(pDM_Odm, FALSE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n"));
}
else
{
odm_SetATCStatus(pDM_Odm, TRUE);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n"));
}
#endif
}
}
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID;
PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK);
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING))
return;
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if(pPktinfo->bPacketMatchBSSID)
#else
if(pPktinfo->StationID != 0)
#endif
{
//3 Update CFO report for path-A & path-B
// Only paht-A and path-B have CFO tail and short CFO
for(i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++)
{
pCfoTrack->CFO_tail[i] = (int)pcfotail[i];
}
//3 Update packet counter
if(pCfoTrack->packetCount == 0xffffffff)
pCfoTrack->packetCount = 0;
else
pCfoTrack->packetCount++;
}
}
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_CfoTracking.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#define CFO_TRACKING_VERSION "1.3" /*2015.07.29 by YuChen*/
#define CFO_TH_XTAL_HIGH 20 // kHz
#define CFO_TH_XTAL_LOW 10 // kHz
#define CFO_TH_ATC 80 // kHz
typedef struct _CFO_TRACKING_
{
BOOLEAN bATCStatus;
BOOLEAN largeCFOHit;
BOOLEAN bAdjust;
u1Byte CrystalCap;
u1Byte DefXCap;
int CFO_tail[2];
int CFO_ave_pre;
u4Byte packetCount;
u4Byte packetCount_pre;
BOOLEAN bForceXtalCap;
BOOLEAN bReset;
}CFO_TRACKING, *PCFO_TRACKING;
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
);
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DIG.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DIG.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDIG_H__
#define __PHYDMDIG_H__
#define DIG_VERSION "1.10" /*2015.08.11 Stanley, modify IGI upper bound when coverage mode*/
/* Pause DIG & CCKPD */
#define DM_DIG_MAX_PAUSE_TYPE 0x7
typedef struct _Dynamic_Initial_Gain_Threshold_
{
BOOLEAN bStopDIG; // for debug
BOOLEAN bIgnoreDIG;
BOOLEAN bPSDInProgress;
u1Byte Dig_Enable_Flag;
u1Byte Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
u4Byte FALowThresh;
u4Byte FAHighThresh;
u1Byte CurSTAConnectState;
u1Byte PreSTAConnectState;
u1Byte CurMultiSTAConnectState;
u1Byte PreIGValue;
u1Byte CurIGValue;
u1Byte BackupIGValue; //MP DIG
u1Byte BT30_CurIGI;
u1Byte IGIBackup;
s1Byte BackoffVal;
s1Byte BackoffVal_range_max;
s1Byte BackoffVal_range_min;
u1Byte rx_gain_range_max;
u1Byte rx_gain_range_min;
u1Byte Rssi_val_min;
u1Byte PreCCK_CCAThres;
u1Byte CurCCK_CCAThres;
u1Byte PreCCKPDState;
u1Byte CurCCKPDState;
u1Byte CCKPDBackup;
u1Byte pause_cckpd_level;
u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
u1Byte LargeFAHit;
u1Byte ForbiddenIGI;
u4Byte Recover_cnt;
u1Byte DIG_Dynamic_MIN_0;
u1Byte DIG_Dynamic_MIN_1;
BOOLEAN bMediaConnect_0;
BOOLEAN bMediaConnect_1;
u4Byte AntDiv_RSSI_max;
u4Byte RSSI_max;
u1Byte *bP2PInProcess;
u1Byte pause_dig_level;
u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
BOOLEAN bTpTarget;
BOOLEAN bNoiseEst;
u4Byte TpTrainTH_min;
u1Byte IGIOffset_A;
u1Byte IGIOffset_B;
#endif
}DIG_T,*pDIG_T;
typedef struct _FALSE_ALARM_STATISTICS{
u4Byte Cnt_Parity_Fail;
u4Byte Cnt_Rate_Illegal;
u4Byte Cnt_Crc8_fail;
u4Byte Cnt_Mcs_fail;
u4Byte Cnt_Ofdm_fail;
u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A
u4Byte Cnt_Cck_fail;
u4Byte Cnt_all;
u4Byte Cnt_Fast_Fsync;
u4Byte Cnt_SB_Search_fail;
u4Byte Cnt_OFDM_CCA;
u4Byte Cnt_CCK_CCA;
u4Byte Cnt_CCA_all;
u4Byte Cnt_BW_USC; //Gary
u4Byte Cnt_BW_LSC; //Gary
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
/*
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
{
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_PD_STAGE_MAX = 3,
}DM_CCK_PDTH_E;
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
{
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
}DM_DIG_EXT_PORT_ALG_E;
typedef enum tag_DIG_Connect_Definition
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
DIG_STA_BEFORE_CONNECT = 2,
DIG_MultiSTA_DISCONNECT = 3,
DIG_MultiSTA_CONNECT = 4,
DIG_CONNECT_MAX
}DM_DIG_CONNECT_E;
#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
*/
typedef enum tag_PHYDM_Pause_Type {
PHYDM_PAUSE = BIT0,
PHYDM_RESUME = BIT1
} PHYDM_PAUSE_TYPE;
typedef enum tag_PHYDM_Pause_Level {
/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
PHYDM_PAUSE_LEVEL_0 = 0,
PHYDM_PAUSE_LEVEL_1 = 1,
PHYDM_PAUSE_LEVEL_2 = 2,
PHYDM_PAUSE_LEVEL_3 = 3,
PHYDM_PAUSE_LEVEL_4 = 4,
PHYDM_PAUSE_LEVEL_5 = 5,
PHYDM_PAUSE_LEVEL_6 = 6,
PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
} PHYDM_PAUSE_LEVEL;
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX_NIC 0x3e
/*define 8814 2G lower bound*/
#define DM_DIG_MIN_8194A 0x28
#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c
#define DM_DIG_MAX_OF_MIN_NIC 0x3e
#ifdef CONFIG_PCI_HCI
#define DM_DIG_MAX_AP 0x3e
#else
#define DM_DIG_MAX_AP 0x50
#endif
#define DM_DIG_MIN_AP 0x1c
#define DM_DIG_MAX_OF_MIN 0x2A //0x32
#define DM_DIG_MIN_AP_DFS 0x20
#define DM_DIG_MAX_NIC_HP 0x46
#define DM_DIG_MIN_NIC_HP 0x2e
#define DM_DIG_MAX_AP_HP 0x42
#define DM_DIG_MIN_AP_HP 0x30
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#define DM_DIG_MAX_AP_COVERAGR 0x26
#define DM_DIG_MIN_AP_COVERAGE 0x1c
#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22
#define DM_DIG_TP_Target_TH0 500
#define DM_DIG_TP_Target_TH1 1000
#define DM_DIG_TP_Training_Period 10
#endif
//vivi 92c&92d has different definition, 20110504
//this is for 92c
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
#define DM_DIG_FA_TH0 0x80//0x20
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#define DM_DIG_FA_TH1 0x300
#define DM_DIG_FA_TH2 0x400
//this is for 92d
#define DM_DIG_FA_TH0_92D 0x100
#define DM_DIG_FA_TH1_92D 0x400
#define DM_DIG_FA_TH2_92D 0x600
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps
#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps
#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps
#define RSSI_OFFSET_DIG 0x05
VOID
ODM_ChangeDynamicInitGainThresh(
IN PVOID pDM_VOID,
IN u4Byte DM_Type,
IN u4Byte DM_Value
);
VOID
ODM_Write_DIG(
IN PVOID pDM_VOID,
IN u1Byte CurrentIGI
);
VOID
odm_PauseDIG(
IN PVOID pDM_VOID,
IN PHYDM_PAUSE_TYPE PauseType,
IN PHYDM_PAUSE_LEVEL pause_level,
IN u1Byte IGIValue
);
VOID
odm_DIGInit(
IN PVOID pDM_VOID
);
VOID
odm_DIG(
IN PVOID pDM_VOID
);
VOID
odm_DIGbyRSSI_LPS(
IN PVOID pDM_VOID
);
VOID
odm_FalseAlarmCounterStatistics(
IN PVOID pDM_VOID
);
VOID
odm_PauseCCKPacketDetection(
IN PVOID pDM_VOID,
IN PHYDM_PAUSE_TYPE PauseType,
IN PHYDM_PAUSE_LEVEL pause_level,
IN u1Byte CCKPDThreshold
);
VOID
odm_CCKPacketDetectionThresh(
IN PVOID pDM_VOID
);
VOID
ODM_Write_CCK_CCA_Thres(
IN PVOID pDM_VOID,
IN u1Byte CurCCK_CCAThres
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_MPT_DIGCallback(
PRT_TIMER pTimer
);
VOID
odm_MPT_DIGWorkItemCallback(
IN PVOID pContext
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
VOID
odm_MPT_DIGCallback(
IN PVOID pDM_VOID
);
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_CE)
VOID
ODM_MPT_DIG(
IN PVOID pDM_VOID
);
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DynamicBBPowerSaving.c
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_DynamicBBPowerSavingInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
pDM_PSTable->PreCCAState = CCA_MAX;
pDM_PSTable->CurCCAState = CCA_MAX;
pDM_PSTable->PreRFState = RF_MAX;
pDM_PSTable->CurRFState = RF_MAX;
pDM_PSTable->Rssi_val_min = 0;
pDM_PSTable->initialize = 0;
}
void
ODM_RF_Saving(
IN PVOID pDM_VOID,
IN u1Byte bForceInNormal
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
u1Byte Rssi_Up_bound = 30 ;
u1Byte Rssi_Low_bound = 25;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
{
Rssi_Up_bound = 50 ;
Rssi_Low_bound = 45;
}
#endif
if(pDM_PSTable->initialize == 0){
pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
//Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
pDM_PSTable->initialize = 1;
}
if(!bForceInNormal)
{
if(pDM_Odm->RSSI_Min != 0xFF)
{
if(pDM_PSTable->PreRFState == RF_Normal)
{
if(pDM_Odm->RSSI_Min >= Rssi_Up_bound)
pDM_PSTable->CurRFState = RF_Save;
else
pDM_PSTable->CurRFState = RF_Normal;
}
else{
if(pDM_Odm->RSSI_Min <= Rssi_Low_bound)
pDM_PSTable->CurRFState = RF_Normal;
else
pDM_PSTable->CurRFState = RF_Save;
}
}
else
pDM_PSTable->CurRFState=RF_MAX;
}
else
{
pDM_PSTable->CurRFState = RF_Normal;
}
if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
{
if(pDM_PSTable->CurRFState == RF_Save)
{
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
}
else
{
ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874);
ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
}
pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
}
#endif
}
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DynamicBBPowerSaving.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__
#define __PHYDMDYNAMICBBPOWERSAVING_H__
#define DYNAMIC_BBPWRSAV_VERSION "1.1"
typedef struct _Dynamic_Power_Saving_
{
u1Byte PreCCAState;
u1Byte CurCCAState;
u1Byte PreRFState;
u1Byte CurRFState;
int Rssi_val_min;
u1Byte initialize;
u4Byte Reg874,RegC70,Reg85C,RegA74;
}PS_T,*pPS_T;
#define dm_RF_Saving ODM_RF_Saving
void ODM_RF_Saving(
IN PVOID pDM_VOID,
IN u1Byte bForceInNormal
);
VOID
odm_DynamicBBPowerSavingInit(
IN PVOID pDM_VOID
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DynamicTxPower.c
Executable
+316
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
odm_DynamicTxPowerInit(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
#if DEV_BUS_TYPE==RT_USB_INTERFACE
if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power)
{
odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
pMgntInfo->bDynamicTxPowerEnable = TRUE;
}
else
#else
//so 92c pci do not need dynamic tx power? vivi check it later
pMgntInfo->bDynamicTxPowerEnable = FALSE;
#endif
pHalData->LastDTPLvl = TxHighPwrLevel_Normal;
pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
#endif
}
VOID
odm_DynamicTxPowerSavePowerIndex(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
for(index = 0; index< 6; index++)
pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
#endif
#endif
}
VOID
odm_DynamicTxPowerRestorePowerIndex(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
u1Byte index;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
for(index = 0; index< 6; index++)
PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]);
#endif
#endif
}
VOID
odm_DynamicTxPowerWritePowerIndex(
IN PVOID pDM_VOID,
IN u1Byte Value)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
for(index = 0; index< 6; index++)
//PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
}
VOID
odm_DynamicTxPower(
IN PVOID pDM_VOID
)
{
//
// For AP/ADSL use prtl8192cd_priv
// For CE/NIC use PADAPTER
//
//PADAPTER pAdapter = pDM_Odm->Adapter;
// prtl8192cd_priv priv = pDM_Odm->priv;
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
return;
//
// 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
// at the same time. In the stage2/3, we need to prive universal interface and merge all
// HW dynamic mechanism.
//
switch (pDM_Odm->SupportPlatform)
{
case ODM_WIN:
case ODM_CE:
odm_DynamicTxPowerNIC(pDM_Odm);
break;
case ODM_AP:
odm_DynamicTxPowerAP(pDM_Odm);
break;
default:
break;
}
}
VOID
odm_DynamicTxPowerNIC(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
return;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
if (pDM_Odm->SupportICType == ODM_RTL8821) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter);
if (pMgntInfo->RegRspPwr == 1)
{
if(pDM_Odm->RSSI_Min > 60)
{
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); // Resp TXAGC offset = -3dB
}
else if(pDM_Odm->RSSI_Min < 55)
{
ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); // Resp TXAGC offset = 0dB
}
}
#endif
}
#endif
}
VOID
odm_DynamicTxPowerAP(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1))
prtl8192cd_priv priv = pDM_Odm->priv;
s4Byte i;
s2Byte pwr_thd = TX_POWER_NEAR_FIELD_THRESH_AP;
if(!priv->pshare->rf_ft_var.tx_pwr_ctrl)
return;
#if ((RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1))
if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A))
pwr_thd = TX_POWER_NEAR_FIELD_THRESH_8812;
#endif
/*
* Check if station is near by to use lower tx power
*/
if ((priv->up_time % 3) == 0 ) {
int disable_pwr_ctrl = ((pDM_Odm->FalseAlmCnt.Cnt_all > 1000 ) || ((pDM_Odm->FalseAlmCnt.Cnt_all > 300 ) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0;
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat) ) {
#ifdef TX_SHORTCUT
unsigned char hp_level = pstat->hp_level;
#endif
if (disable_pwr_ctrl)
pstat->hp_level = 0;
else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd))
pstat->hp_level = 1;
else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8)))
pstat->hp_level = 0;
#ifdef TX_SHORTCUT
if (hp_level != pstat->hp_level) {
clearTxShortCutBufSize(priv, pstat);
}
#endif
}
}
#if defined(CONFIG_WLAN_HAL_8192EE)
if (GET_CHIP_VER(priv) == VERSION_8192E) {
if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) {
if(pDM_Odm->RSSI_Min > pwr_thd)
RRSR_power_control_11n(priv, 1 );
else if(pDM_Odm->RSSI_Min < (pwr_thd-8))
RRSR_power_control_11n(priv, 0 );
} else {
RRSR_power_control_11n(priv, 0 );
}
}
#endif
#ifdef CONFIG_WLAN_HAL_8814AE
if (GET_CHIP_VER(priv) == VERSION_8814A) {
if (!disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff)) {
if (pDM_Odm->RSSI_Min > pwr_thd)
RRSR_power_control_14(priv, 1);
else if (pDM_Odm->RSSI_Min < (pwr_thd-8))
RRSR_power_control_14(priv, 0);
} else {
RRSR_power_control_14(priv, 0);
}
}
#endif
}
//#endif
#endif
}
VOID
odm_DynamicTxPower_8821(
IN PVOID pDM_VOID,
IN pu1Byte pDesc,
IN u1Byte macId
)
{
#if (RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PSTA_INFO_T pEntry;
u1Byte reg0xc56_byte;
u1Byte reg0xe56_byte;
u1Byte txpwr_offset = 0;
pEntry = pDM_Odm->pODM_StaInfo[macId];
reg0xc56_byte = ODM_Read1Byte(pDM_Odm, 0xc56);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte));
if (pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB > 85) {
/* Avoid TXAGC error after TX power offset is applied.
For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB )
Total power = 6-11= -5( overflow!! ), PA may be burned !
so txpwr_offset should be adjusted by Reg0xc56*/
if (reg0xc56_byte < 7)
txpwr_offset = 1;
else if (reg0xc56_byte < 11)
txpwr_offset = 2;
else
txpwr_offset = 3;
SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset));
} else{
SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset));
}
#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
#endif /*#if (RTL8821A_SUPPORT==1)*/
}
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_DynamicTxPower.h
Executable
+88
View File
@@ -0,0 +1,88 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDYNAMICTXPOWER_H__
#define __PHYDMDYNAMICTXPOWER_H__
/*#define DYNAMIC_TXPWR_VERSION "1.0"*/
#define DYNAMIC_TXPWR_VERSION "1.2" /*2015.07.29*/
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
#define TX_POWER_NEAR_FIELD_THRESH_8812 60
#define TxHighPwrLevel_Normal 0
#define TxHighPwrLevel_Level1 1
#define TxHighPwrLevel_Level2 2
#define TxHighPwrLevel_BT1 3
#define TxHighPwrLevel_BT2 4
#define TxHighPwrLevel_15 5
#define TxHighPwrLevel_35 6
#define TxHighPwrLevel_50 7
#define TxHighPwrLevel_70 8
#define TxHighPwrLevel_100 9
VOID
odm_DynamicTxPowerInit(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerRestorePowerIndex(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerNIC(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_DynamicTxPowerSavePowerIndex(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerWritePowerIndex(
IN PVOID pDM_VOID,
IN u1Byte Value);
VOID
odm_DynamicTxPower_8821(
IN PVOID pDM_VOID,
IN pu1Byte pDesc,
IN u1Byte macId
);
#endif
VOID
odm_DynamicTxPower(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerAP(
IN PVOID pDM_VOID
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_EdcaTurboCheck.c
Executable
+768
View File
@@ -0,0 +1,768 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
VOID
ODM_EdcaTurboInit(
IN PVOID pDM_VOID)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
PADAPTER Adapter = NULL;
HAL_DATA_TYPE *pHalData = NULL;
if(pDM_Odm->Adapter==NULL) {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n"));
return;
}
Adapter=pDM_Odm->Adapter;
pHalData=GET_HAL_DATA(Adapter);
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
pHalData->bIsAnyNonBEPkts = FALSE;
#elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
Adapter->recvpriv.bIsAnyNonBEPkts =FALSE;
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM)));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM)));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM)));
} // ODM_InitEdcaTurbo
VOID
odm_EdcaTurboCheck(
IN PVOID pDM_VOID
)
{
//
// For AP/ADSL use prtl8192cd_priv
// For CE/NIC use PADAPTER
//
//
// 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
// at the same time. In the stage2/3, we need to prive universal interface and merge all
// HW dynamic mechanism.
//
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n"));
if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))
return;
switch (pDM_Odm->SupportPlatform)
{
case ODM_WIN:
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
odm_EdcaTurboCheckMP(pDM_Odm);
#endif
break;
case ODM_CE:
#if(DM_ODM_SUPPORT_TYPE==ODM_CE)
odm_EdcaTurboCheckCE(pDM_Odm);
#endif
break;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n"));
} // odm_CheckEdcaTurbo
#if(DM_ODM_SUPPORT_TYPE==ODM_CE)
VOID
odm_EdcaTurboCheckCE(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
u32 EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer];
u32 EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer];
u32 ICType=pDM_Odm->SupportICType;
u32 IOTPeer=0;
u8 WirelessMode=0xFF; //invalid value
u32 trafficIndex;
u32 edca_param;
u64 cur_tx_bytes = 0;
u64 cur_rx_bytes = 0;
u8 bbtchange = _FALSE;
u8 bBiasOnRx = _FALSE;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter);
struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv);
struct recv_priv *precvpriv = &(Adapter->recvpriv);
struct registry_priv *pregpriv = &Adapter->registrypriv;
struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
if(pDM_Odm->bLinked != _TRUE)
{
precvpriv->bIsAnyNonBEPkts = _FALSE;
return;
}
if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0))
{
precvpriv->bIsAnyNonBEPkts = _FALSE;
return;
}
if(pDM_Odm->pWirelessMode!=NULL)
WirelessMode=*(pDM_Odm->pWirelessMode);
IOTPeer = pmlmeinfo->assoc_AP_vendor;
if (IOTPeer >= HT_IOT_PEER_MAX)
{
precvpriv->bIsAnyNonBEPkts = _FALSE;
return;
}
if (pDM_Odm->SupportICType & ODM_RTL8188E) {
if((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS))
bBiasOnRx = _TRUE;
}
// Check if the status needs to be changed.
if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) )
{
cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
//traffic, TX or RX
if(bBiasOnRx)
{
if (cur_tx_bytes > (cur_rx_bytes << 2))
{ // Uplink TP is present.
trafficIndex = UP_LINK;
}
else
{ // Balance TP is present.
trafficIndex = DOWN_LINK;
}
}
else
{
if (cur_rx_bytes > (cur_tx_bytes << 2))
{ // Downlink TP is present.
trafficIndex = DOWN_LINK;
}
else
{ // Balance TP is present.
trafficIndex = UP_LINK;
}
}
//if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
{
if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) {
EDCA_BE_UL = 0x6ea42b;
EDCA_BE_DL = 0x6ea42b;
}
//92D txop can't be set to 0x3e for cisco1250
if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G))
{
EDCA_BE_DL = edca_setting_DL[IOTPeer];
EDCA_BE_UL = edca_setting_UL[IOTPeer];
}
//merge from 92s_92c_merge temp brunch v2445 20120215
else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
{
EDCA_BE_DL = edca_setting_DL_GMode[IOTPeer];
}
else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
{
EDCA_BE_DL = 0xa630;
}
else if(IOTPeer == HT_IOT_PEER_MARVELL)
{
EDCA_BE_DL = edca_setting_DL[IOTPeer];
EDCA_BE_UL = edca_setting_UL[IOTPeer];
}
else if(IOTPeer == HT_IOT_PEER_ATHEROS)
{
// Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
EDCA_BE_DL = edca_setting_DL[IOTPeer];
}
if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8821)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE
{
EDCA_BE_UL = 0x5ea42b;
EDCA_BE_DL = 0x5ea42b;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x",EDCA_BE_UL,EDCA_BE_DL));
}
if (trafficIndex == DOWN_LINK)
edca_param = EDCA_BE_DL;
else
edca_param = EDCA_BE_UL;
rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
}
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE;
}
else
{
//
// Turn Off EDCA turbo here.
// Restore original EDCA according to the declaration of AP.
//
if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
{
rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE;
}
}
}
#elif(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_EdcaTurboCheckMP(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter);
PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos;
//[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn
u8Byte Ext_curTxOkCnt = 0;
u8Byte Ext_curRxOkCnt = 0;
//For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
// Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
u8Byte curTxOkCnt = 0;
u8Byte curRxOkCnt = 0;
u4Byte EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer];
u4Byte EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer];
u4Byte EDCA_BE = 0x5ea42b;
u1Byte IOTPeer=0;
BOOLEAN *pbIsCurRDLState=NULL;
BOOLEAN bLastIsCurRDLState=FALSE;
BOOLEAN bBiasOnRx=FALSE;
BOOLEAN bEdcaTurboOn=FALSE;
u1Byte TxRate = 0xFF;
u8Byte value64;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>"));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
////===============================
////list paramter for different platform
////===============================
bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState;
pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState);
//2012/09/14 MH Add
if (pMgntInfo->NumNonBePkt > pMgntInfo->RegEdcaThresh && !Adapter->MgntInfo.bWiFiConfg)
pHalData->bIsAnyNonBEPkts = TRUE;
pMgntInfo->NumNonBePkt = 0;
// Caculate TX/RX TP:
//curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt;
//curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt;
curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_Odm->lastTxOkCnt;
curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pDM_Odm->lastRxOkCnt;
pDM_Odm->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
pDM_Odm->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
if(pExtAdapter == NULL)
pExtAdapter = pDefaultAdapter;
Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt;
Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt;
GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
//For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
{
curTxOkCnt = Ext_curTxOkCnt ;
curRxOkCnt = Ext_curRxOkCnt ;
}
//
IOTPeer=pMgntInfo->IOTPeer;
bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE;
bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts))?TRUE:FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx \n",pHalData->bIsAnyNonBEPkts));
////===============================
////check if edca turbo is disabled
////===============================
if(odm_IsEdcaTurboDisable(pDM_Odm))
{
pHalData->bIsAnyNonBEPkts = FALSE;
pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast;
pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast;
}
////===============================
////remove iot case out
////===============================
ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL);
////===============================
////Check if the status needs to be changed.
////===============================
if(bEdcaTurboOn)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt));
if(bBiasOnRx)
odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, TRUE, pbIsCurRDLState);
else
odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, FALSE, pbIsCurRDLState);
//modify by Guo.Mingzhi 2011-12-29
EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL;
if(IS_HARDWARE_TYPE_8821U(Adapter))
{
if(pMgntInfo->RegTxDutyEnable)
{
//2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle)
if(!pMgntInfo->ForcedDataRate) //auto rate
{
if(pDM_Odm->TxRate != 0xFF)
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
}
else //force rate
{
TxRate = (u1Byte) pMgntInfo->ForcedDataRate;
}
value64 = (curRxOkCnt<<2);
if(curTxOkCnt < value64) //Downlink
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
else //Uplink
{
/*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/
/*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/
if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G))
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
else
{
switch (TxRate)
{
case MGN_VHT1SS_MCS6:
case MGN_VHT1SS_MCS5:
case MGN_MCS6:
case MGN_MCS5:
case MGN_48M:
case MGN_54M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea42b);
break;
case MGN_VHT1SS_MCS4:
case MGN_MCS4:
case MGN_36M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa42b);
break;
case MGN_VHT1SS_MCS3:
case MGN_MCS3:
case MGN_24M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa47f);
break;
case MGN_VHT1SS_MCS2:
case MGN_MCS2:
case MGN_18M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa57f);
break;
case MGN_VHT1SS_MCS1:
case MGN_MCS1:
case MGN_9M:
case MGN_12M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa77f);
break;
case MGN_VHT1SS_MCS0:
case MGN_MCS0:
case MGN_6M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f);
break;
default:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
break;
}
}
}
}
else
{
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
}
}
else if (IS_HARDWARE_TYPE_8812AU(Adapter)){
if(pMgntInfo->RegTxDutyEnable)
{
//2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle)
// it;s the same issue as 8811AU
if(!pMgntInfo->ForcedDataRate) //auto rate
{
if(pDM_Odm->TxRate != 0xFF)
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
}
else //force rate
{
TxRate = (u1Byte) pMgntInfo->ForcedDataRate;
}
value64 = (curRxOkCnt<<2);
if(curTxOkCnt < value64) //Downlink
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
else //Uplink
{
/*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/
/*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/
if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G))
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
else
{
switch (TxRate)
{
case MGN_VHT2SS_MCS9:
case MGN_VHT1SS_MCS9:
case MGN_VHT1SS_MCS8:
case MGN_MCS15:
case MGN_MCS7:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea44f);
case MGN_VHT2SS_MCS8:
case MGN_VHT1SS_MCS7:
case MGN_MCS14:
case MGN_MCS6:
case MGN_54M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa44f);
case MGN_VHT2SS_MCS7:
case MGN_VHT2SS_MCS6:
case MGN_VHT1SS_MCS6:
case MGN_VHT1SS_MCS5:
case MGN_MCS13:
case MGN_MCS5:
case MGN_48M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa630);
break;
case MGN_VHT2SS_MCS5:
case MGN_VHT2SS_MCS4:
case MGN_VHT1SS_MCS4:
case MGN_VHT1SS_MCS3:
case MGN_MCS12:
case MGN_MCS4:
case MGN_MCS3:
case MGN_36M:
case MGN_24M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa730);
break;
case MGN_VHT2SS_MCS3:
case MGN_VHT2SS_MCS2:
case MGN_VHT2SS_MCS1:
case MGN_VHT1SS_MCS2:
case MGN_VHT1SS_MCS1:
case MGN_MCS11:
case MGN_MCS10:
case MGN_MCS9:
case MGN_MCS2:
case MGN_MCS1:
case MGN_18M:
case MGN_12M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa830);
break;
case MGN_VHT2SS_MCS0:
case MGN_VHT1SS_MCS0:
case MGN_MCS0:
case MGN_MCS8:
case MGN_9M:
case MGN_6M:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f);
break;
default:
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
break;
}
}
}
}
else
{
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
}
}
else
ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE));
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE));
}
else
{
// Turn Off EDCA turbo here.
// Restore original EDCA according to the declaration of AP.
if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
{
Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) );
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE));
}
}
}
//check if edca turbo is disabled
BOOLEAN
odm_IsEdcaTurboDisable(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
u4Byte IOTPeer=pMgntInfo->IOTPeer;
if(pDM_Odm->bBtDisableEdcaTurbo)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
return TRUE;
}
if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))||
(pDM_Odm->bWIFITest)||
(IOTPeer>= HT_IOT_PEER_MAX))
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
return TRUE;
}
// 1. We do not turn on EDCA turbo mode for some AP that has IOT issue
// 2. User may disable EDCA Turbo mode with OID settings.
if(pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n"));
return TRUE;
}
return FALSE;
}
//add iot case here: for MP/CE
VOID
ODM_EdcaParaSelByIot(
IN PVOID pDM_VOID,
OUT u4Byte *EDCA_BE_UL,
OUT u4Byte *EDCA_BE_DL
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u4Byte IOTPeer=0;
u4Byte ICType=pDM_Odm->SupportICType;
u1Byte WirelessMode=0xFF; //invalid value
u4Byte RFType=pDM_Odm->RFType;
u4Byte IOTPeerSubType = 0;
PMGNT_INFO pMgntInfo = &Adapter->MgntInfo;
u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
if(pDM_Odm->pWirelessMode!=NULL)
WirelessMode=*(pDM_Odm->pWirelessMode);
///////////////////////////////////////////////////////////
////list paramter for different platform
IOTPeer=pMgntInfo->IOTPeer;
IOTPeerSubType=pMgntInfo->IOTPeerSubtype;
GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
////============================
/// IOT case for MP
////============================
if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) {
(*EDCA_BE_UL) = 0x6ea42b;
(*EDCA_BE_DL) = 0x6ea42b;
}
if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
{
(*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer];
(*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer];
}
#if (INTEL_PROXIMITY_SUPPORT == 1)
if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE)
{
(*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
}
else
#endif
{
if((pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE)))
{// To check whether we shall force turn on TXOP configuration.
if(!((*EDCA_BE_UL) & 0xffff0000))
(*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL.
if(!((*EDCA_BE_DL) & 0xffff0000))
(*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL.
}
//92D txop can't be set to 0x3e for cisco1250
if ((IOTPeer == HT_IOT_PEER_CISCO) && (WirelessMode == ODM_WM_N24G))
{
(*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
(*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
}
//merge from 92s_92c_merge temp brunch v2445 20120215
else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
{
(*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer];
}
else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
{
(*EDCA_BE_DL) = 0xa630;
}
else if(IOTPeer == HT_IOT_PEER_MARVELL)
{
(*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
(*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
}
else if(IOTPeer == HT_IOT_PEER_ATHEROS && IOTPeerSubType != HT_IOT_PEER_TPLINK_AC1750)
{
// Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
if(WirelessMode==ODM_WM_G)
(*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer];
else
(*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
if(ICType == ODM_RTL8821)
(*EDCA_BE_DL) = 0x5ea630;
}
}
if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE
{
(*EDCA_BE_UL) = 0x5ea42b;
(*EDCA_BE_DL) = 0x5ea42b;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL)));
}
if((ICType==ODM_RTL8814A) && (IOTPeer == HT_IOT_PEER_REALTEK)) /*8814AU and 8814AR*/
{
(*EDCA_BE_UL) = 0x5ea42b;
(*EDCA_BE_DL) = 0xa42b;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL)));
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, IOTPeer = %d\n",(*EDCA_BE_UL),(*EDCA_BE_DL), IOTPeer));
}
VOID
odm_EdcaChooseTrafficIdx(
IN PVOID pDM_VOID,
IN u8Byte cur_tx_bytes,
IN u8Byte cur_rx_bytes,
IN BOOLEAN bBiasOnRx,
OUT BOOLEAN *pbIsCurRDLState
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(bBiasOnRx)
{
if(cur_tx_bytes>(cur_rx_bytes*4))
{
*pbIsCurRDLState=FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n "));
}
else
{
*pbIsCurRDLState=TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
}
}
else
{
if(cur_rx_bytes>(cur_tx_bytes*4))
{
*pbIsCurRDLState=TRUE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink Traffic\n"));
}
else
{
*pbIsCurRDLState=FALSE;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
}
}
return ;
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_EdcaTurboCheck.h
Executable
+100
View File
@@ -0,0 +1,100 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMEDCATURBOCHECK_H__
#define __PHYDMEDCATURBOCHECK_H__
/*#define EDCATURBO_VERSION "2.1"*/
#define EDCATURBO_VERSION "2.3" /*2015.07.29 by YuChen*/
typedef struct _EDCA_TURBO_
{
BOOLEAN bCurrentTurboEDCA;
BOOLEAN bIsCurRDLState;
#if(DM_ODM_SUPPORT_TYPE == ODM_CE )
u4Byte prv_traffic_idx; // edca turbo
#endif
}EDCA_T,*pEDCA_T;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx)
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx)
{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
#endif
VOID
odm_EdcaTurboCheck(
IN PVOID pDM_VOID
);
VOID
ODM_EdcaTurboInit(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_EdcaTurboCheckMP(
IN PVOID pDM_VOID
);
//check if edca turbo is disabled
BOOLEAN
odm_IsEdcaTurboDisable(
IN PVOID pDM_VOID
);
//choose edca paramter for special IOT case
VOID
ODM_EdcaParaSelByIot(
IN PVOID pDM_VOID,
OUT u4Byte *EDCA_BE_UL,
OUT u4Byte *EDCA_BE_DL
);
//check if it is UL or DL
VOID
odm_EdcaChooseTrafficIdx(
IN PVOID pDM_VOID,
IN u8Byte cur_tx_bytes,
IN u8Byte cur_rx_bytes,
IN BOOLEAN bBiasOnRx,
OUT BOOLEAN *pbIsCurRDLState
);
#elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
VOID
odm_EdcaTurboCheckCE(
IN PVOID pDM_VOID
);
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_HWConfig.c
Executable
+3199
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_HWConfig.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/*--------------------------Define -------------------------------------------*/
#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG(ic, band) do {\
if (pDM_Odm->bIsMPChip)\
AGC_DIFF_CONFIG_MP(ic,band);\
else\
AGC_DIFF_CONFIG_TC(ic,band);\
} while(0)
//============================================================
// structure and define
//============================================================
__PACK typedef struct _Phy_Rx_AGC_Info
{
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain:7,trsw:1;
#else
u1Byte trsw:1,gain:7;
#endif
} __WLAN_ATTRIB_PACK__ PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T;
__PACK typedef struct _Phy_Status_Rpt_8192cd {
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;/*ch_corr_msb;*/
u1Byte noise_power_db_msb;
s1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/
u1Byte sgi_en: 1;
u1Byte rxsc: 2;
u1Byte idle_long: 1;
u1Byte r_ant_train_en: 1;
u1Byte ant_sel_b: 1;
u1Byte ant_sel: 1;
#else /*_BIG_ENDIAN_ */
u1Byte ant_sel: 1;
u1Byte ant_sel_b: 1;
u1Byte r_ant_train_en: 1;
u1Byte idle_long: 1;
u1Byte rxsc: 2;
u1Byte sgi_en: 1;
u1Byte antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/
#endif
} __WLAN_ATTRIB_PACK__ PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T;
typedef struct _Phy_Status_Rpt_8812 {
/* DWORD 0*/
u1Byte gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/
u1Byte chl_num_LSB; /*channel number[7:0]*/
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte chl_num_MSB: 2; /*channel number[9:8]*/
u1Byte sub_chnl: 4; /*sub-channel location[3:0]*/
u1Byte r_RFMOD: 2; /*RF mode[1:0]*/
#else /*_BIG_ENDIAN_ */
u1Byte r_RFMOD: 2;
u1Byte sub_chnl: 4;
u1Byte chl_num_MSB: 2;
#endif
/* DWORD 1*/
u1Byte pwdb_all; /*CCK signal quality / OFDM pwdb all*/
s1Byte cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM Path-A and Path-B short CFO*/
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
/*this should be checked again because the definition of 8812 and 8814 is different*/
/* u1Byte r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/
/* u1Byte cck_rx_path:4; cck rx path[3:0]*/
u1Byte resvd_0: 6;
u1Byte bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/
#else /*_BIG_ENDIAN_*/
u1Byte bt_RF_ch_MSB: 2;
u1Byte resvd_0: 6;
#endif
/* DWORD 2*/
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/
u1Byte ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/
u1Byte bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/
#else /*_BIG_ENDIAN_ */
u1Byte bt_RF_ch_LSB: 6;
u1Byte ant_div_sw_b: 1;
u1Byte ant_div_sw_a: 1;
#endif
s1Byte cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/
u1Byte PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/
u1Byte PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/
/* DWORD 3*/
s1Byte rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/
s1Byte rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/
/* DWORD 4*/
u1Byte PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/
u1Byte pcts_rpt_valid: 1; /*pcts_rpt_valid*/
u1Byte resvd_1: 1; /*1'b0*/
#else /*_BIG_ENDIAN_*/
u1Byte resvd_1: 1;
u1Byte pcts_rpt_valid: 1;
u1Byte PCTS_MSK_RPT_3: 6;
#endif
s1Byte rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/
/* DWORD 5*/
u1Byte csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/
u1Byte gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/
/* DWORD 6*/
s1Byte sigevm; /*signal field EVM*/
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/
u1Byte antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/
u1Byte dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/
u1Byte GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/
#else /*_BIG_ENDIAN_*/
u1Byte GNT_BT_keep: 1;
u1Byte dpdt_ctrl_keep: 1;
u1Byte antidx_antd: 3;
u1Byte antidx_antc: 3;
#endif
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_anta: 3; /*antidx_anta[2:0]*/
u1Byte antidx_antb: 3; /*antidx_antb[2:0]*/
u1Byte hw_antsw_occur: 2; /*1'b0*/
#else /*_BIG_ENDIAN_*/
u1Byte hw_antsw_occur: 2;
u1Byte antidx_antb: 3;
u1Byte antidx_anta: 3;
#endif
} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T;
VOID
odm_Init_RSSIForDM(
IN OUT PDM_ODM_T pDM_Odm
);
VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
);
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
IN BOOLEAN bPacketBeacon
);
HAL_STATUS
ODM_ConfigRFWithTxPwrTrackHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_Config_Type ConfigType,
IN ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigFWWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_FW_Config_Type ConfigType,
OUT u1Byte *pFirmware,
OUT u4Byte *pSize
);
u4Byte
ODM_GetHWImgVersion(
IN PDM_ODM_T pDM_Odm
);
s4Byte
odm_SignalScaleMapping(
IN OUT PDM_ODM_T pDM_Odm,
IN s4Byte CurrSig
);
#if (RTL8822B_SUPPORT == 1)
/*For 8822B only!! need to move to FW finally */
/*==============================================*/
VOID
phydm_RxPhyStatusJaguarSeries2(
IN PDM_ODM_T pPhydm,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo,
OUT PODM_PHY_INFO_T pPhyInfo
);
typedef struct _Phy_Status_Rpt_Jaguar2_Type0 {
/* DW0 */
u1Byte page_num;
u1Byte pwdb;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain: 6;
u1Byte rsvd_0: 1;
u1Byte trsw: 1;
#else
u1Byte trsw: 1;
u1Byte rsvd_0: 1;
u1Byte gain: 6;
#endif
u1Byte rsvd_1;
/* DW1 */
u1Byte rsvd_2;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte rxsc: 4;
u1Byte agc_table: 4;
#else
u1Byte agc_table: 4;
u1Byte rxsc: 4;
#endif
u1Byte channel;
u1Byte band;
/* DW2 */
u2Byte length;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_a: 3;
u1Byte antidx_b: 3;
u1Byte rsvd_3: 2;
u1Byte antidx_c: 3;
u1Byte antidx_d: 3;
u1Byte rsvd_4:2;
#else
u1Byte rsvd_3: 2;
u1Byte antidx_b: 3;
u1Byte antidx_a: 3;
u1Byte rsvd_4:2;
u1Byte antidx_d: 3;
u1Byte antidx_c: 3;
#endif
/* DW3 */
u1Byte signal_quality;
u1Byte agc_rpt;
u1Byte bb_power;
u1Byte rsvd_5;
/* DW4 */
u4Byte rsvd_6;
/* DW5 */
u4Byte rsvd_7;
/* DW6 */
u4Byte rsvd_8;
} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0;
typedef struct _Phy_Status_Rpt_Jaguar2_Type1 {
/* DW0 and DW1 */
u1Byte page_num;
u1Byte pwdb[4];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte l_rxsc: 4;
u1Byte ht_rxsc: 4;
#else
u1Byte ht_rxsc: 4;
u1Byte l_rxsc: 4;
#endif
u1Byte channel;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte band: 2;
u1Byte rsvd_0: 1;
u1Byte hw_antsw_occu: 1;
u1Byte gnt_bt: 1;
u1Byte ldpc: 1;
u1Byte stbc: 1;
u1Byte beamformed: 1;
#else
u1Byte beamformed: 1;
u1Byte stbc: 1;
u1Byte ldpc: 1;
u1Byte gnt_bt: 1;
u1Byte hw_antsw_occu: 1;
u1Byte rsvd_0: 1;
u1Byte band: 2;
#endif
/* DW2 */
u2Byte lsig_length;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_a: 3;
u1Byte antidx_b: 3;
u1Byte rsvd_1: 2;
u1Byte antidx_c: 3;
u1Byte antidx_d: 3;
u1Byte rsvd_2: 2;
#else
u1Byte rsvd_1: 2;
u1Byte antidx_b: 3;
u1Byte antidx_a: 3;
u1Byte rsvd_2: 2;
u1Byte antidx_d: 3;
u1Byte antidx_c: 3;
#endif
/* DW3 */
u1Byte paid;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte paid_msb: 1;
u1Byte gid: 6;
u1Byte rsvd_3: 1;
#else
u1Byte rsvd_3: 1;
u1Byte gid: 6;
u1Byte paid_msb: 1;
#endif
u1Byte intf_pos;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte intf_pos_msb: 1;
u1Byte rsvd_4: 2;
u1Byte nb_intf_flag: 1;
u1Byte rf_mode: 2;
u1Byte rsvd_5: 2;
#else
u1Byte rsvd_5: 2;
u1Byte rf_mode: 2;
u1Byte nb_intf_flag: 1;
u1Byte rsvd_4: 2;
u1Byte intf_pos_msb: 1;
#endif
/* DW4 */
s1Byte rxevm[4]; /* s(8,1) */
/* DW5 */
s1Byte cfo_tail[4]; /* s(8,7) */
/* DW6 */
s1Byte rxsnr[4]; /* s(8,1) */
} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1;
typedef struct _Phy_Status_Rpt_Jaguar2_Type2 {
/* DW0 ane DW1 */
u1Byte page_num;
u1Byte pwdb[4];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte l_rxsc: 4;
u1Byte ht_rxsc: 4;
#else
u1Byte ht_rxsc: 4;
u1Byte l_rxsc: 4;
#endif
u1Byte channel;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte band: 2;
u1Byte rsvd_0: 1;
u1Byte hw_antsw_occu: 1;
u1Byte gnt_bt: 1;
u1Byte ldpc: 1;
u1Byte stbc: 1;
u1Byte beamformed: 1;
#else
u1Byte beamformed: 1;
u1Byte stbc: 1;
u1Byte ldpc: 1;
u1Byte gnt_bt: 1;
u1Byte hw_antsw_occu: 1;
u1Byte rsvd_0: 1;
u1Byte band: 2;
#endif
/* DW2 */
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte shift_l_map: 6;
u1Byte rsvd_1: 2;
#else
u1Byte rsvd_1: 2;
u1Byte shift_l_map: 6;
#endif
u1Byte cnt_pw2cca;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte agc_table_a: 4;
u1Byte agc_table_b: 4;
u1Byte agc_table_c: 4;
u1Byte agc_table_d: 4;
#else
u1Byte agc_table_b: 4;
u1Byte agc_table_a: 4;
u1Byte agc_table_d: 4;
u1Byte agc_table_c: 4;
#endif
/* DW3 ~ DW6*/
u1Byte cnt_cca2agc_rdy;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain_a: 6;
u1Byte rsvd_2: 1;
u1Byte trsw_a: 1;
u1Byte gain_b: 6;
u1Byte rsvd_3: 1;
u1Byte trsw_b: 1;
u1Byte gain_c: 6;
u1Byte rsvd_4: 1;
u1Byte trsw_c: 1;
u1Byte gain_d: 6;
u1Byte rsvd_5: 1;
u1Byte trsw_d: 1;
u1Byte aagc_step_a: 2;
u1Byte aagc_step_b: 2;
u1Byte aagc_step_c: 2;
u1Byte aagc_step_d: 2;
#else
u1Byte trsw_a: 1;
u1Byte rsvd_2: 1;
u1Byte gain_a: 6;
u1Byte trsw_b: 1;
u1Byte rsvd_3: 1;
u1Byte gain_b: 6;
u1Byte trsw_c: 1;
u1Byte rsvd_4: 1;
u1Byte gain_c: 6;
u1Byte trsw_d: 1;
u1Byte rsvd_5: 1;
u1Byte gain_d: 6;
u1Byte aagc_step_d: 2;
u1Byte aagc_step_c: 2;
u1Byte aagc_step_b: 2;
u1Byte aagc_step_a: 2;
#endif
u1Byte ht_aagc_gain[4];
u1Byte dagc_gain[4];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte counter: 6;
u1Byte rsvd_6: 2;
u1Byte syn_count: 5;
u1Byte rsvd_7:3;
#else
u1Byte rsvd_6: 2;
u1Byte counter: 6;
u1Byte rsvd_7:3;
u1Byte syn_count: 5;
#endif
} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2;
/*==============================================*/
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_NoiseMonitor.c
Executable
+299
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@@ -0,0 +1,299 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
//#include "Mp_Precomp.h"
#include "phydm_precomp.h"
#include "phydm_NoiseMonitor.h"
//=================================================
// This function is for inband noise test utility only
// To obtain the inband noise level(dbm), do the following.
// 1. disable DIG and Power Saving
// 2. Set initial gain = 0x1a
// 3. Stop updating idle time pwer report (for driver read)
// - 0x80c[25]
//
//=================================================
#define Valid_Min -35
#define Valid_Max 10
#define ValidCnt 5
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time)
{
u4Byte tmp4b;
u1Byte max_rf_path=0,rf_path;
u1Byte reg_c50, reg_c58,valid_done=0;
struct noise_level noise_data;
u32 start = 0, func_start=0, func_end = 0;
func_start = ODM_GetCurrentTime(pDM_Odm);
pDM_Odm->noise_level.noise_all = 0;
if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R))
max_rf_path = 2;
else
max_rf_path = 1;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n"));
ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level));
//
// Step 1. Disable DIG && Set initial gain.
//
if(bPauseDIG)
{
odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue);
}
//
// Step 2. Disable all power save for read registers
//
//dcmd_DebugControlPowerSave(pAdapter, PSDisable);
//
// Step 3. Get noise power level
//
start = ODM_GetCurrentTime(pDM_Odm);
while(1)
{
//Stop updating idle time pwer report (for driver read)
ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1);
//Read Noise Floor Report
tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord );
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b));
//ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain);
//if(max_rf_path == 2)
// ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain);
//update idle time pwer report per 5us
ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0);
noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff);
noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n",
noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B]));
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path];
noise_data.sval[rf_path] /= 2;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n",
noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B]));
//ODM_delay_ms(10);
//ODM_sleep_ms(10);
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
if( (noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min))
{
noise_data.valid_cnt[rf_path]++;
noise_data.sum[rf_path] += noise_data.sval[rf_path];
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("RF_Path:%d Valid sval = %d\n", rf_path,noise_data.sval[rf_path]));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path]));
if(noise_data.valid_cnt[rf_path] == ValidCnt)
{
valid_done++;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("After divided, RF_Path:%d ,sum = %d \n", rf_path,noise_data.sum[rf_path]));
}
}
}
//printk("####### valid_done:%d #############\n",valid_done);
if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time))
{
for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++)
{
//printk("%s PATH_%d - sum = %d, valid_cnt = %d \n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]);
if(noise_data.valid_cnt[rf_path])
noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path];
else
noise_data.sum[rf_path] = 0;
}
break;
}
}
reg_c50 = (s4Byte)ODM_GetBBReg(pDM_Odm,rOFDM0_XAAGCCore1,bMaskByte0);
reg_c50 &= ~BIT7;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50));
pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = -110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A];
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A];
if(max_rf_path == 2){
reg_c58 = (s4Byte)ODM_GetBBReg(pDM_Odm,rOFDM0_XBAGCCore1,bMaskByte0);
reg_c58 &= ~BIT7;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58));
pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = -110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B];
pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B];
}
pDM_Odm->noise_level.noise_all /= max_rf_path;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n",
pDM_Odm->noise_level.noise[ODM_RF_PATH_A],
pDM_Odm->noise_level.noise[ODM_RF_PATH_B]));
//
// Step 4. Recover the Dig
//
if(bPauseDIG)
{
odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue);
}
func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n"));
return pDM_Odm->noise_level.noise_all;
}
s2Byte
odm_InbandNoise_Monitor_ACSeries(PDM_ODM_T pDM_Odm, u8 bPauseDIG, u8 IGIValue, u32 max_time
)
{
s4Byte rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/
s4Byte value32, pwdb_A = 0, sval, noise, sum;
BOOLEAN pd_flag;
u1Byte i, valid_cnt;
u32 start = 0, func_start = 0, func_end = 0;
if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821)))
return 0;
func_start = ODM_GetCurrentTime(pDM_Odm);
pDM_Odm->noise_level.noise_all = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() ==>\n"));
/* Step 1. Disable DIG && Set initial gain. */
if (bPauseDIG)
odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue);
/* Step 2. Disable all power save for read registers */
/*dcmd_DebugControlPowerSave(pAdapter, PSDisable); */
/* Step 3. Get noise power level */
start = ODM_GetCurrentTime(pDM_Odm);
/* reset counters */
sum = 0;
valid_cnt = 0;
/* Step 3. Get noise power level */
while (1) {
/*Set IGI=0x1C */
ODM_Write_DIG(pDM_Odm, 0x1C);
/*stop CK320&CK88 */
ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 1);
/*Read Path-A */
ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, 0x200); /*set debug port*/
value32 = ODM_GetBBReg(pDM_Odm, 0xFA0, bMaskDWord); /*read debug port*/
rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/
rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/
pd_flag = (BOOLEAN) ((value32 & BIT31) >> 31);
/*Not in packet detection period or Tx state */
if ((!pd_flag) || (rxi_buf_anta != 0x200)) {
/*sign conversion*/
rxi_buf_anta = ODM_SignConversion(rxi_buf_anta, 10);
rxq_buf_anta = ODM_SignConversion(rxq_buf_anta, 10);
pwdb_A = ODM_PWdB_Conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF));
}
/*BB Reset*/
ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) & (~BIT0));
ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) | BIT0);
/*Start CK320&CK88*/
ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 0);
sval = pwdb_A;
if (sval < 0 && sval >= -27) {
if (valid_cnt < ValidCnt) {
valid_cnt++;
sum += sval;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum));
if ((valid_cnt >= ValidCnt) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) {
sum /= valid_cnt;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum));
break;
}
}
}
}
/*ADC backoff is 12dB,*/
/*Ptarget=0x1C-110=-82dBm*/
noise = sum + 12 + 0x1C - 110;
/*Offset*/
noise = noise - 3;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise));
pDM_Odm->noise_level.noise_all = (s2Byte)noise;
/* Step 4. Recover the Dig*/
if (bPauseDIG)
odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue);
func_end = ODM_GetProgressingTime(pDM_Odm, func_start);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() <==\n"));
return pDM_Odm->noise_level.noise_all;
}
s2Byte
ODM_InbandNoise_Monitor(PVOID pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
return odm_InbandNoise_Monitor_ACSeries(pDM_Odm, bPauseDIG, IGIValue, max_time);
else
return odm_InbandNoise_Monitor_NSeries(pDM_Odm, bPauseDIG, IGIValue, max_time);
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_NoiseMonitor.h
Executable
+49
View File
@@ -0,0 +1,49 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
*****************************************************************************/
#ifndef __ODMNOISEMONITOR_H__
#define __ODMNOISEMONITOR_H__
#define ODM_MAX_CHANNEL_NUM 38//14+24
struct noise_level
{
//u1Byte value_a, value_b;
u1Byte value[MAX_RF_PATH];
//s1Byte sval_a, sval_b;
s1Byte sval[MAX_RF_PATH];
//s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0;
//s4Byte noise[ODM_RF_PATH_MAX];
s4Byte sum[MAX_RF_PATH];
//u1Byte valid_cnt_a=0, valid_cnt_b=0,
u1Byte valid[MAX_RF_PATH];
u1Byte valid_cnt[MAX_RF_PATH];
};
typedef struct _ODM_NOISE_MONITOR_
{
s1Byte noise[MAX_RF_PATH];
s2Byte noise_all;
}ODM_NOISE_MONITOR;
s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_PathDiv.c
Executable
+810
View File
@@ -0,0 +1,810 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "phydm_precomp.h"
#if(defined(CONFIG_PATH_DIVERSITY))
#if RTL8814A_SUPPORT
VOID
phydm_dtp_fix_tx_path(
IN PVOID pDM_VOID,
IN u1Byte path
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv;
u1Byte i,num_enable_path=0;
if(path==pDM_PathDiv->pre_tx_path)
{
return;
}
else
{
pDM_PathDiv->pre_tx_path=path;
}
ODM_SetBBReg( pDM_Odm, 0x93c, BIT18|BIT19, 3);
for(i=0; i<4; i++)
{
if(path&BIT(i))
num_enable_path++;
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Number of trun-on path : (( %d ))\n", num_enable_path));
if(num_enable_path == 1)
{
ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path);
if(path==PHYDM_A)//1-1
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n"));
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
}
else if(path==PHYDM_B)//1-2
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n"));
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0);
}
else if(path==PHYDM_C)//1-3
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n"));
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0);
}
else if(path==PHYDM_D)//1-4
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n"));
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 0);
}
}
else if(num_enable_path == 2)
{
ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path);
ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path);
if(path==PHYDM_AB)//2-1
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1);
}
else if(path==PHYDM_AC)//2-2
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1);
}
else if(path==PHYDM_AD)//2-3
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1);
}
else if(path==PHYDM_BC)//2-4
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1);
}
else if(path==PHYDM_BD)//2-5
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1);
}
else if(path==PHYDM_CD)//2-6
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1);
}
}
else if(num_enable_path == 3)
{
ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path);
ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path);
ODM_SetBBReg( pDM_Odm, 0x940, 0xf0000, path);
if(path==PHYDM_ABC)//3-1
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 2);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1);
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 2);
//set for 3ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1);
ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 2);
}
else if(path==PHYDM_ABD)//3-2
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1);
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2);
//set for 3ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1);
ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2);
}
else if(path==PHYDM_ACD)//3-3
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1);
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2);
//set for 3ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1);
ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2);
}
else if(path==PHYDM_BCD)//3-4
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n"));
//set for 1ss
ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1);
ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2);
//set for 2ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1);
ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2);
//set for 3ss
ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 0);
ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1);
ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2);
}
}
else if(num_enable_path == 4)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n"));
}
}
VOID
phydm_find_default_path(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv;
u4Byte rssi_avg_a=0, rssi_avg_b=0, rssi_avg_c=0, rssi_avg_d=0, rssi_avg_bcd=0;
u4Byte rssi_total_a=0, rssi_total_b=0, rssi_total_c=0, rssi_total_d=0;
//2 Default Path Selection By RSSI
rssi_avg_a = (pDM_PathDiv->path_a_cnt_all > 0)? (pDM_PathDiv->path_a_sum_all / pDM_PathDiv->path_a_cnt_all) :0 ;
rssi_avg_b = (pDM_PathDiv->path_b_cnt_all > 0)? (pDM_PathDiv->path_b_sum_all / pDM_PathDiv->path_b_cnt_all) :0 ;
rssi_avg_c = (pDM_PathDiv->path_c_cnt_all > 0)? (pDM_PathDiv->path_c_sum_all / pDM_PathDiv->path_c_cnt_all) :0 ;
rssi_avg_d = (pDM_PathDiv->path_d_cnt_all > 0)? (pDM_PathDiv->path_d_sum_all / pDM_PathDiv->path_d_cnt_all) :0 ;
pDM_PathDiv->path_a_sum_all = 0;
pDM_PathDiv->path_a_cnt_all = 0;
pDM_PathDiv->path_b_sum_all = 0;
pDM_PathDiv->path_b_cnt_all = 0;
pDM_PathDiv->path_c_sum_all = 0;
pDM_PathDiv->path_c_cnt_all = 0;
pDM_PathDiv->path_d_sum_all = 0;
pDM_PathDiv->path_d_cnt_all = 0;
if(pDM_PathDiv->use_path_a_as_default_ant == 1)
{
rssi_avg_bcd=(rssi_avg_b+rssi_avg_c+rssi_avg_d)/3;
if( (rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd )
{
pDM_PathDiv->is_pathA_exist=TRUE;
pDM_PathDiv->default_path=PATH_A;
}
else
{
pDM_PathDiv->is_pathA_exist=FALSE;
}
}
else
{
if( (rssi_avg_a >=rssi_avg_b) && (rssi_avg_a >=rssi_avg_c)&&(rssi_avg_a >=rssi_avg_d))
pDM_PathDiv->default_path=PATH_A;
else if( (rssi_avg_b >=rssi_avg_c)&&(rssi_avg_b >=rssi_avg_d))
pDM_PathDiv->default_path=PATH_B;
else if( rssi_avg_c >=rssi_avg_d)
pDM_PathDiv->default_path=PATH_C;
else
pDM_PathDiv->default_path=PATH_D;
}
}
VOID
phydm_candidate_dtp_update(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv;
pDM_PathDiv->num_candidate=3;
if(pDM_PathDiv->use_path_a_as_default_ant == 1)
{
if(pDM_PathDiv->num_tx_path==3)
{
if(pDM_PathDiv->is_pathA_exist)
{
pDM_PathDiv->ant_candidate_1 = PHYDM_ABC;
pDM_PathDiv->ant_candidate_2 = PHYDM_ABD;
pDM_PathDiv->ant_candidate_3 = PHYDM_ACD;
}
else // use path BCD
{
pDM_PathDiv->num_candidate=1;
phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD);
return;
}
}
else if(pDM_PathDiv->num_tx_path==2)
{
if(pDM_PathDiv->is_pathA_exist)
{
pDM_PathDiv->ant_candidate_1 = PHYDM_AB;
pDM_PathDiv->ant_candidate_2 = PHYDM_AC;
pDM_PathDiv->ant_candidate_3 = PHYDM_AD;
}
else
{
pDM_PathDiv->ant_candidate_1 = PHYDM_BC;
pDM_PathDiv->ant_candidate_2 = PHYDM_BD;
pDM_PathDiv->ant_candidate_3 = PHYDM_CD;
}
}
}
else
{
//2 3 TX Mode
if(pDM_PathDiv->num_tx_path==3)//choose 3 ant form 4
{
if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3
{
pDM_PathDiv->ant_candidate_1 = PHYDM_ABC;
pDM_PathDiv->ant_candidate_2 = PHYDM_ABD;
pDM_PathDiv->ant_candidate_3 = PHYDM_ACD;
}
else if(pDM_PathDiv->default_path==PATH_B)
{
pDM_PathDiv->ant_candidate_1 = PHYDM_ABC;
pDM_PathDiv->ant_candidate_2 = PHYDM_ABD;
pDM_PathDiv->ant_candidate_3 = PHYDM_BCD;
}
else if(pDM_PathDiv->default_path == PATH_C)
{
pDM_PathDiv->ant_candidate_1 = PHYDM_ABC;
pDM_PathDiv->ant_candidate_2 = PHYDM_ACD;
pDM_PathDiv->ant_candidate_3 = PHYDM_BCD;
}
else if(pDM_PathDiv->default_path == PATH_D)
{
pDM_PathDiv->ant_candidate_1 = PHYDM_ABD;
pDM_PathDiv->ant_candidate_2 = PHYDM_ACD;
pDM_PathDiv->ant_candidate_3 = PHYDM_BCD;
}
}
//2 2 TX Mode
else if(pDM_PathDiv->num_tx_path==2)//choose 2 ant form 4
{
if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3
{
pDM_PathDiv->ant_candidate_1 = PHYDM_AB;
pDM_PathDiv->ant_candidate_2 = PHYDM_AC;
pDM_PathDiv->ant_candidate_3 = PHYDM_AD;
}
else if(pDM_PathDiv->default_path==PATH_B)
{
pDM_PathDiv->ant_candidate_1 = PHYDM_AB;
pDM_PathDiv->ant_candidate_2 = PHYDM_BC;
pDM_PathDiv->ant_candidate_3 = PHYDM_BD;
}
else if(pDM_PathDiv->default_path == PATH_C)
{
pDM_PathDiv->ant_candidate_1 = PHYDM_AC;
pDM_PathDiv->ant_candidate_2 = PHYDM_BC;
pDM_PathDiv->ant_candidate_3 = PHYDM_CD;
}
else if(pDM_PathDiv->default_path == PATH_D)
{
pDM_PathDiv->ant_candidate_1= PHYDM_AD;
pDM_PathDiv->ant_candidate_2 = PHYDM_BD;
pDM_PathDiv->ant_candidate_3= PHYDM_CD;
}
}
}
}
VOID
phydm_dynamic_tx_path(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv;
PSTA_INFO_T pEntry;
u4Byte i;
u1Byte num_client=0;
u1Byte H2C_Parameter[6] ={0};
if(!pDM_Odm->bLinked) //bLinked==False
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n"));
if(pDM_PathDiv->bBecomeLinked == TRUE)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n"));
pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked;
}
return;
}
else
{
if(pDM_PathDiv->bBecomeLinked ==FALSE)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n"));
pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked;
}
}
//2 [Period CTRL]
if(pDM_PathDiv->dtp_period >=2)
{
pDM_PathDiv->dtp_period=0;
}
else
{
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",pDM_PathDiv->dtp_period));
pDM_PathDiv->dtp_period++;
return;
}
//2 [Fix Path]
if (pDM_Odm->path_select != PHYDM_AUTO_PATH)
{
return;
}
//2 [Check Bfer]
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (BEAMFORMING_SUPPORT == 1)
{
BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap);
if( BeamformCap & BEAMFORMER_CAP ) // BFmer On && Div On -> Div Off
{
if( pDM_PathDiv->fix_path_bfer == 0)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : OFF ] BFmer ==1 \n"));
pDM_PathDiv->fix_path_bfer = 1 ;
}
return;
}
else // BFmer Off && Div Off -> Div On
{
if( pDM_PathDiv->fix_path_bfer == 1 )
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : ON ] BFmer ==0 \n"));
pDM_PathDiv->fix_path_bfer = 0;
}
}
}
#endif
#endif
if(pDM_PathDiv->use_path_a_as_default_ant ==1)
{
phydm_find_default_path(pDM_Odm);
phydm_candidate_dtp_update(pDM_Odm);
}
else
{
if( pDM_PathDiv->dtp_state == PHYDM_DTP_INIT)
{
phydm_find_default_path(pDM_Odm);
phydm_candidate_dtp_update(pDM_Odm);
pDM_PathDiv->dtp_state = PHYDM_DTP_RUNNING_1;
}
else if( pDM_PathDiv->dtp_state == PHYDM_DTP_RUNNING_1)
{
pDM_PathDiv->dtp_check_patha_counter++;
if(pDM_PathDiv->dtp_check_patha_counter>=NUM_RESET_DTP_PERIOD)
{
pDM_PathDiv->dtp_check_patha_counter=0;
pDM_PathDiv->dtp_state = PHYDM_DTP_INIT;
}
//2 Search space update
else
{
// 1. find the worst candidate
// 2. repalce the worst candidate
}
}
}
//2 Dynamic Path Selection H2C
if(pDM_PathDiv->num_candidate == 1)
{
return;
}
else
{
H2C_Parameter[0] = pDM_PathDiv->num_candidate;
H2C_Parameter[1] = pDM_PathDiv->num_tx_path;
H2C_Parameter[2] = pDM_PathDiv->ant_candidate_1;
H2C_Parameter[3] = pDM_PathDiv->ant_candidate_2;
H2C_Parameter[4] = pDM_PathDiv->ant_candidate_3;
ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, H2C_Parameter);
}
}
VOID
phydm_dynamic_tx_path_init(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv);
PADAPTER pAdapter = pDM_Odm->Adapter;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
USB_MODE_MECH *pUsbModeMech = &pAdapter->UsbModeMechanism;
#endif
u1Byte search_space_2[NUM_CHOOSE2_FROM4]= {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD };
u1Byte search_space_3[NUM_CHOOSE3_FROM4]= {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
pDM_PathDiv->is_u3_mode = (pUsbModeMech->CurUsbMode==USB_MODE_U3)? 1 : 0 ;
#else
pDM_PathDiv->is_u3_mode = 1;
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX Path Init 8814\n"));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("is_u3_mode = (( %d ))\n", pDM_PathDiv->is_u3_mode));
memcpy(&(pDM_PathDiv->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4);
memcpy(&(pDM_PathDiv->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4);
pDM_PathDiv->use_path_a_as_default_ant= 1;
pDM_PathDiv->dtp_state = PHYDM_DTP_INIT;
pDM_Odm->path_select = PHYDM_AUTO_PATH;
pDM_PathDiv->path_div_type = PHYDM_4R_PATH_DIV;
if(pDM_PathDiv->is_u3_mode )
{
pDM_PathDiv->num_tx_path=3;
phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD);/* 3TX Set Init TX Path*/
}
else
{
pDM_PathDiv->num_tx_path=2;
phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BC);/* 2TX // Set Init TX Path*/
}
}
VOID
phydm_process_rssi_for_path_div(
IN OUT PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void;
PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void;
pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv);
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID)
{
if(pPktinfo->DataRate > ODM_RATE11M)
{
if(pDM_PathDiv->path_div_type == PHYDM_4R_PATH_DIV)
{
#if RTL8814A_SUPPORT
if(pDM_Odm->SupportICType & ODM_RTL8814A)
{
pDM_PathDiv->path_a_sum_all+=pPhyInfo->RxMIMOSignalStrength[0];
pDM_PathDiv->path_a_cnt_all++;
pDM_PathDiv->path_b_sum_all+=pPhyInfo->RxMIMOSignalStrength[1];
pDM_PathDiv->path_b_cnt_all++;
pDM_PathDiv->path_c_sum_all+=pPhyInfo->RxMIMOSignalStrength[2];
pDM_PathDiv->path_c_cnt_all++;
pDM_PathDiv->path_d_sum_all+=pPhyInfo->RxMIMOSignalStrength[3];
pDM_PathDiv->path_d_cnt_all++;
}
#endif
}
else
{
pDM_PathDiv->PathA_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[0];
pDM_PathDiv->PathA_Cnt[pPktinfo->StationID]++;
pDM_PathDiv->PathB_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[1];
pDM_PathDiv->PathB_Cnt[pPktinfo->StationID]++;
}
}
}
}
#endif //#if RTL8814A_SUPPORT
VOID
odm_pathdiv_debug(
IN PVOID pDM_VOID,
IN u4Byte *const dm_value,
IN u4Byte *_used,
OUT char *output,
IN u4Byte *_out_len
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv);
u4Byte used = *_used;
u4Byte out_len = *_out_len;
pDM_Odm->path_select = (dm_value[0] & 0xf);
PHYDM_SNPRINTF((output+used, out_len-used,"Path_select = (( 0x%x ))\n",pDM_Odm->path_select ));
//2 [Fix Path]
if (pDM_Odm->path_select != PHYDM_AUTO_PATH)
{
PHYDM_SNPRINTF((output+used, out_len-used,"Trun on path [%s%s%s%s]\n",
((pDM_Odm->path_select) & 0x1)?"A":"",
((pDM_Odm->path_select) & 0x2)?"B":"",
((pDM_Odm->path_select) & 0x4)?"C":"",
((pDM_Odm->path_select) & 0x8)?"D":"" ));
phydm_dtp_fix_tx_path( pDM_Odm, pDM_Odm->path_select );
}
else
{
PHYDM_SNPRINTF((output+used, out_len-used,"%s\n","Auto Path"));
}
}
#endif // #if(defined(CONFIG_PATH_DIVERSITY))
VOID
phydm_c2h_dtp_handler(
IN PVOID pDM_VOID,
IN pu1Byte CmdBuf,
IN u1Byte CmdLen
)
{
#if(defined(CONFIG_PATH_DIVERSITY))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv);
u1Byte macid = CmdBuf[0];
u1Byte target = CmdBuf[1];
u1Byte nsc_1 = CmdBuf[2];
u1Byte nsc_2 = CmdBuf[3];
u1Byte nsc_3 = CmdBuf[4];
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Target_candidate = (( %d ))\n", target));
/*
if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3))
{
phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_1);
}
else if( nsc_2 >= nsc_3)
{
phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_2);
}
else
{
phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_3);
}
*/
#endif
}
VOID
odm_PathDiversity(
IN PVOID pDM_VOID
)
{
#if(defined(CONFIG_PATH_DIVERSITY))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n"));
return;
}
#if RTL8812A_SUPPORT
if(pDM_Odm->SupportICType & ODM_RTL8812)
ODM_PathDiversity_8812A(pDM_Odm);
else
#endif
#if RTL8814A_SUPPORT
if(pDM_Odm->SupportICType & ODM_RTL8814A)
phydm_dynamic_tx_path(pDM_Odm);
else
#endif
{}
#endif
}
VOID
odm_PathDiversityInit(
IN PVOID pDM_VOID
)
{
#if(defined(CONFIG_PATH_DIVERSITY))
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
/*pDM_Odm->SupportAbility |= ODM_BB_PATH_DIV;*/
if(pDM_Odm->mp_mode == TRUE)
return;
if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n"));
return;
}
#if RTL8812A_SUPPORT
if(pDM_Odm->SupportICType & ODM_RTL8812)
ODM_PathDiversityInit_8812A(pDM_Odm);
else
#endif
#if RTL8814A_SUPPORT
if(pDM_Odm->SupportICType & ODM_RTL8814A)
phydm_dynamic_tx_path_init(pDM_Odm);
else
#endif
{}
#endif
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
//
// 2011/12/02 MH Copy from MP oursrc for temporarily test.
//
VOID
odm_PathDivChkAntSwitchCallback(
PRT_TIMER pTimer
)
{
}
VOID
odm_PathDivChkAntSwitchWorkitemCallback(
IN PVOID pContext
)
{
}
VOID
odm_CCKTXPathDiversityCallback(
PRT_TIMER pTimer
)
{
}
VOID
odm_CCKTXPathDiversityWorkItemCallback(
IN PVOID pContext
)
{
}
u1Byte
odm_SwAntDivSelectScanChnl(
IN PADAPTER Adapter
)
{
return 0;
}
VOID
odm_SwAntDivConstructScanChnl(
IN PADAPTER Adapter,
IN u1Byte ScanChnl
)
{
}
#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_PathDiv.h
Executable
+324
View File
@@ -0,0 +1,324 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMPATHDIV_H__
#define __PHYDMPATHDIV_H__
/*#define PATHDIV_VERSION "2.0" //2014.11.04*/
#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/
#if(defined(CONFIG_PATH_DIVERSITY))
#define USE_PATH_A_AS_DEFAULT_ANT //for 8814 dynamic TX path selection
#define NUM_RESET_DTP_PERIOD 5
#define ANT_DECT_RSSI_TH 3
#define PATH_A 1
#define PATH_B 2
#define PATH_C 3
#define PATH_D 4
#define PHYDM_AUTO_PATH 0
#define PHYDM_FIX_PATH 1
#define NUM_CHOOSE2_FROM4 6
#define NUM_CHOOSE3_FROM4 4
#define PHYDM_A BIT0
#define PHYDM_B BIT1
#define PHYDM_C BIT2
#define PHYDM_D BIT3
#define PHYDM_AB (BIT0 | BIT1) // 0
#define PHYDM_AC (BIT0 | BIT2) // 1
#define PHYDM_AD (BIT0 | BIT3) // 2
#define PHYDM_BC (BIT1 | BIT2) // 3
#define PHYDM_BD (BIT1 | BIT3) // 4
#define PHYDM_CD (BIT2 | BIT3) // 5
#define PHYDM_ABC (BIT0 | BIT1 | BIT2) /* 0*/
#define PHYDM_ABD (BIT0 | BIT1 | BIT3) /* 1*/
#define PHYDM_ACD (BIT0 | BIT2 | BIT3) /* 2*/
#define PHYDM_BCD (BIT1 | BIT2 | BIT3) /* 3*/
#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3)
typedef enum dtp_state
{
PHYDM_DTP_INIT=1,
PHYDM_DTP_RUNNING_1
}PHYDM_DTP_STATE;
typedef enum path_div_type
{
PHYDM_2R_PATH_DIV = 1,
PHYDM_4R_PATH_DIV = 2
}PHYDM_PATH_DIV_TYPE;
VOID
phydm_process_rssi_for_path_div(
IN OUT PVOID pDM_VOID,
IN PVOID p_phy_info_void,
IN PVOID p_pkt_info_void
);
typedef struct _ODM_PATH_DIVERSITY_
{
u1Byte RespTxPath;
u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u2Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u2Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte path_div_type;
#if RTL8814A_SUPPORT
u4Byte path_a_sum_all;
u4Byte path_b_sum_all;
u4Byte path_c_sum_all;
u4Byte path_d_sum_all;
u4Byte path_a_cnt_all;
u4Byte path_b_cnt_all;
u4Byte path_c_cnt_all;
u4Byte path_d_cnt_all;
u1Byte dtp_period;
BOOLEAN bBecomeLinked;
BOOLEAN is_u3_mode;
u1Byte num_tx_path;
u1Byte default_path;
u1Byte num_candidate;
u1Byte ant_candidate_1;
u1Byte ant_candidate_2;
u1Byte ant_candidate_3;
u1Byte dtp_state;
u1Byte dtp_check_patha_counter;
BOOLEAN fix_path_bfer;
u1Byte search_space_2[NUM_CHOOSE2_FROM4];
u1Byte search_space_3[NUM_CHOOSE3_FROM4];
u1Byte pre_tx_path;
u1Byte use_path_a_as_default_ant;
BOOLEAN is_pathA_exist;
#endif
}PATHDIV_T, *pPATHDIV_T;
#endif //#if(defined(CONFIG_PATH_DIVERSITY))
VOID
phydm_c2h_dtp_handler(
IN PVOID pDM_VOID,
IN pu1Byte CmdBuf,
IN u1Byte CmdLen
);
VOID
odm_PathDiversityInit(
IN PVOID pDM_VOID
);
VOID
odm_PathDiversity(
IN PVOID pDM_VOID
);
VOID
odm_pathdiv_debug(
IN PVOID pDM_VOID,
IN u4Byte *const dm_value,
IN u4Byte *_used,
OUT char *output,
IN u4Byte *_out_len
);
//1 [OLD IC]--------------------------------------------------------------------------------
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
//#define PATHDIV_ENABLE 1
#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi
#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C
typedef struct _PathDiv_Parameter_define_
{
u4Byte org_5g_RegE30;
u4Byte org_5g_RegC14;
u4Byte org_5g_RegCA0;
u4Byte swt_5g_RegE30;
u4Byte swt_5g_RegC14;
u4Byte swt_5g_RegCA0;
//for 2G IQK information
u4Byte org_2g_RegC80;
u4Byte org_2g_RegC4C;
u4Byte org_2g_RegC94;
u4Byte org_2g_RegC14;
u4Byte org_2g_RegCA0;
u4Byte swt_2g_RegC80;
u4Byte swt_2g_RegC4C;
u4Byte swt_2g_RegC94;
u4Byte swt_2g_RegC14;
u4Byte swt_2g_RegCA0;
}PATHDIV_PARA,*pPATHDIV_PARA;
VOID
odm_PathDiversityInit_92C(
IN PADAPTER Adapter
);
VOID
odm_2TPathDiversityInit_92C(
IN PADAPTER Adapter
);
VOID
odm_1TPathDiversityInit_92C(
IN PADAPTER Adapter
);
BOOLEAN
odm_IsConnected_92C(
IN PADAPTER Adapter
);
BOOLEAN
ODM_PathDiversityBeforeLink92C(
//IN PADAPTER Adapter
IN PDM_ODM_T pDM_Odm
);
VOID
odm_PathDiversityAfterLink_92C(
IN PADAPTER Adapter
);
VOID
odm_SetRespPath_92C(
IN PADAPTER Adapter,
IN u1Byte DefaultRespPath
);
VOID
odm_OFDMTXPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_CCKTXPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_ResetPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_CCKTXPathDiversityCallback(
PRT_TIMER pTimer
);
VOID
odm_CCKTXPathDiversityWorkItemCallback(
IN PVOID pContext
);
VOID
odm_PathDivChkAntSwitchCallback(
PRT_TIMER pTimer
);
VOID
odm_PathDivChkAntSwitchWorkitemCallback(
IN PVOID pContext
);
VOID
odm_PathDivChkAntSwitch(
PDM_ODM_T pDM_Odm
);
VOID
ODM_CCKPathDiversityChkPerPktRssi(
PADAPTER Adapter,
BOOLEAN bIsDefPort,
BOOLEAN bMatchBSSID,
PRT_WLAN_STA pEntry,
PRT_RFD pRfd,
pu1Byte pDesc
);
VOID
ODM_PathDivChkPerPktRssi(
PADAPTER Adapter,
BOOLEAN bIsDefPort,
BOOLEAN bMatchBSSID,
PRT_WLAN_STA pEntry,
PRT_RFD pRfd
);
VOID
ODM_PathDivRestAfterLink(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_FillTXPathInTXDESC(
IN PADAPTER Adapter,
IN PRT_TCB pTcb,
IN pu1Byte pDesc
);
VOID
odm_PathDivInit_92D(
IN PDM_ODM_T pDM_Odm
);
u1Byte
odm_SwAntDivSelectScanChnl(
IN PADAPTER Adapter
);
VOID
odm_SwAntDivConstructScanChnl(
IN PADAPTER Adapter,
IN u1Byte ScanChnl
);
#endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
#endif //#ifndef __ODMPATHDIV_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_PowerTracking_AP.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_PowerTracking_AP.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#define POWRTRACKING_VERSION "1.1"
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifdef RTK_AC_SUPPORT
#define ODM_IC_11AC_SERIES_SUPPORT 1
#else
#define ODM_IC_11AC_SERIES_SUPPORT 0
#endif
#else
#define ODM_IC_11AC_SERIES_SUPPORT 1
#endif
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define DELTA_SWINGIDX_SIZE 30
#define BAND_NUM 3
#define MAX_RF_PATH 4
#define TXSCALE_TABLE_SIZE 37
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#define IQK_BB_REG_NUM 9
#define HP_THERMAL_NUM 8
#define AVG_THERMAL_NUM 8
#define IQK_Matrix_REG_NUM 8
//#define IQK_Matrix_Settings_NUM 1+24+21
#define IQK_Matrix_Settings_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
#if !defined(_OUTSRC_COEXIST)
#define OFDM_TABLE_SIZE_92D 43
#define OFDM_TABLE_SIZE 37
#define CCK_TABLE_SIZE 33
#define CCK_TABLE_SIZE_88F 21
//#define OFDM_TABLE_SIZE_92E 54
//#define CCK_TABLE_SIZE_92E 54
extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D];
extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D];
extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];
extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16];
#endif
#define ODM_OFDM_TABLE_SIZE 37
#define ODM_CCK_TABLE_SIZE 33
// <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.
extern u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE];
extern u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE];
//extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E];
//extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8];
//extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8];
#ifdef CONFIG_WLAN_HAL_8192EE
#define OFDM_TABLE_SIZE_92E 54
#define CCK_TABLE_SIZE_92E 54
extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E];
extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8];
extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8];
#endif
#define OFDM_TABLE_SIZE_8812 43
#define AVG_THERMAL_NUM_8812 4
#if(RTL8814A_SUPPORT == 1)
extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
#elif(ODM_IC_11AC_SERIES_SUPPORT)
extern unsigned int OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812];
#endif
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
typedef struct _IQK_MATRIX_REGS_SETTING{
BOOLEAN bIQKDone;
s4Byte Value[1][IQK_Matrix_REG_NUM];
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
typedef struct ODM_RF_Calibration_Structure
{
//for tx power tracking
u4Byte RegA24; // for TempCCK
s4Byte RegE94;
s4Byte RegE9C;
s4Byte RegEB4;
s4Byte RegEBC;
//u1Byte bTXPowerTracking;
u1Byte TXPowercount;
BOOLEAN bTXPowerTrackingInit;
BOOLEAN bTXPowerTracking;
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u1Byte TM_Trigger;
u1Byte InternalPA5G[2]; //pathA / pathB
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u1Byte ThermalValue;
u1Byte ThermalValue_LCK;
u1Byte ThermalValue_IQK;
u1Byte ThermalValue_DPK;
u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
u1Byte ThermalValue_AVG_index;
u1Byte ThermalValue_RxGain;
u1Byte ThermalValue_Crystal;
u1Byte ThermalValue_DPKstore;
u1Byte ThermalValue_DPKtrack;
BOOLEAN TxPowerTrackingInProgress;
BOOLEAN bDPKenable;
BOOLEAN bReloadtxpowerindex;
u1Byte bRfPiEnable;
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
u1Byte bCCKinCH14;
u1Byte CCK_index;
u1Byte OFDM_index[MAX_RF_PATH];
s1Byte PowerIndexOffset;
s1Byte DeltaPowerIndex;
s1Byte DeltaPowerIndexLast;
BOOLEAN bTxPowerChanged;
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
u1Byte ThermalValue_HP_index;
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
BOOLEAN bNeedIQK;
u1Byte Delta_IQK;
u1Byte Delta_LCK;
u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
u1Byte BbSwingIdxOfdm[MAX_RF_PATH];
u1Byte BbSwingIdxOfdmCurrent;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH];
#else
u1Byte BbSwingIdxOfdmBase;
#endif
BOOLEAN BbSwingFlagOfdm;
u1Byte BbSwingIdxCck;
u1Byte BbSwingIdxCckCurrent;
u1Byte BbSwingIdxCckBase;
u1Byte DefaultOfdmIndex;
u1Byte DefaultCckIndex;
BOOLEAN BbSwingFlagCck;
s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH];
s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH];
s1Byte Remnant_CCKSwingIdx;
s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */
BOOLEAN Modify_TxAGC_Flag_PathA;
BOOLEAN Modify_TxAGC_Flag_PathB;
BOOLEAN Modify_TxAGC_Flag_PathC;
BOOLEAN Modify_TxAGC_Flag_PathD;
BOOLEAN Modify_TxAGC_Flag_PathA_CCK;
s1Byte KfreeOffset[MAX_RF_PATH];
//--------------------------------------------------------------------//
//for IQK
u4Byte RegC04;
u4Byte Reg874;
u4Byte RegC08;
u4Byte RegB68;
u4Byte RegB6C;
u4Byte Reg870;
u4Byte Reg860;
u4Byte Reg864;
BOOLEAN bIQKInitialized;
BOOLEAN bLCKInProgress;
BOOLEAN bAntennaDetected;
u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
u4Byte IQK_BB_backup_recover[9];
u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
//for APK
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u1Byte bAPKdone;
u1Byte bAPKThermalMeterIgnore;
u1Byte bDPdone;
u1Byte bDPPathAOK;
u1Byte bDPPathBOK;
/*Add by Yuchen for Kfree Phydm*/
u1Byte RegRfKFreeEnable; /*for registry*/
u1Byte RfKFreeEnable; /*for efuse enable check*/
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
VOID
odm_TXPowerTrackingCheckAP(
IN PVOID pDM_VOID
);
VOID
ODM_TXPowerTrackingCheck(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingThermalMeterInit(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingInit(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckMP(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckCE(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
VOID
odm_TXPowerTrackingCallbackThermalMeter92C(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingCallbackThermalMeter92D(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingDirectCall92C(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingThermalMeterCheck(
IN PADAPTER Adapter
);
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_RaInfo.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_RaInfo.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMRAINFO_H__
#define __PHYDMRAINFO_H__
/*#define RAINFO_VERSION "2.0" //2014.11.04*/
/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/
/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/
#define RAINFO_VERSION "3.3" /*2015.07.29 YuChen*/
#define HIGH_RSSI_THRESH 50
#define LOW_RSSI_THRESH 20
#define ACTIVE_TP_THRESHOLD 150
#define RA_RETRY_DESCEND_NUM 2
#define RA_RETRY_LIMIT_LOW 4
#define RA_RETRY_LIMIT_HIGH 32
#define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F)
#define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8821B|ODM_RTL8822B)
#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL
#define RAINFO_STBC_STATE BIT1
//#define RAINFO_LDPC_STATE BIT2
#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection
#define RAINFO_SHURTCUT_STATE BIT3
#define RAINFO_SHURTCUT_FLAG BIT4
#define RAINFO_INIT_RSSI_RATE_STATE BIT5
#define RAINFO_BF_STATE BIT6
#define RAINFO_BE_TX_STATE BIT7 // 1:TX
#define RA_MASK_CCK 0xf
#define RA_MASK_OFDM 0xff0
#define RA_MASK_HT1SS 0xff000
#define RA_MASK_HT2SS 0xff00000
/*#define RA_MASK_MCS3SS */
#define RA_MASK_HT4SS 0xff0
#define RA_MASK_VHT1SS 0x3ff000
#define RA_MASK_VHT2SS 0xffc00000
#if(DM_ODM_SUPPORT_TYPE == ODM_AP)
#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8881A |ODM_RTL8192E |ODM_RTL8812 |ODM_RTL8814A|ODM_RTL8822B)
#define RA_FIRST_MACID 1
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8703B)
#define RA_FIRST_MACID 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
/*#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8723B|ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8703B) */
#define RA_FIRST_MACID 0
#endif
#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#if(DM_ODM_SUPPORT_TYPE & ODM_AP)
#define DM_RATR_STA_ULTRA_LOW 4
#endif
#define DM_RA_RATE_UP 1
#define DM_RA_RATE_DOWN 2
typedef enum _phydm_arfr_num {
ARFR_0_RATE_ID = 0x9,
ARFR_1_RATE_ID = 0xa,
ARFR_2_RATE_ID = 0xb,
ARFR_3_RATE_ID = 0xc,
ARFR_4_RATE_ID = 0xd,
ARFR_5_RATE_ID = 0xe
} PHYDM_RA_ARFR_NUM_E;
typedef enum _Phydm_ra_dbg_para {
RADBG_RTY_PENALTY = 1, //u8
RADBG_N_HIGH = 2,
RADBG_N_LOW = 3,
RADBG_TRATE_UP_TABLE = 4,
RADBG_TRATE_DOWN_TABLE = 5,
RADBG_TRYING_NECESSARY = 6,
RADBG_TDROPING_NECESSARY = 7,
RADBG_RATE_UP_RTY_RATIO = 8, //u8
RADBG_RATE_DOWN_RTY_RATIO = 9, //u8
RADBG_DEBUG_MONITOR1 = 0xc,
RADBG_DEBUG_MONITOR2 = 0xd,
RADBG_DEBUG_MONITOR3 = 0xe,
RADBG_DEBUG_MONITOR4 = 0xf,
NUM_RA_PARA
} PHYDM_RA_DBG_PARA_E;
#if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA
typedef struct _ODM_RA_Info_ {
u1Byte RateID;
u4Byte RateMask;
u4Byte RAUseRate;
u1Byte RateSGI;
u1Byte RssiStaRA;
u1Byte PreRssiStaRA;
u1Byte SGIEnable;
u1Byte DecisionRate;
u1Byte PreRate;
u1Byte HighestRate;
u1Byte LowestRate;
u4Byte NscUp;
u4Byte NscDown;
u2Byte RTY[5];
u4Byte TOTAL;
u2Byte DROP;
u1Byte Active;
u2Byte RptTime;
u1Byte RAWaitingCounter;
u1Byte RAPendingCounter;
#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
u1Byte PTActive; // on or off
u1Byte PTTryState; // 0 trying state, 1 for decision state
u1Byte PTStage; // 0~6
u1Byte PTStopCount; //Stop PT counter
u1Byte PTPreRate; // if rate change do PT
u1Byte PTPreRssi; // if RSSI change 5% do PT
u1Byte PTModeSS; // decide whitch rate should do PT
u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
u1Byte PTSmoothFactor;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
u1Byte RateDownCounter;
u1Byte RateUpCounter;
u1Byte RateDirection;
u1Byte BoundingType;
u1Byte BoundingCounter;
u1Byte BoundingLearningTime;
u1Byte RateDownStartTime;
#endif
} ODM_RA_INFO_T, *PODM_RA_INFO_T;
#endif
typedef struct _Rate_Adaptive_Table_ {
u1Byte firstconnect;
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
BOOLEAN PT_collision_pre;
#endif
#if (defined(CONFIG_RA_DBG_CMD))
BOOLEAN is_ra_dbg_init;
u1Byte RTY_P[ODM_NUM_RATE_IDX];
u1Byte RTY_P_default[ODM_NUM_RATE_IDX];
BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX];
u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
BOOLEAN RA_Para_feedback_req;
u1Byte para_idx;
u1Byte rate_idx;
u1Byte value;
u2Byte value_16;
u1Byte rate_length;
#endif
u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
u1Byte retry_descend_num;
u1Byte retrylimit_low;
u1Byte retrylimit_high;
#endif
} RA_T, *pRA_T;
typedef struct _ODM_RATE_ADAPTIVE {
u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC
BOOLEAN bLowerRtsRate;
#endif
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
u1Byte RtsThres;
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
BOOLEAN bUseLdpc;
#else
u1Byte UltraLowRSSIThresh;
u4Byte LastRATR; // RATR Register Content
#endif
} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
VOID
ODM_C2HRaParaReportHandler(
IN PVOID pDM_VOID,
IN pu1Byte CmdBuf,
IN u1Byte CmdLen
);
VOID
odm_RA_ParaAdjust_Send_H2C(
IN PVOID pDM_VOID
);
VOID
odm_RA_debug(
IN PVOID pDM_VOID,
IN u4Byte *const dm_value
);
VOID
odm_RA_ParaAdjust_init(
IN PVOID pDM_VOID
);
VOID
odm_RA_ParaAdjust(
IN PVOID pDM_VOID
);
VOID
phydm_ra_dynamic_retry_count(
IN PVOID pDM_VOID
);
VOID
phydm_ra_dynamic_retry_limit(
IN PVOID pDM_VOID
);
VOID
phydm_ra_dynamic_rate_id_on_assoc(
IN PVOID pDM_VOID,
IN u1Byte wireless_mode,
IN u1Byte init_rate_id
);
VOID
phydm_print_rate(
IN PVOID pDM_VOID,
IN u1Byte rate,
IN u4Byte dbg_component
);
VOID
phydm_c2h_ra_report_handler(
IN PVOID pDM_VOID,
IN pu1Byte CmdBuf,
IN u1Byte CmdLen
);
VOID
phydm_ra_info_init(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorInit(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheck(
IN PVOID pDM_VOID
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
s4Byte
phydm_FindMinimumRSSI(
IN PDM_ODM_T pDM_Odm,
IN PADAPTER pAdapter,
IN OUT BOOLEAN *pbLink_temp
);
#endif
VOID
odm_RSSIMonitorCheckMP(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheckCE(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheckAP(
IN PVOID pDM_VOID
);
VOID
odm_RateAdaptiveMaskInit(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMask(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskMP(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskCE(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskAPADSL(
IN PVOID pDM_VOID
);
BOOLEAN
ODM_RAStateCheck(
IN PVOID pDM_VOID,
IN s4Byte RSSI,
IN BOOLEAN bForceUpdate,
OUT pu1Byte pRATRState
);
VOID
odm_RefreshBasicRateMask(
IN PVOID pDM_VOID
);
VOID
ODM_RAPostActionOnAssoc(
IN PVOID pDM_Odm
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
u1Byte
odm_Find_RTS_Rate(
IN PVOID pDM_VOID,
IN u1Byte Tx_Rate,
IN BOOLEAN bErpProtect
);
VOID
ODM_UpdateNoisyState(
IN PVOID pDM_VOID,
IN BOOLEAN bNoisyStateFromC2H
);
u4Byte
Set_RA_DM_Ratrbitmap_by_Noisy(
IN PVOID pDM_VOID,
IN WIRELESS_MODE WirelessMode,
IN u4Byte ratr_bitmap,
IN u1Byte rssi_level
);
VOID
ODM_UpdateInitRate(
IN PVOID pDM_VOID,
IN u1Byte Rate
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_RSSIDumpToRegister(
IN PVOID pDM_VOID
);
VOID
odm_RefreshLdpcRtsMP(
IN PADAPTER pAdapter,
IN PDM_ODM_T pDM_Odm,
IN u1Byte mMacId,
IN u1Byte IOTPeer,
IN s4Byte UndecoratedSmoothedPWDB
);
VOID
ODM_DynamicARFBSelect(
IN PVOID pDM_VOID,
IN u1Byte rate,
IN BOOLEAN Collision_State
);
VOID
ODM_RateAdaptiveStateApInit(
IN PVOID PADAPTER_VOID,
IN PRT_WLAN_STA pEntry
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
static void
FindMinimumRSSI(
IN PADAPTER pAdapter
);
u8Byte
PhyDM_Get_Rate_Bitmap_Ex(
IN PVOID pDM_VOID,
IN u4Byte macid,
IN u8Byte ra_mask,
IN u1Byte rssi_level,
OUT u8Byte *dm_RA_Mask,
OUT u1Byte *dm_RteID
);
u4Byte
ODM_Get_Rate_Bitmap(
IN PVOID pDM_VOID,
IN u4Byte macid,
IN u4Byte ra_mask,
IN u1Byte rssi_level
);
#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/
#endif /*#ifndef __ODMRAINFO_H__*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_RegDefine11AC.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
//2 RF REG LIST
//2 BB REG LIST
//PAGE 8
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
#define ODM_REG_BB_RX_PATH_11AC 0x808
#define ODM_REG_BB_TX_PATH_11AC 0x80c
#define ODM_REG_BB_ATC_11AC 0x860
#define ODM_REG_EDCCA_POWER_CAL 0x8dc
#define ODM_REG_DBG_RPT_11AC 0x8fc
//PAGE 9
#define ODM_REG_EDCCA_DOWN_OPT 0x900
#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
#define ODM_REG_NHM_TIMER_11AC 0x990
#define ODM_REG_CLM_TIME_PERIOD_11AC 0x990
#define ODM_REG_NHM_TH9_TH10_11AC 0x994
#define ODM_REG_CLM_11AC 0x994
#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
#define ODM_REG_NHM_TH8_11AC 0x9a0
#define ODM_REG_NHM_9E8_11AC 0x9e8
#define ODM_REG_CSI_CONTENT_VALUE 0x9b4
//PAGE A
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
//PAGE B
#define ODM_REG_RST_RPT_11AC 0xB58
//PAGE C
#define ODM_REG_TRMUX_11AC 0xC08
#define ODM_REG_IGI_A_11AC 0xC50
//PAGE E
#define ODM_REG_IGI_B_11AC 0xE50
#define ODM_REG_TRMUX_11AC_B 0xE08
//PAGE F
#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
#define ODM_REG_OFDM_FA_11AC 0xF48
#define ODM_REG_RPT_11AC 0xfa0
#define ODM_REG_CLM_RESULT_11AC 0xfa4
#define ODM_REG_NHM_CNT_11AC 0xfa8
#define ODM_REG_NHM_DUR_READY_11AC 0xfb4
#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac
#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0
#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0
//PAGE 18
#define ODM_REG_IGI_C_11AC 0x1850
//PAGE 1A
#define ODM_REG_IGI_D_11AC 0x1A50
//2 MAC REG LIST
#define ODM_REG_RESP_TX_11AC 0x6D8
//DIG Related
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16
#define ODM_BIT_BB_RX_PATH_11AC 0xF
#define ODM_BIT_BB_TX_PATH_11AC 0xF
#define ODM_BIT_BB_ATC_11AC BIT14
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_RegDefine11N.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
//2 RF REG LIST
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
//2 BB REG LIST
//PAGE 8
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
#define ODM_REG_RX_DEFUALT_A_11N 0x858
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_NHM_TIMER_11N 0x894
#define ODM_REG_CLM_TIME_PERIOD_11N 0x894
#define ODM_REG_NHM_TH9_TH10_11N 0x890
#define ODM_REG_CLM_11N 0x890
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
#define ODM_REG_NHM_TH8_11N 0xe28
#define ODM_REG_CLM_READY_11N 0x8b4
#define ODM_REG_CLM_RESULT_11N 0x8d0
#define ODM_REG_NHM_CNT_11N 0x8d8
// For ACS, Jeffery, 2014-12-26
#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc
#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0
#define ODM_REG_NHM_CNT10_11N 0x8d4
//PAGE 9
#define ODM_REG_DBG_RPT_11N 0x908
#define ODM_REG_BB_TX_PATH_11N 0x90c
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
//PAGE A
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
//PAGE B
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
//PAGE C
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_BB_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
//PAGE D
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_BB_ATC_11N 0xD2C
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
#define ODM_REG_RPT_11N 0xDF4
//PAGE E
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define ODM_REG_EDCCA_DCNF_11N 0xE24
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
#define ODM_REG_IGI_C_11N 0xF84
#define ODM_REG_IGI_D_11N 0xF88
//2 MAC REG LIST
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
//DIG Related
#define ODM_BIT_IGI_11N 0x0000007F
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
#define ODM_BIT_BB_RX_PATH_11N 0xF
#define ODM_BIT_BB_TX_PATH_11N 0xF
#define ODM_BIT_BB_ATC_11N BIT11
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_debug.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_debug.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
#define DEBUG_VERSION "1.1" /*2015.07.29 YuChen*/
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE()!
//
#define ODM_DBG_OFF 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define ODM_DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define ODM_DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define ODM_DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define ODM_DBG_TRACE 5
/*FW DBG MSG*/
#define RATE_DECISION BIT0
#define INIT_RA_TABLE BIT1
#define RATE_UP BIT2
#define RATE_DOWN BIT3
#define TRY_DONE BIT4
#define F_RATE_AP_RPT BIT7
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
//BB Functions
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_MP BIT14
#define ODM_COMP_CFO_TRACKING BIT15
#define ODM_COMP_ACS BIT16
#define PHYDM_COMP_ADAPTIVITY BIT17
#define PHYDM_COMP_RA_DBG BIT18
#define PHYDM_COMP_TXBF BIT19
//MAC Functions
#define ODM_COMP_EDCA_TURBO BIT20
#define ODM_COMP_EARLY_MODE BIT21
#define ODM_FW_DEBUG_TRACE BIT22
//RF Functions
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
//Common Functions
#define ODM_PHY_CONFIG BIT28
#define BEAMFORMING_DEBUG BIT29
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
#define ODM_COMP_NOISY_DETECT BIT32
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define RT_PRINTK DbgPrint
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define DbgPrint printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#define RT_DISP(dbgtype, dbgflag, printstr)
#else
#define DbgPrint panic_printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#if DBG
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
do { \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \
{ \
if (pDM_Odm->SupportICType == ODM_RTL8188E) \
DbgPrint("[ODM-8188E] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8192E) \
DbgPrint("[ODM-8192E] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8812) \
DbgPrint("[ODM-8812] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8821) \
DbgPrint("[ODM-8821] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8814A) \
DbgPrint("[ODM-8814] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8703B) \
DbgPrint("[ODM-8703B] "); \
else if(pDM_Odm->SupportICType == ODM_RTL8822B) \
DbgPrint("[ODM-8822] "); \
else if (pDM_Odm->SupportICType == ODM_RTL8188F) \
DbgPrint("[ODM-8188F] "); \
RT_PRINTK fmt; \
} \
} while (0)
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if(!(expr)) { \
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
RT_PRINTK fmt; \
ASSERT(FALSE); \
}
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); }
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); }
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \
{ \
int __i; \
pu1Byte __ptr = (pu1Byte)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#else
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
#define ODM_dbg_enter()
#define ODM_dbg_exit()
#define ODM_dbg_trace(str)
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
VOID
PHYDM_InitDebugSetting(IN PDM_ODM_T pDM_Odm);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID phydm_BB_RxHang_Info(IN PDM_ODM_T pDM_Odm);
#endif
#define BB_TMP_BUF_SIZE 100
VOID phydm_BB_Debug_Info(IN PDM_ODM_T pDM_Odm);
VOID phydm_BasicDbgMessage( IN PVOID pDM_VOID);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define PHYDM_DBGPRINT 0
#define PHYDM_SSCANF(x, y, z) DCMD_Scanf(x, y, z)
#if (PHYDM_DBGPRINT == 1)
#define PHYDM_SNPRINTF(msg) \
do {\
rsprintf msg;\
DbgPrint(output);\
} while (0)
#else
#define PHYDM_SNPRINTF(msg) \
do {\
rsprintf msg;\
DCMD_Printf(output);\
} while (0)
#endif
#else
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define PHYDM_DBGPRINT 0
#else
#define PHYDM_DBGPRINT 1
#endif
#define MAX_ARGC 20
#define MAX_ARGV 16
#define DCMD_DECIMAL "%d"
#define DCMD_CHAR "%c"
#define DCMD_HEX "%x"
#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z)
#if (PHYDM_DBGPRINT == 1)
#define PHYDM_SNPRINTF(msg)\
do {\
snprintf msg;\
DbgPrint(output);\
} while (0)
#else
#define PHYDM_SNPRINTF(msg)\
do {\
if(out_len > used)\
used+=snprintf msg;\
} while (0)
#endif
#endif
VOID phydm_BasicProfile(
IN PVOID pDM_VOID,
IN u4Byte *_used,
OUT char *output,
IN u4Byte *_out_len
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))
s4Byte
phydm_cmd(
IN PDM_ODM_T pDM_Odm,
IN char *input,
IN u4Byte in_len,
IN u1Byte flag,
OUT char *output,
IN u4Byte out_len
);
#endif
VOID
phydm_cmd_parser(
IN PDM_ODM_T pDM_Odm,
IN char input[][16],
IN u4Byte input_num,
IN u1Byte flag,
OUT char *output,
IN u4Byte out_len
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void phydm_sbd_check(
IN PDM_ODM_T pDM_Odm
);
void phydm_sbd_callback(
PRT_TIMER pTimer
);
void phydm_sbd_workitem_callback(
IN PVOID pContext
);
#endif
VOID
phydm_fw_trace_en_h2c(
IN PVOID pDM_VOID,
IN BOOLEAN enable,
IN u4Byte monitor_mode,
IN u4Byte macid
);
VOID
phydm_fw_trace_handler(
IN PVOID pDM_VOID,
IN pu1Byte CmdBuf,
IN u1Byte CmdLen
);
VOID
phydm_fw_trace_handler_code(
IN PVOID pDM_VOID,
IN pu1Byte Buffer,
IN u1Byte CmdLen
);
VOID
phydm_fw_trace_handler_8051(
IN PVOID pDM_VOID,
IN pu1Byte CmdBuf,
IN u1Byte CmdLen
);
#endif // __ODM_DBG_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_interface.c
Executable
+1021
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_interface.h
Executable
+438
View File
@@ -0,0 +1,438 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/
//
// =========== Constant/Structure/Enum/... Define
//
//
// =========== Macro Define
//
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
// _cat: implemented by Token-Pasting Operator.
#if 0
#define _cat(_name, _ic_type, _func) \
( \
_func##_all(_name) \
)
#endif
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pDM_Odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#ifdef __ECOS
#define _rtk_cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#else
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#endif
/*
// only sample code
//#define _cat(_name, _ic_type, _func) \
// ( \
// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \
// _func##_ic(_name, _8195) \
// )
*/
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
#ifdef __ECOS
#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit)
#else
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
#endif
typedef enum _PHYDM_H2C_CMD {
ODM_H2C_RSSI_REPORT = 0,
ODM_H2C_PSD_RESULT = 1,
ODM_H2C_PathDiv = 2,
ODM_H2C_WIFI_CALIBRATION = 3,
ODM_H2C_IQ_CALIBRATION = 4,
ODM_H2C_RA_PARA_ADJUST = 5,
PHYDM_H2C_DYNAMIC_TX_PATH = 6,
PHYDM_H2C_FW_TRACE_EN = 7,
PHYDM_H2C_TXBF = 8,
ODM_MAX_H2CCMD
}PHYDM_H2C_CMD;
typedef enum _PHYDM_C2H_EVT {
PHYDM_C2H_DBG = 0,
PHYDM_C2H_LB = 1,
PHYDM_C2H_XBF = 2,
PHYDM_C2H_TX_REPORT = 3,
PHYDM_C2H_INFO = 9,
PHYDM_C2H_BT_MP = 11,
PHYDM_C2H_RA_RPT = 12,
PHYDM_C2H_RA_PARA_RPT=14,
PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15,
PHYDM_C2H_IQK_FINISH = 17, /*0x11*/
PHYDM_C2H_DBG_CODE = 0xFE,
PHYDM_C2H_EXTEND = 0xFF,
}PHYDM_C2H_EVT;
typedef enum _PHYDM_EXTEND_C2H_EVT {
PHYDM_EXTEND_C2H_DBG_PRINT = 0
}PHYDM_EXTEND_C2H_EVT;
typedef enum _PHYDM_ACTING_TYPE {
PhyDM_ACTING_AS_IBSS = 0,
PhyDM_ACTING_AS_AP = 1
} PHYDM_ACTING_TYPE;
//
// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
// Suggest HW team to use thread instead of workitem. Windows also support the feature.
//
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
#if 0
typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
typedef struct _RT_WORK_ITEM
{
RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
PVOID Adapter; // Pointer to Adapter object.
PVOID pContext; // Parameter to passed to CallBackFunc().
RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem.
u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled.
PVOID pPlatformExt; // Pointer to platform-dependent extension.
BOOLEAN bFree;
char szID[36]; // An identity string of this workitem.
}RT_WORK_ITEM, *PRT_WORK_ITEM;
#endif
#endif
//
// =========== Extern Variable ??? It should be forbidden.
//
//
// =========== EXtern Function Prototype
//
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
);
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
);
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
);
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
//
// Memory Relative Function.
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
);
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
);
VOID
ODM_MoveMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pDest,
IN PVOID pSrc,
IN u4Byte Length
);
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
);
void ODM_Memory_Set
(IN PDM_ODM_T pDM_Odm,
IN PVOID pbuf,
IN s1Byte value,
IN u4Byte length);
//
// ODM MISC-spin lock relative API.
//
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
//
// ODM MISC-workitem relative API.
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
);
//
// ODM Timer relative API.
//
VOID
ODM_StallExecution(
IN u4Byte usDelay
);
VOID
ODM_delay_ms(IN u4Byte ms);
VOID
ODM_delay_us(IN u4Byte us);
VOID
ODM_sleep_ms(IN u4Byte ms);
VOID
ODM_sleep_us(IN u4Byte us);
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
);
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
BOOLEAN
phydm_actingDetermine(
IN PDM_ODM_T pDM_Odm,
IN PHYDM_ACTING_TYPE type
);
//
// ODM FW relative API.
//
VOID
ODM_FillH2CCmd(
IN PDM_ODM_T pDM_Odm,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
);
u1Byte
phydm_c2H_content_parsing(
IN PVOID pDM_VOID,
IN u1Byte c2hCmdId,
IN u1Byte c2hCmdLen,
IN pu1Byte tmpBuf
);
u8Byte
ODM_GetCurrentTime(
IN PDM_ODM_T pDM_Odm
);
u8Byte
ODM_GetProgressingTime(
IN PDM_ODM_T pDM_Odm,
IN u8Byte Start_Time
);
#endif // __ODM_INTERFACE_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_kfree.c
Executable
+191
View File
@@ -0,0 +1,191 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*============================================================*/
/*include files*/
/*============================================================*/
#include "mp_precomp.h"
#include "phydm_precomp.h"
/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/
/*This is a phydm API*/
VOID
phydm_SetKfreeToRF_8814A(
IN PVOID pDM_VOID,
IN u1Byte eRFPath,
IN u1Byte Data
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
BOOLEAN bOdd;
if ((Data%2) != 0) { /*odd -> positive*/
Data = Data - 1;
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 1);
bOdd = TRUE;
} else { /*even -> negative*/
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT19, 0);
bOdd = FALSE;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", bOdd));
switch (Data) {
case 0:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 0;
break;
case 2:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 0);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 0;
break;
case 4:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 1;
break;
case 6:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 1);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 1;
break;
case 8:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 2;
break;
case 10:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 2);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 2;
break;
case 12:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 3;
break;
case 14:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 3);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 3;
break;
case 16:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 4;
break;
case 18:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 1);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 4);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 4;
break;
case 20:
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT14, 0);
ODM_SetRFReg(pDM_Odm, eRFPath, rRF_TxGainOffset, BIT17|BIT16|BIT15, 5);
pRFCalibrateInfo->KfreeOffset[eRFPath] = 5;
break;
default:
break;
}
if (bOdd == FALSE) {
/*that means Kfree offset is negative, we need to record it.*/
pRFCalibrateInfo->KfreeOffset[eRFPath] = (-1)*pRFCalibrateInfo->KfreeOffset[eRFPath];
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath]));
} else
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): KfreeOffset = %d\n", pRFCalibrateInfo->KfreeOffset[eRFPath]));
}
VOID
phydm_SetKfreeToRF(
IN PVOID pDM_VOID,
IN u1Byte eRFPath,
IN u1Byte Data
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
if (pDM_Odm->SupportICType & ODM_RTL8814A)
phydm_SetKfreeToRF_8814A(pDM_Odm, eRFPath, Data);
}
VOID
phydm_ConfigKFree(
IN PVOID pDM_VOID,
IN u1Byte channelToSW,
IN pu1Byte kfreeTable
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
u1Byte rfpath = 0, maxRFpath = 0;
u1Byte channelIdx = 0;
if (pDM_Odm->SupportICType & ODM_RTL8814A)
maxRFpath = 4; /*0~3*/
else if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B))
maxRFpath = 2; /*0~1*/
else
maxRFpath = 1;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>phy_ConfigKFree8814A()\n"));
if (pRFCalibrateInfo->RegRfKFreeEnable == 2) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == 2, Disable\n"));
return;
} else if (pRFCalibrateInfo->RegRfKFreeEnable == 1 || pRFCalibrateInfo->RegRfKFreeEnable == 0) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RegRfKFreeEnable == TRUE\n"));
/*Make sure the targetval is defined*/
if (((pRFCalibrateInfo->RegRfKFreeEnable == 1) && (kfreeTable[0] != 0xFF)) || (pRFCalibrateInfo->RfKFreeEnable == TRUE)) {
/*if kfreeTable[0] == 0xff, means no Kfree*/
if (*pDM_Odm->pBandType == ODM_BAND_2_4G) {
if (channelToSW <= 14 && channelToSW >= 1)
channelIdx = PHYDM_2G;
} else if (*pDM_Odm->pBandType == ODM_BAND_5G) {
if (channelToSW >= 36 && channelToSW <= 48)
channelIdx = PHYDM_5GLB1;
if (channelToSW >= 52 && channelToSW <= 64)
channelIdx = PHYDM_5GLB2;
if (channelToSW >= 100 && channelToSW <= 120)
channelIdx = PHYDM_5GMB1;
if (channelToSW >= 124 && channelToSW <= 144)
channelIdx = PHYDM_5GMB2;
if (channelToSW >= 149 && channelToSW <= 177)
channelIdx = PHYDM_5GHB;
}
for (rfpath = ODM_RF_PATH_A; rfpath < maxRFpath; rfpath++) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phydm_kfree(): PATH_%d: %#x\n", rfpath, kfreeTable[channelIdx*maxRFpath + rfpath]));
phydm_SetKfreeToRF(pDM_Odm, rfpath, kfreeTable[channelIdx*maxRFpath + rfpath]);
}
} else {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): targetval not defined, Don't execute KFree Process.\n"));
return;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===phy_ConfigKFree8814A()\n"));
}
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_kfree.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMKFREE_H__
#define __PHYDKFREE_H__
#define KFREE_VERSION "1.0"
typedef enum tag_phydm_kfree_channeltosw {
PHYDM_2G = 0,
PHYDM_5GLB1 = 1,
PHYDM_5GLB2 = 2,
PHYDM_5GMB1 = 3,
PHYDM_5GMB2 = 4,
PHYDM_5GHB = 5,
} PHYDM_KFREE_CHANNELTOSW;
VOID
phydm_ConfigKFree(
IN PVOID pDM_VOID,
IN u1Byte channelToSW,
IN pu1Byte kfreeTable
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_pre_define.h
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+610
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMPREDEFINE_H__
#define __PHYDMPREDEFINE_H__
//1 ============================================================
//1 Definition
//1 ============================================================
//Max path of IC
#define MAX_PATH_NUM_8188E 1
#define MAX_PATH_NUM_8192E 2
#define MAX_PATH_NUM_8723B 1
#define MAX_PATH_NUM_8812A 2
#define MAX_PATH_NUM_8821A 1
#define MAX_PATH_NUM_8814A 4
#define MAX_PATH_NUM_8822B 2
#define MAX_PATH_NUM_8821B 2
#define MAX_PATH_NUM_8703B 1
#define MAX_PATH_NUM_8188F 1
//Max RF path
#define ODM_RF_PATH_MAX 2
#define ODM_RF_PATH_MAX_JAGUAR 4
//number of entry
#if(DM_ODM_SUPPORT_TYPE & (ODM_CE))
#define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/
#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
#define ASSOCIATE_ENTRY_NUM NUM_STAT
#define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1)
#else
#define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1)
#endif
/* -----MGN rate--------------------------------- */
#define ODM_MGN_1M 0x02
#define ODM_MGN_2M 0x04
#define ODM_MGN_5_5M 0x0b
#define ODM_MGN_11M 0x16
#define ODM_MGN_6M 0x0c
#define ODM_MGN_9M 0x12
#define ODM_MGN_12M 0x18
#define ODM_MGN_18M 0x24
#define ODM_MGN_24M 0x30
#define ODM_MGN_36M 0x48
#define ODM_MGN_48M 0x60
#define ODM_MGN_54M 0x6c
/*TxHT = 1*/
#define ODM_MGN_MCS0 0x80
#define ODM_MGN_MCS1 0x81
#define ODM_MGN_MCS2 0x82
#define ODM_MGN_MCS3 0x83
#define ODM_MGN_MCS4 0x84
#define ODM_MGN_MCS5 0x85
#define ODM_MGN_MCS6 0x86
#define ODM_MGN_MCS7 0x87
#define ODM_MGN_MCS8 0x88
#define ODM_MGN_MCS9 0x89
#define ODM_MGN_MCS10 0x8a
#define ODM_MGN_MCS11 0x8b
#define ODM_MGN_MCS12 0x8c
#define ODM_MGN_MCS13 0x8d
#define ODM_MGN_MCS14 0x8e
#define ODM_MGN_MCS15 0x8f
#define ODM_MGN_VHT1SS_MCS0 0x90
#define ODM_MGN_VHT1SS_MCS1 0x91
#define ODM_MGN_VHT1SS_MCS2 0x92
#define ODM_MGN_VHT1SS_MCS3 0x93
#define ODM_MGN_VHT1SS_MCS4 0x94
#define ODM_MGN_VHT1SS_MCS5 0x95
#define ODM_MGN_VHT1SS_MCS6 0x96
#define ODM_MGN_VHT1SS_MCS7 0x97
#define ODM_MGN_VHT1SS_MCS8 0x98
#define ODM_MGN_VHT1SS_MCS9 0x99
#define ODM_MGN_VHT2SS_MCS0 0x9a
#define ODM_MGN_VHT2SS_MCS1 0x9b
#define ODM_MGN_VHT2SS_MCS2 0x9c
#define ODM_MGN_VHT2SS_MCS3 0x9d
#define ODM_MGN_VHT2SS_MCS4 0x9e
#define ODM_MGN_VHT2SS_MCS5 0x9f
#define ODM_MGN_VHT2SS_MCS6 0xa0
#define ODM_MGN_VHT2SS_MCS7 0xa1
#define ODM_MGN_VHT2SS_MCS8 0xa2
#define ODM_MGN_VHT2SS_MCS9 0xa3
#define ODM_MGN_MCS0_SG 0xc0
#define ODM_MGN_MCS1_SG 0xc1
#define ODM_MGN_MCS2_SG 0xc2
#define ODM_MGN_MCS3_SG 0xc3
#define ODM_MGN_MCS4_SG 0xc4
#define ODM_MGN_MCS5_SG 0xc5
#define ODM_MGN_MCS6_SG 0xc6
#define ODM_MGN_MCS7_SG 0xc7
#define ODM_MGN_MCS8_SG 0xc8
#define ODM_MGN_MCS9_SG 0xc9
#define ODM_MGN_MCS10_SG 0xca
#define ODM_MGN_MCS11_SG 0xcb
#define ODM_MGN_MCS12_SG 0xcc
#define ODM_MGN_MCS13_SG 0xcd
#define ODM_MGN_MCS14_SG 0xce
#define ODM_MGN_MCS15_SG 0xcf
/* -----DESC rate--------------------------------- */
#define ODM_RATEMCS15_SG 0x1c
#define ODM_RATEMCS32 0x20
// CCK Rates, TxHT = 0
#define ODM_RATE1M 0x00
#define ODM_RATE2M 0x01
#define ODM_RATE5_5M 0x02
#define ODM_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define ODM_RATE6M 0x04
#define ODM_RATE9M 0x05
#define ODM_RATE12M 0x06
#define ODM_RATE18M 0x07
#define ODM_RATE24M 0x08
#define ODM_RATE36M 0x09
#define ODM_RATE48M 0x0A
#define ODM_RATE54M 0x0B
// MCS Rates, TxHT = 1
#define ODM_RATEMCS0 0x0C
#define ODM_RATEMCS1 0x0D
#define ODM_RATEMCS2 0x0E
#define ODM_RATEMCS3 0x0F
#define ODM_RATEMCS4 0x10
#define ODM_RATEMCS5 0x11
#define ODM_RATEMCS6 0x12
#define ODM_RATEMCS7 0x13
#define ODM_RATEMCS8 0x14
#define ODM_RATEMCS9 0x15
#define ODM_RATEMCS10 0x16
#define ODM_RATEMCS11 0x17
#define ODM_RATEMCS12 0x18
#define ODM_RATEMCS13 0x19
#define ODM_RATEMCS14 0x1A
#define ODM_RATEMCS15 0x1B
#define ODM_RATEMCS16 0x1C
#define ODM_RATEMCS17 0x1D
#define ODM_RATEMCS18 0x1E
#define ODM_RATEMCS19 0x1F
#define ODM_RATEMCS20 0x20
#define ODM_RATEMCS21 0x21
#define ODM_RATEMCS22 0x22
#define ODM_RATEMCS23 0x23
#define ODM_RATEMCS24 0x24
#define ODM_RATEMCS25 0x25
#define ODM_RATEMCS26 0x26
#define ODM_RATEMCS27 0x27
#define ODM_RATEMCS28 0x28
#define ODM_RATEMCS29 0x29
#define ODM_RATEMCS30 0x2A
#define ODM_RATEMCS31 0x2B
#define ODM_RATEVHTSS1MCS0 0x2C
#define ODM_RATEVHTSS1MCS1 0x2D
#define ODM_RATEVHTSS1MCS2 0x2E
#define ODM_RATEVHTSS1MCS3 0x2F
#define ODM_RATEVHTSS1MCS4 0x30
#define ODM_RATEVHTSS1MCS5 0x31
#define ODM_RATEVHTSS1MCS6 0x32
#define ODM_RATEVHTSS1MCS7 0x33
#define ODM_RATEVHTSS1MCS8 0x34
#define ODM_RATEVHTSS1MCS9 0x35
#define ODM_RATEVHTSS2MCS0 0x36
#define ODM_RATEVHTSS2MCS1 0x37
#define ODM_RATEVHTSS2MCS2 0x38
#define ODM_RATEVHTSS2MCS3 0x39
#define ODM_RATEVHTSS2MCS4 0x3A
#define ODM_RATEVHTSS2MCS5 0x3B
#define ODM_RATEVHTSS2MCS6 0x3C
#define ODM_RATEVHTSS2MCS7 0x3D
#define ODM_RATEVHTSS2MCS8 0x3E
#define ODM_RATEVHTSS2MCS9 0x3F
#define ODM_RATEVHTSS3MCS0 0x40
#define ODM_RATEVHTSS3MCS1 0x41
#define ODM_RATEVHTSS3MCS2 0x42
#define ODM_RATEVHTSS3MCS3 0x43
#define ODM_RATEVHTSS3MCS4 0x44
#define ODM_RATEVHTSS3MCS5 0x45
#define ODM_RATEVHTSS3MCS6 0x46
#define ODM_RATEVHTSS3MCS7 0x47
#define ODM_RATEVHTSS3MCS8 0x48
#define ODM_RATEVHTSS3MCS9 0x49
#define ODM_RATEVHTSS4MCS0 0x4A
#define ODM_RATEVHTSS4MCS1 0x4B
#define ODM_RATEVHTSS4MCS2 0x4C
#define ODM_RATEVHTSS4MCS3 0x4D
#define ODM_RATEVHTSS4MCS4 0x4E
#define ODM_RATEVHTSS4MCS5 0x4F
#define ODM_RATEVHTSS4MCS6 0x50
#define ODM_RATEVHTSS4MCS7 0x51
#define ODM_RATEVHTSS4MCS8 0x52
#define ODM_RATEVHTSS4MCS9 0x53
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
#else
#if (RTL8192E_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1)
#elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1)
#elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1)
#elif (RTL8812A_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1)
#elif(RTL8814A_SUPPORT == 1)
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1)
#else
#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1)
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define CONFIG_SFW_SUPPORTED
#endif
//1 ============================================================
//1 enumeration
//1 ============================================================
// ODM_CMNINFO_INTERFACE
typedef enum tag_ODM_Support_Interface_Definition
{
ODM_ITRF_PCIE = 0x1,
ODM_ITRF_USB = 0x2,
ODM_ITRF_SDIO = 0x4,
ODM_ITRF_ALL = 0x7,
}ODM_INTERFACE_E;
// ODM_CMNINFO_IC_TYPE
typedef enum tag_ODM_Support_IC_Type_Definition
{
ODM_RTL8188E = BIT0,
ODM_RTL8812 = BIT1,
ODM_RTL8821 = BIT2,
ODM_RTL8192E = BIT3,
ODM_RTL8723B = BIT4,
ODM_RTL8814A = BIT5,
ODM_RTL8881A = BIT6,
ODM_RTL8821B = BIT7,
ODM_RTL8822B = BIT8,
ODM_RTL8703B = BIT9,
ODM_RTL8195A = BIT10,
ODM_RTL8188F = BIT11
}ODM_IC_TYPE_E;
#define ODM_IC_11N_SERIES (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F)
#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B)
#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B)
#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A|ODM_RTL8703B|ODM_RTL8188F)
#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A|ODM_RTL8822B)
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifdef RTK_AC_SUPPORT
#define ODM_IC_11AC_SERIES_SUPPORT 1
#else
#define ODM_IC_11AC_SERIES_SUPPORT 0
#endif
#define ODM_IC_11N_SERIES_SUPPORT 1
#define ODM_CONFIG_BT_COEXIST 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define ODM_IC_11AC_SERIES_SUPPORT 1
#define ODM_IC_11N_SERIES_SUPPORT 1
#define ODM_CONFIG_BT_COEXIST 1
#else
#if ((RTL8188E_SUPPORT == 1) || \
(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \
(RTL8188F_SUPPORT == 1))
#define ODM_IC_11N_SERIES_SUPPORT 1
#define ODM_IC_11AC_SERIES_SUPPORT 0
#else
#define ODM_IC_11N_SERIES_SUPPORT 0
#define ODM_IC_11AC_SERIES_SUPPORT 1
#endif
#ifdef CONFIG_BT_COEXIST
#define ODM_CONFIG_BT_COEXIST 1
#else
#define ODM_CONFIG_BT_COEXIST 0
#endif
#endif
//ODM_CMNINFO_CUT_VER
typedef enum tag_ODM_Cut_Version_Definition
{
ODM_CUT_A = 0,
ODM_CUT_B = 1,
ODM_CUT_C = 2,
ODM_CUT_D = 3,
ODM_CUT_E = 4,
ODM_CUT_F = 5,
ODM_CUT_I = 8,
ODM_CUT_J = 9,
ODM_CUT_K = 10,
ODM_CUT_TEST = 15,
}ODM_CUT_VERSION_E;
// ODM_CMNINFO_FAB_VER
typedef enum tag_ODM_Fab_Version_Definition
{
ODM_TSMC = 0,
ODM_UMC = 1,
}ODM_FAB_E;
// ODM_CMNINFO_RF_TYPE
//
// For example 1T2R (A+AB = BIT0|BIT4|BIT5)
//
typedef enum tag_ODM_RF_Path_Bit_Definition
{
ODM_RF_A = BIT0,
ODM_RF_B = BIT1,
ODM_RF_C = BIT2,
ODM_RF_D = BIT3,
}ODM_RF_PATH_E;
typedef enum tag_PHYDM_RF_TX_NUM {
ODM_1T = 1,
ODM_2T = 2,
ODM_3T = 3,
ODM_4T = 4,
} ODM_RF_TX_NUM_E;
typedef enum tag_ODM_RF_Type_Definition {
ODM_1T1R,
ODM_1T2R,
ODM_2T2R,
ODM_2T2R_GREEN,
ODM_2T3R,
ODM_2T4R,
ODM_3T3R,
ODM_3T4R,
ODM_4T4R,
ODM_XTXR
}ODM_RF_TYPE_E;
typedef enum tag_ODM_MAC_PHY_Mode_Definition
{
ODM_SMSP = 0,
ODM_DMSP = 1,
ODM_DMDP = 2,
}ODM_MAC_PHY_MODE_E;
typedef enum tag_BT_Coexist_Definition
{
ODM_BT_BUSY = 1,
ODM_BT_ON = 2,
ODM_BT_OFF = 3,
ODM_BT_NONE = 4,
}ODM_BT_COEXIST_E;
// ODM_CMNINFO_OP_MODE
typedef enum tag_Operation_Mode_Definition
{
ODM_NO_LINK = BIT0,
ODM_LINK = BIT1,
ODM_SCAN = BIT2,
ODM_POWERSAVE = BIT3,
ODM_AP_MODE = BIT4,
ODM_CLIENT_MODE = BIT5,
ODM_AD_HOC = BIT6,
ODM_WIFI_DIRECT = BIT7,
ODM_WIFI_DISPLAY = BIT8,
}ODM_OPERATION_MODE_E;
// ODM_CMNINFO_WM_MODE
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
typedef enum tag_Wireless_Mode_Definition
{
ODM_WM_UNKNOW = 0x0,
ODM_WM_B = BIT0,
ODM_WM_G = BIT1,
ODM_WM_A = BIT2,
ODM_WM_N24G = BIT3,
ODM_WM_N5G = BIT4,
ODM_WM_AUTO = BIT5,
ODM_WM_AC = BIT6,
}ODM_WIRELESS_MODE_E;
#else
typedef enum tag_Wireless_Mode_Definition
{
ODM_WM_UNKNOWN = 0x00,/*0x0*/
ODM_WM_A = BIT0, /* 0x1*/
ODM_WM_B = BIT1, /* 0x2*/
ODM_WM_G = BIT2,/* 0x4*/
ODM_WM_AUTO = BIT3,/* 0x8*/
ODM_WM_N24G = BIT4,/* 0x10*/
ODM_WM_N5G = BIT5,/* 0x20*/
ODM_WM_AC_5G = BIT6,/* 0x40*/
ODM_WM_AC_24G = BIT7,/* 0x80*/
ODM_WM_AC_ONLY = BIT8,/* 0x100*/
ODM_WM_MAX = BIT11/* 0x800*/
}ODM_WIRELESS_MODE_E;
#endif
// ODM_CMNINFO_BAND
typedef enum tag_Band_Type_Definition
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
ODM_BAND_2_4G = BIT0,
ODM_BAND_5G = BIT1,
#else
ODM_BAND_2_4G = 0,
ODM_BAND_5G,
ODM_BAND_ON_BOTH,
ODM_BANDMAX
#endif
}ODM_BAND_TYPE_E;
// ODM_CMNINFO_SEC_CHNL_OFFSET
typedef enum tag_Secondary_Channel_Offset_Definition
{
ODM_DONT_CARE = 0,
ODM_BELOW = 1,
ODM_ABOVE = 2
}ODM_SEC_CHNL_OFFSET_E;
// ODM_CMNINFO_SEC_MODE
typedef enum tag_Security_Definition
{
ODM_SEC_OPEN = 0,
ODM_SEC_WEP40 = 1,
ODM_SEC_TKIP = 2,
ODM_SEC_RESERVE = 3,
ODM_SEC_AESCCMP = 4,
ODM_SEC_WEP104 = 5,
ODM_WEP_WPA_MIXED = 6, // WEP + WPA
ODM_SEC_SMS4 = 7,
}ODM_SECURITY_E;
// ODM_CMNINFO_BW
typedef enum tag_Bandwidth_Definition
{
ODM_BW20M = 0,
ODM_BW40M = 1,
ODM_BW80M = 2,
ODM_BW160M = 3,
ODM_BW5M = 4,
ODM_BW10M = 5,
ODM_BW_MAX = 6
}ODM_BW_E;
// ODM_CMNINFO_CHNL
// ODM_CMNINFO_BOARD_TYPE
typedef enum tag_Board_Definition
{
ODM_BOARD_DEFAULT = 0, // The DEFAULT case.
ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card.
ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card
ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT
ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA
ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA
ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW
ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA
ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA
}ODM_BOARD_TYPE_E;
typedef enum tag_ODM_Package_Definition
{
ODM_PACKAGE_DEFAULT = 0,
ODM_PACKAGE_QFN68 = BIT(0),
ODM_PACKAGE_TFBGA90 = BIT(1),
ODM_PACKAGE_TFBGA79 = BIT(2),
}ODM_Package_TYPE_E;
typedef enum tag_ODM_TYPE_GPA_Definition {
TYPE_GPA0 = 0x0000,
TYPE_GPA1 = 0x0055,
TYPE_GPA2 = 0x00AA,
TYPE_GPA3 = 0x00FF,
TYPE_GPA4 = 0x5500,
TYPE_GPA5 = 0x5555,
TYPE_GPA6 = 0x55AA,
TYPE_GPA7 = 0x55FF,
TYPE_GPA8 = 0xAA00,
TYPE_GPA9 = 0xAA55,
TYPE_GPA10 = 0xAAAA,
TYPE_GPA11 = 0xAAFF,
TYPE_GPA12 = 0xFF00,
TYPE_GPA13 = 0xFF55,
TYPE_GPA14 = 0xFFAA,
TYPE_GPA15 = 0xFFFF,
}ODM_TYPE_GPA_E;
typedef enum tag_ODM_TYPE_APA_Definition {
TYPE_APA0 = 0x0000,
TYPE_APA1 = 0x0055,
TYPE_APA2 = 0x00AA,
TYPE_APA3 = 0x00FF,
TYPE_APA4 = 0x5500,
TYPE_APA5 = 0x5555,
TYPE_APA6 = 0x55AA,
TYPE_APA7 = 0x55FF,
TYPE_APA8 = 0xAA00,
TYPE_APA9 = 0xAA55,
TYPE_APA10 = 0xAAAA,
TYPE_APA11 = 0xAAFF,
TYPE_APA12 = 0xFF00,
TYPE_APA13 = 0xFF55,
TYPE_APA14 = 0xFFAA,
TYPE_APA15 = 0xFFFF,
}ODM_TYPE_APA_E;
typedef enum tag_ODM_TYPE_GLNA_Definition {
TYPE_GLNA0 = 0x0000,
TYPE_GLNA1 = 0x0055,
TYPE_GLNA2 = 0x00AA,
TYPE_GLNA3 = 0x00FF,
TYPE_GLNA4 = 0x5500,
TYPE_GLNA5 = 0x5555,
TYPE_GLNA6 = 0x55AA,
TYPE_GLNA7 = 0x55FF,
TYPE_GLNA8 = 0xAA00,
TYPE_GLNA9 = 0xAA55,
TYPE_GLNA10 = 0xAAAA,
TYPE_GLNA11 = 0xAAFF,
TYPE_GLNA12 = 0xFF00,
TYPE_GLNA13 = 0xFF55,
TYPE_GLNA14 = 0xFFAA,
TYPE_GLNA15 = 0xFFFF,
}ODM_TYPE_GLNA_E;
typedef enum tag_ODM_TYPE_ALNA_Definition {
TYPE_ALNA0 = 0x0000,
TYPE_ALNA1 = 0x0055,
TYPE_ALNA2 = 0x00AA,
TYPE_ALNA3 = 0x00FF,
TYPE_ALNA4 = 0x5500,
TYPE_ALNA5 = 0x5555,
TYPE_ALNA6 = 0x55AA,
TYPE_ALNA7 = 0x55FF,
TYPE_ALNA8 = 0xAA00,
TYPE_ALNA9 = 0xAA55,
TYPE_ALNA10 = 0xAAAA,
TYPE_ALNA11 = 0xAAFF,
TYPE_ALNA12 = 0xFF00,
TYPE_ALNA13 = 0xFF55,
TYPE_ALNA14 = 0xFFAA,
TYPE_ALNA15 = 0xFFFF,
}ODM_TYPE_ALNA_E;
typedef enum _ODM_RF_RADIO_PATH {
ODM_RF_PATH_A = 0, //Radio Path A
ODM_RF_PATH_B = 1, //Radio Path B
ODM_RF_PATH_C = 2, //Radio Path C
ODM_RF_PATH_D = 3, //Radio Path D
ODM_RF_PATH_AB,
ODM_RF_PATH_AC,
ODM_RF_PATH_AD,
ODM_RF_PATH_BC,
ODM_RF_PATH_BD,
ODM_RF_PATH_CD,
ODM_RF_PATH_ABC,
ODM_RF_PATH_ACD,
ODM_RF_PATH_BCD,
ODM_RF_PATH_ABCD,
// ODM_RF_PATH_MAX, //Max RF number 90 support
} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
typedef enum _ODM_PARAMETER_INIT {
ODM_PRE_SETTING = 0,
ODM_POST_SETTING = 1,
} ODM_PARAMETER_INIT_E;
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_precomp.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "phydm_types.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting.
#else
#define TEST_FALG___ 1
#endif
//2 Config Flags and Structs - defined by each ODM Type
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
#define __PACK
#define __WLAN_ATTRIB_PACK__
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Mp_Precomp.h"
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#define __PACK
#define __WLAN_ATTRIB_PACK__
#endif
//2 OutSrc Header Files
#include "phydm.h"
#include "phydm_HWConfig.h"
#include "phydm_debug.h"
#include "phydm_RegDefine11AC.h"
#include "phydm_RegDefine11N.h"
#include "phydm_interface.h"
#include "phydm_reg.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#define RTL8821B_SUPPORT 0
#define RTL8822B_SUPPORT 0
VOID
PHY_SetTxPowerLimit(
IN PDM_ODM_T pDM_Odm,
IN u8 *Regulation,
IN u8 *Band,
IN u8 *Bandwidth,
IN u8 *RateSection,
IN u8 *RfPath,
IN u8 *Channel,
IN u8 *PowerLimit
);
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#define RTL8821B_SUPPORT 0
#define RTL8822B_SUPPORT 0
#define RTL8703B_SUPPORT 0
#define RTL8188F_SUPPORT 0
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#include "rtl8188e/HalHWImg8188E_MAC.h"
#include "rtl8188e/HalHWImg8188E_RF.h"
#include "rtl8188e/HalHWImg8188E_BB.h"
#include "rtl8188e/HalHWImg8188E_FW.h"
#include "rtl8188e/phydm_RegConfig8188E.h"
#include "rtl8188e/phydm_RTL8188E.h"
#include "rtl8188e/Hal8188EReg.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8188e_hal.h"
#include "rtl8188e/HalPhyRf_8188e_CE.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "rtl8188e/HalPhyRf_8188e_WIN.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8188e/HalPhyRf_8188e_AP.h"
#endif
#endif //88E END
#if (RTL8192E_SUPPORT==1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "rtl8192e/HalPhyRf_8192e_WIN.h" /*FOR_8192E_IQK*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8192e/HalPhyRf_8192e_AP.h" /*FOR_8192E_IQK*/
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8192e/HalPhyRf_8192e_CE.h" /*FOR_8192E_IQK*/
#endif
#include "rtl8192e/phydm_RTL8192E.h" //FOR_8192E_IQK
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8192e/HalHWImg8192E_BB.h"
#include "rtl8192e/HalHWImg8192E_MAC.h"
#include "rtl8192e/HalHWImg8192E_RF.h"
#include "rtl8192e/phydm_RegConfig8192E.h"
#include "rtl8192e/HalHWImg8192E_FW.h"
#include "rtl8192e/Hal8192EReg.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8192e_hal.h"
#endif
#endif //92E END
#if (RTL8812A_SUPPORT==1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "rtl8812a/HalPhyRf_8812A_WIN.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8812a/HalPhyRf_8812A_AP.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8812a/HalPhyRf_8812A_CE.h"
#endif
//#include "rtl8812a/HalPhyRf_8812A.h" //FOR_8812_IQK
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8812a/HalHWImg8812A_BB.h"
#include "rtl8812a/HalHWImg8812A_MAC.h"
#include "rtl8812a/HalHWImg8812A_RF.h"
#include "rtl8812a/phydm_RegConfig8812A.h"
#include "rtl8812a/HalHWImg8812A_FW.h"
#include "rtl8812a/phydm_RTL8812A.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8812a_hal.h"
#endif
#endif //8812 END
#if (RTL8814A_SUPPORT==1)
#include "rtl8814a/HalHWImg8814A_MAC.h"
#include "rtl8814a/HalHWImg8814A_RF.h"
#include "rtl8814a/HalHWImg8814A_BB.h"
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#include "rtl8814a/HalHWImg8814A_FW.h"
#include "rtl8814a/phydm_RTL8814A.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "rtl8814a/HalPhyRf_8814A_WIN.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8814a/HalPhyRf_8814A_CE.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8814a/HalPhyRf_8814A_AP.h"
#endif
#include "rtl8814a/phydm_RegConfig8814A.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8814a_hal.h"
#include "rtl8814a/PhyDM_IQK_8814A.h"
#endif
#endif //8814 END
#if (RTL8881A_SUPPORT==1)//FOR_8881_IQK
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "rtl8821a/PhyDM_IQK_8821A_WIN.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8821a/PhyDM_IQK_8821A_CE.h"
#else
#include "rtl8821a/PhyDM_IQK_8821A_AP.h"
#endif
//#include "rtl8881a/HalHWImg8881A_BB.h"
//#include "rtl8881a/HalHWImg8881A_MAC.h"
//#include "rtl8881a/HalHWImg8881A_RF.h"
//#include "rtl8881a/odm_RegConfig8881A.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalHWImg8723B_MAC.h"
#include "rtl8723b/HalHWImg8723B_RF.h"
#include "rtl8723b/HalHWImg8723B_BB.h"
#include "rtl8723b/HalHWImg8723B_FW.h"
#include "rtl8723b/phydm_RegConfig8723B.h"
#include "rtl8723b/phydm_RTL8723B.h"
#include "rtl8723b/Hal8723BReg.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "rtl8723b/HalPhyRf_8723B_WIN.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8723b/HalPhyRf_8723B_CE.h"
#include "rtl8723b/HalHWImg8723B_MP.h"
#include "rtl8723b_hal.h"
#endif
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalHWImg8821A_MAC.h"
#include "rtl8821a/HalHWImg8821A_RF.h"
#include "rtl8821a/HalHWImg8821A_BB.h"
#include "rtl8821a/HalHWImg8821A_FW.h"
#include "rtl8821a/phydm_RegConfig8821A.h"
#include "rtl8821a/phydm_RTL8821A.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "rtl8821a/HalPhyRf_8821A_WIN.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8821a/HalPhyRf_8821A_CE.h"
#include "rtl8821a/PhyDM_IQK_8821A_CE.h"/*for IQK*/
#include "rtl8812a/HalPhyRf_8812A_CE.h"/*for IQK,LCK,Power-tracking*/
#include "rtl8812a_hal.h"
#else
#endif
#endif
#if (RTL8821B_SUPPORT==1)
#include "rtl8821b/HalHWImg8821B_MAC.h"
#include "rtl8821b/HalHWImg8821B_RF.h"
#include "rtl8821b/HalHWImg8821B_BB.h"
#include "rtl8821b/HalHWImg8821B_FW.h"
#include "rtl8821b/phydm_RegConfig8821B.h"
#include "rtl8821b/HalHWImg8821B_TestChip_MAC.h"
#include "rtl8821b/HalHWImg8821B_TestChip_RF.h"
#include "rtl8821b/HalHWImg8821B_TestChip_BB.h"
#include "rtl8821b/HalHWImg8821B_TestChip_FW.h"
#include "rtl8821b/HalPhyRf_8821B.h"
#endif
#if (RTL8822B_SUPPORT==1)
#include "rtl8822b/halhwimg8822b_mac.h"
#include "rtl8822b/halhwimg8822b_rf.h"
#include "rtl8822b/halhwimg8822b_bb.h"
/*#include "rtl8822b/halhwimg8822b_fw.h"*/
#include "rtl8822b/phydm_regconfig8822b.h"
#include "rtl8822b/halphyrf_8822b.h"
#include "rtl8822b/phydm_rtl8822b.h"
#include "rtl8822b/phydm_hal_api8822b.h"
#include "rtl8822b/version_rtl8822b.h"
#endif
#if (RTL8703B_SUPPORT==1)
#include "rtl8703b/phydm_regconfig8703b.h"
#include "rtl8703b/halhwimg8703b_mac.h"
#include "rtl8703b/halhwimg8703b_rf.h"
#include "rtl8703b/halhwimg8703b_bb.h"
#include "rtl8703b/halhwimg8703b_fw.h"
#include "rtl8703b/halphyrf_8703b.h"
#include "rtl8703b/version_rtl8703b.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8703b_hal.h"
#endif
#endif
#if (RTL8188F_SUPPORT == 1)
#include "rtl8188f/halhwimg8188f_mac.h"
#include "rtl8188f/halhwimg8188f_rf.h"
#include "rtl8188f/halhwimg8188f_bb.h"
#include "rtl8188f/halhwimg8188f_fw.h"
#include "rtl8188f/hal8188freg.h"
#include "rtl8188f/phydm_rtl8188f.h"
#include "rtl8188f/phydm_regconfig8188f.h"
#include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include "rtl8188f_hal.h"
#endif
#endif
#endif // __ODM_PRECOMP_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_reg.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: odm_reg.h
//
// Description:
//
// This file is for general register definition.
//
//
//============================================================
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
//
// Register Definition
//
//MAC REG
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define RF_T_METER_OLD 0x24
#define RF_T_METER_NEW 0x42
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
//BB REG
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_6_18 0x830
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
//RF REG
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
#define ODM_RF_T_METER 0x24
#define ODM_RF_T_METER_92D 0x42
#define ODM_RF_T_METER_88E 0x42
#define ODM_RF_T_METER_92E 0x42
#define ODM_RF_T_METER_8812 0x42
#define rRF_TxGainOffset 0x55
//Ant Detect Reg
#define ODM_DPDT 0x300
//PSD Init
#define ODM_PSDREG 0x808
//92D Path Div
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
//
// Bitmap Definition
//
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
// TX AGC
#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
#if defined(CONFIG_WLAN_HAL_8814AE)
#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8
#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc
#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0
#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4
#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8
#endif
#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
#if defined(CONFIG_WLAN_HAL_8814AE)
#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8
#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc
#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0
#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4
#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8
#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820
#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824
#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828
#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c
#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830
#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834
#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838
#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c
#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840
#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844
#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848
#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c
#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8
#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc
#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0
#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4
#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8
#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20
#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24
#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28
#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c
#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30
#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34
#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38
#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c
#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40
#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44
#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48
#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c
#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8
#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc
#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0
#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4
#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8
#endif
#define bTxAGC_byte0_Jaguar 0xff
#define bTxAGC_byte1_Jaguar 0xff00
#define bTxAGC_byte2_Jaguar 0xff0000
#define bTxAGC_byte3_Jaguar 0xff000000
#endif
#define BIT_FA_RESET BIT0
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/phydm_types.h
Executable
+316
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@@ -0,0 +1,316 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_TYPES_H__
#define __ODM_TYPES_H__
/*Define Different SW team support*/
#define ODM_AP 0x01 /*BIT0*/
#define ODM_CE 0x04 /*BIT2*/
#define ODM_WIN 0x08 /*BIT3*/
#define DM_ODM_SUPPORT_TYPE ODM_AP
/*Deifne HW endian support*/
#define ODM_ENDIAN_BIG 0
#define ODM_ENDIAN_LITTLE 1
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc)))
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv)))
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define RT_PCI_INTERFACE 1
#define RT_USB_INTERFACE 2
#define RT_SDIO_INTERFACE 3
#endif
typedef enum _HAL_STATUS{
HAL_STATUS_SUCCESS,
HAL_STATUS_FAILURE,
/*RT_STATUS_PENDING,
RT_STATUS_RESOURCE,
RT_STATUS_INVALID_CONTEXT,
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,*/
}HAL_STATUS,*PHAL_STATUS;
#if( DM_ODM_SUPPORT_TYPE == ODM_AP)
#define MP_DRIVER 0
#endif
#if(DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define VISTA_USB_RX_REVISE 0
//
// Declare for ODM spin lock defintion temporarily fro compile pass.
//
typedef enum _RT_SPINLOCK_TYPE{
RT_TX_SPINLOCK = 1,
RT_RX_SPINLOCK = 2,
RT_RM_SPINLOCK = 3,
RT_CAM_SPINLOCK = 4,
RT_SCAN_SPINLOCK = 5,
RT_LOG_SPINLOCK = 7,
RT_BW_SPINLOCK = 8,
RT_CHNLOP_SPINLOCK = 9,
RT_RF_OPERATE_SPINLOCK = 10,
RT_INITIAL_SPINLOCK = 11,
RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30.
#if VISTA_USB_RX_REVISE
RT_USBRX_CONTEXT_SPINLOCK = 13,
RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR
#endif
//Shall we define Ndis 6.2 SpinLock Here ?
RT_PORT_SPINLOCK=16,
RT_VNIC_SPINLOCK=17,
RT_HVL_SPINLOCK=18,
RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
RT_BTData_SPINLOCK=25,
RT_WAPI_OPTION_SPINLOCK=26,
RT_WAPI_RX_SPINLOCK=27,
// add for 92D CCK control issue
RT_CCK_PAGEA_SPINLOCK = 28,
RT_BUFFER_SPINLOCK = 29,
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
RT_GEN_TEMP_BUF_SPINLOCK = 31,
RT_AWB_SPINLOCK = 32,
RT_FW_PS_SPINLOCK = 33,
RT_HW_TIMER_SPIN_LOCK = 34,
RT_MPT_WI_SPINLOCK = 35,
RT_P2P_SPIN_LOCK = 36, // Protect P2P context
RT_DBG_SPIN_LOCK = 37,
RT_IQK_SPINLOCK = 38,
RT_PENDED_OID_SPINLOCK = 39,
RT_CHNLLIST_SPINLOCK = 40,
RT_INDIC_SPINLOCK = 41, //protect indication
RT_RFD_SPINLOCK = 42,
RT_SYNC_IO_CNT_SPINLOCK = 43,
RT_LAST_SPINLOCK,
}RT_SPINLOCK_TYPE;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define STA_INFO_T RT_WLAN_STA
#define PSTA_INFO_T PRT_WLAN_STA
#define CONFIG_HW_ANTENNA_DIVERSITY
#define CONFIG_SW_ANTENNA_DIVERSITY
/*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_ANT_DETECTION
#define CONFIG_RA_DBG_CMD
#define __func__ __FUNCTION__
#define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT
#define bMaskH3Bytes 0xffffff00
#define SUCCESS 0
#define FAIL (-1)
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
#define ADSL_AP_BUILD_WORKAROUND
#define AP_BUILD_WORKAROUND
//2 [ Configure RA Debug H2C CMD ]
#define CONFIG_RA_DBG_CMD
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#define CONFIG_RA_DYNAMIC_RATE_ID
//2 [ Configure Antenna Diversity ]
#if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH)
#define CONFIG_HW_ANTENNA_DIVERSITY
#define ODM_EVM_ENHANCE_ANTDIV
//----------
#if(!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_2G_DIVERSITY
#endif
#ifdef CONFIG_NO_5G_DIVERSITY_8881A
#define CONFIG_NO_5G_DIVERSITY
#elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A)
#define CONFIG_5G_CGCS_RX_DIVERSITY
#elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A)
#define CONFIG_5G_CG_TRX_DIVERSITY
#elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)
#define CONFIG_2G5G_CG_TRX_DIVERSITY
#endif
#if(!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
#define CONFIG_NO_5G_DIVERSITY
#endif
//----------
#if ( defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_NOT_SUPPORT_ANTDIV
#elif( !defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_2G_SUPPORT_ANTDIV
#elif( defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_5G_SUPPORT_ANTDIV
#elif( (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY) )
#define CONFIG_2G5G_SUPPORT_ANTDIV
#endif
//----------
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../typedef.h"
#else
typedef void VOID,*PVOID;
typedef unsigned char BOOLEAN,*PBOOLEAN;
typedef unsigned char u1Byte,*pu1Byte;
typedef unsigned short u2Byte,*pu2Byte;
typedef unsigned int u4Byte,*pu4Byte;
typedef unsigned long long u8Byte,*pu8Byte;
#if 1
/* In ARM platform, system would use the type -- "char" as "unsigned char"
* And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/
typedef signed char s1Byte,*ps1Byte;
#else
typedef char s1Byte,*ps1Byte;
#endif
typedef short s2Byte,*ps2Byte;
typedef long s4Byte,*ps4Byte;
typedef long long s8Byte,*ps8Byte;
#endif
typedef struct rtl8192cd_priv *prtl8192cd_priv;
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#ifdef CONFIG_PCI_HCI
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#endif
#define _TRUE 1
#define _FALSE 0
#if (defined(TESTCHIP_SUPPORT))
#define PHYDM_TESTCHIP_SUPPORT 1
#else
#define PHYDM_TESTCHIP_SUPPORT 0
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <drv_types.h>
/*#define CONFIG_RA_DBG_CMD*/
/*#define CONFIG_ANT_DETECTION*/
/*#define CONFIG_PATH_DIVERSITY*/
/*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/
#if 0
typedef u8 u1Byte, *pu1Byte;
typedef u16 u2Byte,*pu2Byte;
typedef u32 u4Byte,*pu4Byte;
typedef u64 u8Byte,*pu8Byte;
typedef s8 s1Byte,*ps1Byte;
typedef s16 s2Byte,*ps2Byte;
typedef s32 s4Byte,*ps4Byte;
typedef s64 s8Byte,*ps8Byte;
#else
#define u1Byte u8
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
#endif
#ifdef CONFIG_USB_HCI
#define DEV_BUS_TYPE RT_USB_INTERFACE
#elif defined(CONFIG_PCI_HCI)
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#elif defined(CONFIG_SDIO_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_GSPI_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#endif
#if defined(CONFIG_LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#elif defined (CONFIG_BIG_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#endif
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define STA_INFO_T struct sta_info
#define PSTA_INFO_T struct sta_info *
#define TRUE _TRUE
#define FALSE _FALSE
#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
//define useless flag to avoid compile warning
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
/*#define BT_30_SUPPORT 0*/
#define FPGA_TWO_MAC_VERIFICATION 0
#define RTL8881A_SUPPORT 0
#if (defined(TESTCHIP_SUPPORT))
#define PHYDM_TESTCHIP_SUPPORT 1
#else
#define PHYDM_TESTCHIP_SUPPORT 0
#endif
#endif
#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
#define COND_ELSE 2
#define COND_ENDIF 3
#endif // __ODM_TYPES_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/Hal8188EFWImg_CE_OFFLOAD8.c
Executable
+895
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@@ -0,0 +1,895 @@
#ifdef USE_OUT_SRC
#include "Mp_Precomp.h"
#include "../odm_precomp.h"
#else
#include "../../8192cd_cfg.h"
#endif
#ifdef CONFIG_RTL_88E_SUPPORT
u1Byte Array_8188E_FW_AP[] = {
0xE1, 0x88, 0x20, 0x00, 0x0D, 0x00, 0x00, 0x00, 0x07, 0x09, 0x11, 0x23, 0xCE, 0x36, 0x00, 0x00,
0xCC, 0xCC, 0xCC, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x02, 0x46, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x02, 0x4A, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x02, 0x49, 0xC5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x57, 0xCA, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xE7, 0x09, 0xF6, 0x08, 0xDF, 0xFA, 0x80, 0x46, 0xE7, 0x09, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x3E,
0x88, 0x82, 0x8C, 0x83, 0xE7, 0x09, 0xF0, 0xA3, 0xDF, 0xFA, 0x80, 0x32, 0xE3, 0x09, 0xF6, 0x08,
0xDF, 0xFA, 0x80, 0x78, 0xE3, 0x09, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x70, 0x88, 0x82, 0x8C, 0x83,
0xE3, 0x09, 0xF0, 0xA3, 0xDF, 0xFA, 0x80, 0x64, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xA3, 0xF6, 0x08,
0xDF, 0xFA, 0x80, 0x58, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xA3, 0xF2, 0x08, 0xDF, 0xFA, 0x80, 0x4C,
0x80, 0xD2, 0x80, 0xFA, 0x80, 0xC6, 0x80, 0xD4, 0x80, 0x69, 0x80, 0xF2, 0x80, 0x33, 0x80, 0x10,
0x80, 0xA6, 0x80, 0xEA, 0x80, 0x9A, 0x80, 0xA8, 0x80, 0xDA, 0x80, 0xE2, 0x80, 0xCA, 0x80, 0x33,
0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE4, 0x93, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83,
0xCC, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xDF, 0xE9, 0xDE, 0xE7, 0x80,
0x0D, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xA3, 0xF6, 0x08, 0xDF, 0xF9, 0xEC, 0xFA, 0xA9, 0xF0,
0xED, 0xFB, 0x22, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA, 0xE0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC,
0xC5, 0x83, 0xCC, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xDF, 0xEA, 0xDE,
0xE8, 0x80, 0xDB, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xA3, 0xF2, 0x08, 0xDF, 0xF9, 0x80, 0xCC,
0x88, 0xF0, 0xEF, 0x60, 0x01, 0x0E, 0x4E, 0x60, 0xC3, 0x88, 0xF0, 0xED, 0x24, 0x02, 0xB4, 0x04,
0x00, 0x50, 0xB9, 0xF5, 0x82, 0xEB, 0x24, 0x02, 0xB4, 0x04, 0x00, 0x50, 0xAF, 0x23, 0x23, 0x45,
0x82, 0x23, 0x90, 0x41, 0x50, 0x73, 0xC5, 0xF0, 0xF8, 0xA3, 0xE0, 0x28, 0xF0, 0xC5, 0xF0, 0xF8,
0xE5, 0x82, 0x15, 0x82, 0x70, 0x02, 0x15, 0x83, 0xE0, 0x38, 0xF0, 0x22, 0xEF, 0x5B, 0xFF, 0xEE,
0x5A, 0xFE, 0xED, 0x59, 0xFD, 0xEC, 0x58, 0xFC, 0x22, 0xEF, 0x4B, 0xFF, 0xEE, 0x4A, 0xFE, 0xED,
0x49, 0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFE, 0xA3, 0xE0,
0xFF, 0x22, 0xE0, 0xF8, 0xA3, 0xE0, 0xF9, 0xA3, 0xE0, 0xFA, 0xA3, 0xE0, 0xFB, 0x22, 0xA4, 0x25,
0x82, 0xF5, 0x82, 0xE5, 0xF0, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xE0, 0xFB, 0xA3, 0xE0, 0xFA, 0xA3,
0xE0, 0xF9, 0x22, 0xEB, 0xF0, 0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xD0, 0x83, 0xD0, 0x82,
0xF8, 0xE4, 0x93, 0x70, 0x12, 0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93, 0xF8, 0x74, 0x01,
0x93, 0xF5, 0x82, 0x88, 0x83, 0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60, 0xEF, 0xA3, 0xA3, 0xA3,
0x80, 0xDF, 0xE3, 0xF5, 0xF0, 0x09, 0xE2, 0x08, 0xB5, 0xF0, 0x6B, 0xDF, 0xF5, 0x80, 0x67, 0xE3,
0xF5, 0xF0, 0x09, 0xE6, 0x08, 0xB5, 0xF0, 0x5E, 0xDF, 0xF5, 0x80, 0x5A, 0x87, 0xF0, 0x09, 0xE6,
0x08, 0xB5, 0xF0, 0x52, 0xDF, 0xF6, 0x80, 0x4E, 0x87, 0xF0, 0x09, 0xE2, 0x08, 0xB5, 0xF0, 0x46,
0xDF, 0xF6, 0x80, 0x42, 0x88, 0x82, 0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE0, 0xA3, 0xB5, 0xF0, 0x36,
0xDF, 0xF6, 0x80, 0x32, 0x88, 0x82, 0x8C, 0x83, 0x87, 0xF0, 0x09, 0xE4, 0x93, 0xA3, 0xB5, 0xF0,
0x25, 0xDF, 0xF5, 0x80, 0x21, 0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5, 0xF0, 0x09, 0xE0, 0xA3, 0xB5,
0xF0, 0x14, 0xDF, 0xF5, 0x80, 0x10, 0x88, 0x82, 0x8C, 0x83, 0xE3, 0xF5, 0xF0, 0x09, 0xE4, 0x93,
0xA3, 0xB5, 0xF0, 0x02, 0xDF, 0xF4, 0x02, 0x43, 0xB1, 0x80, 0x87, 0x80, 0xE9, 0x80, 0x90, 0x80,
0xD4, 0x80, 0x3E, 0x80, 0x15, 0x80, 0x6E, 0x80, 0x7E, 0x80, 0x9D, 0x80, 0xB7, 0x80, 0x8D, 0x80,
0xA3, 0x80, 0x51, 0x80, 0x74, 0x80, 0x3C, 0x02, 0x43, 0xBD, 0x89, 0x82, 0x8A, 0x83, 0xEC, 0xFA,
0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xE4, 0x93, 0xA3,
0xC8, 0xC5, 0x82, 0xC8, 0xCC, 0xC5, 0x83, 0xCC, 0xB5, 0xF0, 0x76, 0xDF, 0xE3, 0xDE, 0xE1, 0x80,
0x70, 0x89, 0x82, 0x8A, 0x83, 0xE4, 0x93, 0xF5, 0xF0, 0xA3, 0xE2, 0x08, 0xB5, 0xF0, 0x62, 0xDF,
0xF4, 0x80, 0x5E, 0x89, 0x82, 0x8A, 0x83, 0xE0, 0xF5, 0xF0, 0xA3, 0xE6, 0x08, 0xB5, 0xF0, 0x51,
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0x90, 0x82, 0x6D, 0xED, 0xF0, 0x90, 0x82, 0x6C, 0xEF, 0xF0, 0xD3, 0x94, 0x07, 0x50, 0x70, 0xE0,
0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00,
0x47, 0xE0, 0x5F, 0xFD, 0x7F, 0x47, 0x12, 0x32, 0x1E, 0x90, 0x82, 0x6C, 0xE0, 0xFF, 0x74, 0x01,
0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x46, 0xE0, 0x4F, 0xFD,
0x7F, 0x46, 0x12, 0x32, 0x1E, 0x90, 0x82, 0x6D, 0xE0, 0x60, 0x18, 0x90, 0x82, 0x6C, 0xE0, 0xFF,
0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x45, 0xE0,
0x4F, 0x80, 0x17, 0x90, 0x82, 0x6C, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3,
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0x82, 0x6C, 0xE0, 0x24, 0xF8, 0xF0, 0xE0, 0x24, 0x04, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80,
0x02, 0xC3, 0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x43, 0xE0, 0x5F, 0xFD, 0x7F, 0x43, 0x12,
0x32, 0x1E, 0x90, 0x82, 0x6C, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, 0x80, 0x02, 0xC3, 0x33,
0xD8, 0xFC, 0xFF, 0x90, 0x00, 0x43, 0xE0, 0x4F, 0xFD, 0x7F, 0x43, 0x12, 0x32, 0x1E, 0x90, 0x82,
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0x33, 0xD8, 0xFC, 0xF4, 0xFF, 0x90, 0x00, 0x42, 0xE0, 0x5F, 0xFD, 0x7F, 0x42, 0x12, 0x32, 0x1E,
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0x12, 0x2E, 0xA2, 0x90, 0x85, 0xBB, 0x12, 0x20, 0xDA, 0x00, 0x00, 0x00, 0x14, 0x7F, 0x70, 0x7E,
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0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x02, 0x49, 0xB3, 0x90, 0x81, 0x57, 0xE0, 0xFF, 0xC4, 0x13, 0x13,
0x54, 0x03, 0x30, 0xE0, 0x27, 0xEF, 0x54, 0xBF, 0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x90, 0x81, 0x58,
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0xF0, 0x90, 0x00, 0x83, 0xE0, 0xFE, 0x90, 0x81, 0x8E, 0xE0, 0xFF, 0xB5, 0x06, 0x01, 0x22, 0xC3,
0x90, 0x81, 0x90, 0xE0, 0x94, 0x64, 0x90, 0x81, 0x8F, 0xE0, 0x94, 0x00, 0x40, 0x0D, 0x90, 0x01,
0xC0, 0xE0, 0x44, 0x40, 0xF0, 0x90, 0x81, 0x8E, 0xE0, 0xFF, 0x22, 0x90, 0x81, 0x8F, 0xE4, 0x75,
0xF0, 0x01, 0x12, 0x41, 0xF6, 0x80, 0xC2, 0x90, 0x81, 0x57, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F,
0x30, 0xE0, 0x11, 0xEF, 0x54, 0xFB, 0xF0, 0x90, 0x81, 0x5E, 0xE0, 0x54, 0xFD, 0xF0, 0x54, 0x07,
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0x05, 0x58, 0xE0, 0x04, 0xF0, 0x90, 0x81, 0x6B, 0xE0, 0xFF, 0x90, 0x81, 0x63, 0xE0, 0xD3, 0x9F,
0x40, 0x0F, 0x90, 0x81, 0x16, 0xE0, 0xB4, 0x01, 0x0B, 0x90, 0x81, 0x58, 0xE0, 0x54, 0xFB, 0xF0,
0x22, 0x12, 0x4F, 0xEC, 0x22, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0xA6, 0x7F, 0xF5, 0x7E, 0x00, 0x12,
0x2B, 0x27, 0xBF, 0x01, 0x06, 0x90, 0x81, 0xA6, 0xE0, 0xA3, 0xF0, 0x7B, 0x01, 0x7A, 0x81, 0x79,
0xA6, 0x7F, 0xF6, 0x7E, 0x00, 0x12, 0x2B, 0x27, 0xBF, 0x01, 0x08, 0x90, 0x81, 0xA6, 0xE0, 0x90,
0x81, 0xA8, 0xF0, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0xA6, 0x7F, 0xF4, 0x7E, 0x00, 0x12, 0x2B, 0x27,
0xBF, 0x01, 0x08, 0x90, 0x81, 0xA6, 0xE0, 0x90, 0x81, 0xA9, 0xF0, 0x7B, 0x01, 0x7A, 0x81, 0x79,
0xA6, 0x7F, 0xF3, 0x7E, 0x00, 0x12, 0x2B, 0x27, 0xBF, 0x01, 0x08, 0x90, 0x81, 0xA6, 0xE0, 0x90,
0x81, 0xAA, 0xF0, 0x7B, 0x01, 0x7A, 0x81, 0x79, 0xA6, 0x7F, 0xF2, 0x7E, 0x00, 0x12, 0x2B, 0x27,
0xBF, 0x01, 0x08, 0x90, 0x81, 0xA6, 0xE0, 0x90, 0x81, 0xAB, 0xF0, 0x90, 0x81, 0xA7, 0xE0, 0xFF,
0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFB, 0xA3, 0xE0, 0x90, 0x81, 0xAF, 0xF0, 0x90, 0x81, 0xAB, 0xE0,
0x90, 0x81, 0xB0, 0xF0, 0x01, 0xD0, 0x12, 0x1F, 0xA4, 0xFF, 0x90, 0x81, 0x15, 0xF0, 0xBF, 0x01,
0x07, 0x51, 0xE5, 0xE4, 0x90, 0x81, 0x15, 0xF0, 0x22, 0x90, 0x81, 0xA3, 0x12, 0x42, 0x53, 0xEF,
0x12, 0x42, 0x5C, 0x5B, 0xC4, 0x00, 0x5B, 0xCC, 0x01, 0x5B, 0xD4, 0x02, 0x5B, 0xDC, 0x03, 0x5B,
0xE4, 0x04, 0x5B, 0xEC, 0x08, 0x5B, 0xF5, 0x09, 0x5B, 0xFD, 0x0A, 0x5C, 0x05, 0x12, 0x5C, 0x0D,
0x13, 0x5C, 0x16, 0x20, 0x5C, 0x1F, 0x21, 0x5C, 0x27, 0x23, 0x5C, 0x2F, 0x25, 0x5C, 0x37, 0x26,
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0x42, 0x4A, 0x81, 0xD7, 0x90, 0x81, 0xA3, 0x12, 0x42, 0x4A, 0xC1, 0xAD, 0x90, 0x81, 0xA3, 0x12,
0x42, 0x4A, 0xC1, 0x2D, 0x90, 0x81, 0xA3, 0x12, 0x42, 0x4A, 0x80, 0x5B, 0x90, 0x81, 0xA3, 0x12,
0x42, 0x4A, 0x02, 0x56, 0x38, 0x90, 0x81, 0xA3, 0x12, 0x42, 0x4A, 0xC1, 0x4D, 0x90, 0x81, 0xA3,
0x12, 0x42, 0x4A, 0xC1, 0x7D, 0x90, 0x81, 0xA3, 0x12, 0x42, 0x4A, 0x61, 0x76, 0x90, 0x81, 0xA3,
0x12, 0x42, 0x4A, 0x02, 0x67, 0x01, 0x90, 0x81, 0xA3, 0x12, 0x42, 0x4A, 0x02, 0x67, 0x6F, 0x90,
0x81, 0xA3, 0x12, 0x42, 0x4A, 0xE1, 0x1E, 0x90, 0x81, 0xA3, 0x12, 0x42, 0x4A, 0xA1, 0x7A, 0x90,
0x81, 0xA3, 0x12, 0x42, 0x4A, 0xA1, 0x82, 0x90, 0x81, 0xA3, 0x12, 0x42, 0x4A, 0xC1, 0xE5, 0x90,
0x01, 0xC0, 0xE0, 0x44, 0x01, 0xF0, 0x22, 0xB1, 0xA5, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE,
0x90, 0x81, 0x78, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30, 0xE0, 0x14, 0x90, 0x00,
0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x79, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81,
0x7A, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x80, 0x5C, 0xE0, 0xFF, 0x90,
0x80, 0x5B, 0xE0, 0xB5, 0x07, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, 0xEF, 0x70, 0x43, 0x90,
0x80, 0x5B, 0xE0, 0xFE, 0x75, 0xF0, 0x08, 0x90, 0x80, 0x0B, 0x12, 0x42, 0x3E, 0xE0, 0xFD, 0xEE,
0x75, 0xF0, 0x08, 0xA4, 0x24, 0x0C, 0xF9, 0x74, 0x80, 0x35, 0xF0, 0xFA, 0x7B, 0x01, 0xAF, 0x05,
0x71, 0x89, 0x90, 0x80, 0x5B, 0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0xB4, 0x0A, 0x02, 0x7F, 0x01,
0xEF, 0x60, 0x05, 0xE4, 0x90, 0x80, 0x5B, 0xF0, 0x12, 0x67, 0xEB, 0x90, 0x80, 0x01, 0xE0, 0x44,
0x02, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, 0x81, 0xA6, 0x12, 0x42, 0x53, 0x90, 0x00, 0x01,
0x12, 0x1F, 0xBD, 0xFF, 0xFE, 0x12, 0x1F, 0xA4, 0xFD, 0xC3, 0x13, 0x30, 0xE0, 0x12, 0x90, 0x81,
0xA6, 0x12, 0x42, 0x4A, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0xAA, 0xF0, 0x80, 0x05,
0x90, 0x81, 0xAA, 0xEF, 0xF0, 0x90, 0x81, 0xA9, 0xEE, 0xF0, 0x90, 0x81, 0xAA, 0xE0, 0xFE, 0x90,
0x81, 0xA9, 0xE0, 0xFF, 0xD3, 0x9E, 0x50, 0x38, 0x90, 0x81, 0xA6, 0x12, 0x42, 0x4A, 0x12, 0x1F,
0xA4, 0x54, 0x01, 0xFE, 0x74, 0x16, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEE, 0xF0,
0x74, 0x16, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x70, 0x04, 0xB1, 0x79, 0x80,
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0x90, 0x81, 0x16, 0xE0, 0x70, 0x21, 0x90, 0x81, 0x5D, 0xE0, 0x70, 0x04, 0xFF, 0x12, 0x4D, 0x63,
0x90, 0x81, 0x5D, 0xE0, 0x64, 0x0C, 0x60, 0x02, 0xB1, 0x92, 0x90, 0x81, 0x57, 0xE0, 0x54, 0xF7,
0xF0, 0x54, 0xBF, 0xF0, 0x54, 0x7F, 0xF0, 0x22, 0x22, 0x22, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x64,
0xF0, 0x22, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x71, 0xF0, 0x90, 0x81, 0x71, 0xE0, 0x90, 0x01, 0xE7,
0xF0, 0x22, 0x90, 0x06, 0x04, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, 0x81,
0x5D, 0x74, 0x0C, 0xF0, 0x22, 0x90, 0x81, 0x78, 0xE0, 0x54, 0xFE, 0xF0, 0xA3, 0x74, 0x03, 0xF0,
0xA3, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0xB1, 0xE0, 0xB1, 0xE6, 0x12, 0x6D,
0xEC, 0xD1, 0x18, 0xB1, 0xF4, 0xB1, 0xA5, 0xD1, 0x06, 0x12, 0x49, 0x66, 0x90, 0x81, 0x88, 0xE0,
0x54, 0x7F, 0xF0, 0x54, 0xBF, 0xF0, 0x54, 0xDF, 0xF0, 0x54, 0xF0, 0xF0, 0xE4, 0xA3, 0xF0, 0x22,
0xE4, 0x90, 0x81, 0x16, 0xF0, 0x22, 0xE4, 0x90, 0x80, 0xF3, 0xF0, 0xA3, 0xF0, 0x90, 0x80, 0x5B,
0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x81, 0x75, 0xE0, 0x54, 0xFE, 0xF0, 0x54, 0x7F, 0xF0, 0xA3, 0x74,
0x0A, 0xF0, 0xE4, 0xA3, 0xF0, 0x22, 0xE4, 0x90, 0x80, 0xF7, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3,
0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x81, 0x72, 0xE0, 0x54, 0xFE, 0xF0, 0x54,
0xFD, 0xF0, 0xE4, 0xA3, 0xF0, 0x90, 0x81, 0x72, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x12, 0x1F, 0xA4,
0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0x75, 0xE0, 0x54, 0xFE, 0x4E, 0xF0, 0xEF, 0xC3, 0x13, 0x30,
0xE0, 0x0A, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x76, 0xF0, 0x22, 0x12, 0x1F, 0xA4,
0x90, 0x81, 0x0B, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x0C, 0xF0, 0x90, 0x00,
0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x0D, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x90, 0x81,
0x0E, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x0F, 0xF0, 0x22, 0x12, 0x1F, 0xA4,
0x90, 0x81, 0x10, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x11, 0xF0, 0x90, 0x00,
0x02, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x12, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x90, 0x81,
0x13, 0xF0, 0x90, 0x00, 0x04, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x14, 0xF0, 0x22, 0xD3, 0x10, 0xAF,
0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x1F, 0xA4, 0xFF, 0x90, 0x81, 0x56, 0xF0, 0xBF, 0x01, 0x12, 0x90,
0x00, 0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x60, 0x17, 0x90, 0x05, 0x22, 0x74, 0x6F, 0xF0, 0x80,
0x0F, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0x64, 0x01, 0x60, 0x05, 0x90, 0x05, 0x22, 0xE4, 0xF0,
0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x12, 0x1F, 0xA4, 0xFF, 0x54, 0x01, 0xFE, 0x90, 0x81, 0x72, 0xE0,
0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF, 0x54, 0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0xF0, 0x90, 0x00,
0x01, 0x12, 0x1F, 0xBD, 0xFF, 0x90, 0x05, 0x54, 0xE0, 0xC3, 0x9F, 0x90, 0x81, 0x73, 0xF0, 0x12,
0x1F, 0xA4, 0x20, 0xE0, 0x08, 0x12, 0x4D, 0xD3, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x22, 0x90, 0x00,
0x02, 0x12, 0x1F, 0xBD, 0xFF, 0x30, 0xE0, 0x26, 0x12, 0x1F, 0xA4, 0x90, 0x81, 0x6B, 0xF0, 0x90,
0x00, 0x01, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x6C, 0xF0, 0xEF, 0x54, 0xFE, 0xFF, 0xA3, 0xE0, 0x54,
0x01, 0x4F, 0xF0, 0x90, 0x00, 0x03, 0x12, 0x1F, 0xBD, 0x90, 0x81, 0x6E, 0xF0, 0x22, 0x90, 0x81,
0x6B, 0x74, 0x01, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xA3, 0xE0, 0x54, 0x01, 0x44, 0x28, 0xF0, 0xA3,
0x74, 0x05, 0xF0, 0x22, 0x90, 0x02, 0x09, 0xE0, 0xFD, 0x12, 0x1F, 0xA4, 0xFE, 0xAF, 0x05, 0xED,
0x2E, 0x90, 0x80, 0x06, 0xF0, 0x90, 0x00, 0x01, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80,
0x07, 0xF0, 0x90, 0x00, 0x02, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x08, 0xF0, 0x90,
0x00, 0x03, 0x12, 0x1F, 0xBD, 0xFF, 0xED, 0x2F, 0x90, 0x80, 0x09, 0xF0, 0x90, 0x00, 0x04, 0x12,
0x1F, 0xBD, 0xFF, 0xAE, 0x05, 0xED, 0x2F, 0x90, 0x80, 0x0A, 0xF0, 0x22, 0x90, 0x00, 0xF7, 0xE0,
0x20, 0xE7, 0x09, 0xE0, 0x7F, 0x01, 0x20, 0xE6, 0x0C, 0x7F, 0x02, 0x22, 0x90, 0x00, 0xF7, 0xE0,
0x30, 0xE6, 0x02, 0x7F, 0x03, 0x22, 0xF1, 0xAC, 0x90, 0x80, 0x05, 0xEF, 0xF0, 0xF1, 0xD8, 0x90,
0x01, 0x64, 0x74, 0x01, 0xF0, 0x02, 0x2D, 0xA7, 0x12, 0x6A, 0x35, 0x12, 0x6A, 0xA0, 0x12, 0x6A,
0xD1, 0x12, 0x6A, 0xF0, 0xE4, 0xF5, 0x35, 0xF5, 0x36, 0xF5, 0x37, 0x75, 0x38, 0x80, 0xAD, 0x35,
0x7F, 0x50, 0x12, 0x32, 0x1E, 0xAD, 0x36, 0x7F, 0x51, 0x12, 0x32, 0x1E, 0xAD, 0x37, 0x7F, 0x52,
0x12, 0x32, 0x1E, 0xAD, 0x38, 0x7F, 0x53, 0x02, 0x32, 0x1E, 0x75, 0xE8, 0x03, 0x75, 0xA8, 0x84,
0x22, 0x90, 0x00, 0x80, 0xE0, 0x44, 0x80, 0xFD, 0x7F, 0x80, 0x12, 0x32, 0x1E, 0x90, 0xFD, 0x00,
0xE0, 0x54, 0xBF, 0xF0, 0x11, 0x6E, 0x12, 0x32, 0x77, 0x11, 0x88, 0x11, 0x62, 0x7F, 0x01, 0x12,
0x45, 0x41, 0x90, 0x81, 0x74, 0x74, 0x02, 0xF0, 0xFF, 0x12, 0x45, 0x41, 0x90, 0x81, 0x74, 0xE0,
0x04, 0xF0, 0x12, 0x5F, 0xC6, 0x12, 0x5D, 0xBA, 0x90, 0x00, 0x80, 0xE0, 0x44, 0x40, 0xFD, 0x7F,
0x80, 0x12, 0x32, 0x1E, 0x75, 0x20, 0xFF, 0x11, 0x0A, 0x11, 0xB8, 0x11, 0x7B, 0xE4, 0xFF, 0x02,
0x45, 0xCA, 0xE4, 0x90, 0x80, 0x01, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x01,
0x94, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x01, 0xC7, 0xE4, 0xF0, 0x22, 0x90, 0x01, 0xE4, 0x74, 0x0D,
0xF0, 0xA3, 0xE4, 0xF0, 0x74, 0xFF, 0xF0, 0x22, 0x90, 0x01, 0x01, 0xE0, 0x44, 0x04, 0xF0, 0x90,
0x01, 0x9C, 0x74, 0x7E, 0xF0, 0xA3, 0x74, 0x92, 0xF0, 0xA3, 0x74, 0xA0, 0xF0, 0xA3, 0x74, 0x24,
0xF0, 0x90, 0x01, 0x9B, 0x74, 0x49, 0xF0, 0x90, 0x01, 0x9A, 0x74, 0xE0, 0xF0, 0x90, 0x01, 0x99,
0xE4, 0xF0, 0x90, 0x01, 0x98, 0x04, 0xF0, 0x22, 0xE4, 0x90, 0x81, 0x9C, 0xF0, 0xA3, 0xF0, 0x90,
0x01, 0x98, 0xE0, 0x7F, 0x00, 0x30, 0xE4, 0x02, 0x7F, 0x01, 0xEF, 0x64, 0x01, 0x60, 0x45, 0xC3,
0x90, 0x81, 0x9D, 0xE0, 0x94, 0x88, 0x90, 0x81, 0x9C, 0xE0, 0x94, 0x13, 0x40, 0x0F, 0x90, 0x01,
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0x22, 0x90, 0x81, 0x5E, 0xE0, 0x44, 0x01, 0xF0, 0x90, 0x81, 0x59, 0xE0, 0x54, 0x0F, 0x64, 0x02,
0x60, 0x05, 0x12, 0x4F, 0xA0, 0x80, 0x0C, 0x12, 0x4E, 0xEF, 0x80, 0x07, 0x90, 0x81, 0x5E, 0xE0,
0x54, 0xFE, 0xF0, 0x90, 0x81, 0x8B, 0xE0, 0x90, 0x81, 0x5E, 0x30, 0xE7, 0x14, 0xE0, 0x44, 0x02,
0x12, 0x4F, 0xF5, 0x90, 0x01, 0x57, 0x74, 0x05, 0xF0, 0x90, 0x81, 0x57, 0xE0, 0x44, 0x04, 0xF0,
0x22, 0xE0, 0x54, 0xFD, 0xF0, 0x22, 0x22, 0x90, 0x80, 0x08, 0xE0, 0xFE, 0x90, 0x04, 0x1C, 0xE0,
0x6E, 0x70, 0x40, 0x90, 0x81, 0x5D, 0xE0, 0xFE, 0xB4, 0x0E, 0x18, 0xEF, 0x70, 0x35, 0x90, 0x81,
0x57, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x06, 0x04, 0xE0, 0x54, 0x7F, 0xF0, 0x90, 0x81, 0x5D, 0x74,
0x0C, 0xF0, 0x22, 0xEE, 0x64, 0x06, 0x70, 0x1B, 0xEF, 0x60, 0x18, 0x90, 0x81, 0x57, 0xE0, 0x54,
0xBF, 0xF0, 0x90, 0x06, 0x04, 0xE0, 0x44, 0x40, 0xF0, 0xE0, 0x44, 0x80, 0xF0, 0x90, 0x81, 0x5D,
0x74, 0x04, 0xF0, 0x22, 0xAB, 0x07, 0xAA, 0x06, 0xED, 0x2B, 0xFB, 0xE4, 0x3A, 0xFA, 0xC3, 0x90,
0x80, 0xF6, 0xE0, 0x9B, 0x90, 0x80, 0xF5, 0xE0, 0x9A, 0x50, 0x13, 0xA3, 0xE0, 0x24, 0x01, 0xFF,
0x90, 0x80, 0xF5, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0xEB, 0x9F, 0xFB, 0xEA, 0x9E, 0xFA, 0xEA, 0x90,
0xFD, 0x11, 0xF0, 0xAF, 0x03, 0x74, 0x00, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0,
0xFF, 0x22, 0x90, 0x02, 0x84, 0xEF, 0xF0, 0xEE, 0xA3, 0xF0, 0xA3, 0xE0, 0x44, 0x01, 0xF0, 0x22,
0x90, 0x81, 0x10, 0xE0, 0x90, 0x81, 0xD6, 0xF0, 0x90, 0x81, 0x11, 0xE0, 0x90, 0x81, 0xD7, 0xF0,
0x90, 0x81, 0x12, 0xE0, 0x90, 0x81, 0xD8, 0xF0, 0x90, 0x81, 0x13, 0xE0, 0x90, 0x81, 0xD9, 0xF0,
0x90, 0x81, 0x14, 0xE0, 0x90, 0x81, 0xDA, 0xF0, 0x90, 0x81, 0x01, 0xE0, 0x90, 0x81, 0xDB, 0xF0,
0x90, 0x81, 0x02, 0xE0, 0x90, 0x81, 0xDC, 0xF0, 0x90, 0x81, 0x03, 0xE0, 0x90, 0x81, 0xDD, 0xF0,
0x90, 0x81, 0x04, 0xE0, 0x90, 0x81, 0xDE, 0xF0, 0x90, 0x81, 0x05, 0xE0, 0x90, 0x81, 0xDF, 0xF0,
0x90, 0x81, 0x06, 0xE0, 0x90, 0x81, 0xE0, 0xF0, 0x90, 0x81, 0x07, 0xE0, 0x90, 0x81, 0xE1, 0xF0,
0x90, 0x81, 0x08, 0xE0, 0x90, 0x81, 0xE2, 0xF0, 0x90, 0x81, 0x09, 0xE0, 0x90, 0x81, 0xE3, 0xF0,
0x90, 0x81, 0x0A, 0xE0, 0x90, 0x81, 0xE4, 0xF0, 0xE4, 0x90, 0x81, 0xAE, 0xF0, 0x90, 0x81, 0xEA,
0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0xAD, 0xF0, 0x90, 0x80, 0xFE,
0xE0, 0xFF, 0x90, 0x81, 0xAD, 0xE0, 0xFE, 0xC3, 0x9F, 0x50, 0x15, 0x74, 0xEA, 0x2E, 0xF5, 0x82,
0xE4, 0x34, 0x81, 0xF5, 0x83, 0x74, 0x01, 0xF0, 0x90, 0x81, 0xAD, 0xE0, 0x04, 0xF0, 0x80, 0xDD,
0x90, 0x01, 0x1F, 0xE0, 0xFE, 0x90, 0x01, 0x1E, 0xE0, 0x7C, 0x00, 0x24, 0x00, 0xFF, 0xEC, 0x3E,
0x90, 0x81, 0xA3, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, 0x90, 0x81, 0xAD, 0xF0, 0x90, 0x80, 0xFE, 0xE0,
0xFF, 0x90, 0x81, 0xAD, 0xE0, 0xFE, 0xC3, 0x9F, 0x40, 0x02, 0x41, 0x01, 0x12, 0x6C, 0x82, 0x90,
0x81, 0xAD, 0xE0, 0xFE, 0x24, 0xE5, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEF, 0xF0, 0x74,
0xE5, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x24, 0x45, 0xF5, 0x82, 0xE4, 0x34,
0xFC, 0xF5, 0x83, 0xE0, 0xFF, 0x74, 0xAF, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xEF,
0xF0, 0x74, 0xE5, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x24, 0x46, 0xF9, 0xE4,
0x34, 0xFC, 0xFA, 0x7B, 0x01, 0xEE, 0x75, 0xF0, 0x03, 0xA4, 0x24, 0xB4, 0xF5, 0x82, 0xE4, 0x34,
0x81, 0xF5, 0x83, 0x12, 0x42, 0x53, 0x74, 0xE5, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83,
0xE0, 0x24, 0x30, 0xF9, 0xE4, 0x34, 0xFC, 0xFA, 0xEE, 0x75, 0xF0, 0x03, 0xA4, 0x24, 0xC7, 0xF5,
0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x12, 0x42, 0x53, 0x90, 0x81, 0xAD, 0xE0, 0x04, 0xF0, 0x21,
0x6C, 0x90, 0x02, 0x87, 0xE0, 0x70, 0x02, 0xC1, 0x37, 0x90, 0x80, 0xF7, 0xE0, 0x64, 0x01, 0x60,
0x02, 0xC1, 0x37, 0x90, 0x81, 0xEF, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90,
0x81, 0xA3, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xEC, 0x90, 0xFD, 0x11, 0xF0, 0x74, 0x02, 0x2D, 0xF5,
0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0x0F, 0x33, 0x33, 0x33, 0x54, 0xF8, 0xFC, 0x74,
0x07, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0x90, 0x81, 0xAB, 0xF0,
0xED, 0x24, 0x18, 0x2C, 0x90, 0x81, 0xA9, 0xF0, 0xE0, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0xFB,
0xF5, 0x83, 0xE0, 0x54, 0xFC, 0x90, 0x81, 0xAA, 0xF0, 0x74, 0x01, 0x2D, 0xF5, 0x82, 0xE4, 0x34,
0xFB, 0xF5, 0x83, 0xE0, 0xFE, 0x74, 0x00, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0,
0x7A, 0x00, 0x24, 0x00, 0xFF, 0xEA, 0x3E, 0x54, 0x3F, 0x90, 0x81, 0xA5, 0xF0, 0xA3, 0xEF, 0xF0,
0xAF, 0x04, 0xEF, 0x24, 0x18, 0xFF, 0xE4, 0x33, 0x90, 0x81, 0xA5, 0x8F, 0xF0, 0x12, 0x41, 0xF6,
0x90, 0x81, 0xA5, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x54, 0x7F, 0x60, 0x0B, 0xEF, 0x54, 0x80, 0x24,
0x80, 0xFF, 0xE4, 0x3E, 0xA3, 0x80, 0x0B, 0x90, 0x81, 0xA5, 0xE0, 0xFF, 0xA3, 0xE0, 0x54, 0x80,
0xA3, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x81, 0xA7, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90, 0x81,
0xA3, 0xEE, 0x8F, 0xF0, 0x12, 0x41, 0xF6, 0x90, 0x80, 0xF5, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x90,
0x81, 0xA3, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xD3, 0x9F, 0xEC, 0x9E, 0x40, 0x1B, 0x90, 0x80, 0xF6,
0xE0, 0x24, 0x01, 0xFF, 0x90, 0x80, 0xF5, 0xE0, 0x34, 0x00, 0xFE, 0xC3, 0xED, 0x9F, 0xFF, 0xEC,
0x9E, 0x90, 0x81, 0xA3, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x81, 0x72, 0xE0, 0x30, 0xE0, 0x09, 0x13,
0x13, 0x54, 0x3F, 0x20, 0xE0, 0x02, 0xC1, 0x2B, 0x90, 0x81, 0xAA, 0xE0, 0x24, 0xC0, 0x60, 0x02,
0xA1, 0x45, 0x90, 0x81, 0xA9, 0xE0, 0xFF, 0x24, 0x18, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83,
0xE0, 0x60, 0x02, 0xA1, 0x43, 0x74, 0x19, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0,
0xFE, 0x90, 0x81, 0xC3, 0xF0, 0x74, 0x1A, 0x2F, 0xF9, 0xE4, 0x34, 0xFB, 0xFA, 0x7B, 0x01, 0xA3,
0x12, 0x42, 0x53, 0xEE, 0x70, 0x02, 0x81, 0x59, 0xE4, 0x90, 0x81, 0xAD, 0xF0, 0x90, 0x80, 0xFE,
0xE0, 0xFF, 0x90, 0x81, 0xAD, 0xE0, 0xFE, 0xC3, 0x9F, 0x40, 0x02, 0x81, 0x41, 0x12, 0x6C, 0x82,
0x90, 0x81, 0xAD, 0xE0, 0xFF, 0x24, 0xAF, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0xFE,
0x90, 0x81, 0xC3, 0xE0, 0xFD, 0xEE, 0x6D, 0x70, 0x2C, 0xFC, 0xAE, 0x04, 0xC0, 0x05, 0xEF, 0x75,
0xF0, 0x03, 0xA4, 0x24, 0xB4, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x12, 0x42, 0x4A, 0xA8,
0x01, 0xAC, 0x02, 0xAD, 0x03, 0x90, 0x81, 0xC4, 0x12, 0x42, 0x4A, 0xD0, 0x07, 0x12, 0x44, 0x08,
0xEF, 0x70, 0x02, 0x80, 0x5B, 0x90, 0x81, 0xC3, 0xE0, 0x64, 0x03, 0x70, 0x6D, 0x78, 0x36, 0x7C,
0x82, 0x7D, 0x01, 0xA3, 0x12, 0x42, 0x4A, 0x7E, 0x00, 0x7F, 0x03, 0x12, 0x44, 0x08, 0xEF, 0x60,
0x16, 0x78, 0x32, 0x7C, 0x82, 0x7D, 0x01, 0x90, 0x81, 0xC4, 0x12, 0x42, 0x4A, 0x7E, 0x00, 0x7F,
0x03, 0x12, 0x44, 0x08, 0xEF, 0x70, 0x3B, 0x90, 0x81, 0xAD, 0xE0, 0xFF, 0x24, 0xE0, 0xF5, 0x82,
0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x60, 0x02, 0x80, 0x11, 0x90, 0x81, 0xAD, 0xE0, 0xFF, 0x24,
0xDB, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x60, 0x05, 0x74, 0xEF, 0x2F, 0x80, 0x20,
0x90, 0x81, 0xAD, 0xE0, 0x24, 0xEF, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x74, 0x01, 0xF0,
0x80, 0x17, 0x90, 0x81, 0xAD, 0xE0, 0x24, 0xEF, 0x80, 0x06, 0x90, 0x81, 0xAD, 0xE0, 0x24, 0xEF,
0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE4, 0xF0, 0x90, 0x81, 0xAD, 0xE0, 0x04, 0xF0, 0x61,
0x5D, 0x90, 0x81, 0xEF, 0xE0, 0x70, 0x6D, 0xA3, 0xE0, 0x70, 0x69, 0xA3, 0xE0, 0x70, 0x65, 0xA3,
0xE0, 0x70, 0x61, 0xA3, 0xE0, 0x70, 0x5D, 0xA1, 0x43, 0xE4, 0x90, 0x81, 0xAD, 0xF0, 0x90, 0x80,
0xFE, 0xE0, 0xFF, 0x90, 0x81, 0xAD, 0xE0, 0xFE, 0xC3, 0x9F, 0x50, 0x30, 0x74, 0xDB, 0x2E, 0xF5,
0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x60, 0x0E, 0x74, 0xEF, 0x2E, 0xF5, 0x82, 0xE4, 0x34,
0x81, 0xF5, 0x83, 0xE4, 0xF0, 0x80, 0x0D, 0x74, 0xEF, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5,
0x83, 0x74, 0x01, 0xF0, 0x90, 0x81, 0xAD, 0xE0, 0x04, 0xF0, 0x80, 0xC2, 0x90, 0x81, 0xEF, 0xE0,
0x70, 0x12, 0xA3, 0xE0, 0x70, 0x0E, 0xA3, 0xE0, 0x70, 0x0A, 0xA3, 0xE0, 0x70, 0x06, 0xA3, 0xE0,
0x70, 0x02, 0xA1, 0x43, 0xE4, 0x90, 0x81, 0xAD, 0xF0, 0x90, 0x80, 0xFE, 0xE0, 0xFF, 0x90, 0x81,
0xAD, 0xE0, 0xFE, 0xC3, 0x9F, 0x50, 0x7C, 0x12, 0x6C, 0x82, 0x90, 0x81, 0xAD, 0xE0, 0x24, 0xEF,
0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, 0x60, 0x61, 0x12, 0x6B, 0xEB, 0xEF, 0x64, 0x01,
0x70, 0x59, 0x90, 0x81, 0xAD, 0xE0, 0x24, 0xD6, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0,
0xFF, 0x7D, 0x01, 0x12, 0x6C, 0x19, 0x90, 0x81, 0xA5, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, 0x90,
0x81, 0xAC, 0xF0, 0x90, 0x81, 0xAC, 0xE0, 0xFF, 0x90, 0x81, 0xA9, 0xE0, 0x2F, 0x24, 0x0A, 0xF5,
0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0xFE, 0x90, 0x81, 0xA5, 0xA3, 0xE0, 0xFD, 0xEF, 0x2D,
0x24, 0x24, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xEE, 0xF0, 0x90, 0x81, 0xAC, 0xE0, 0x04,
0xF0, 0xE0, 0xB4, 0x06, 0xCE, 0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x90, 0x81, 0xAD, 0xE0, 0x04,
0xF0, 0x81, 0xB9, 0xC1, 0x2B, 0x90, 0x81, 0xAB, 0xE0, 0x60, 0x02, 0xC1, 0x2B, 0xE4, 0x90, 0x81,
0xAD, 0xF0, 0x90, 0x80, 0xFE, 0xE0, 0xFF, 0x90, 0x81, 0xAD, 0xE0, 0xFE, 0xC3, 0x9F, 0x50, 0x5F,
0x12, 0x6C, 0x82, 0xE4, 0x90, 0x81, 0xAC, 0xF0, 0x90, 0x81, 0xAD, 0xE0, 0x75, 0xF0, 0x03, 0xA4,
0x24, 0xC7, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x12, 0x42, 0x4A, 0x90, 0x81, 0xAC, 0xE0,
0xFF, 0xF5, 0x82, 0x75, 0x83, 0x00, 0x12, 0x1F, 0xBD, 0xFE, 0x90, 0x81, 0xA9, 0xE0, 0x2F, 0x24,
0x04, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x6E, 0x60, 0x11, 0x90, 0x81, 0xAD, 0xE0,
0x24, 0xEA, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE4, 0xF0, 0x80, 0x0A, 0x90, 0x81, 0xAC,
0xE0, 0x04, 0xF0, 0xE0, 0xB4, 0x06, 0xB1, 0x90, 0x81, 0xAD, 0xE0, 0x04, 0xF0, 0x80, 0x93, 0x90,
0x81, 0xEA, 0xE0, 0x64, 0x01, 0x60, 0x17, 0xA3, 0xE0, 0x64, 0x01, 0x60, 0x11, 0xA3, 0xE0, 0x64,
0x01, 0x60, 0x0B, 0xA3, 0xE0, 0x64, 0x01, 0x60, 0x05, 0xA3, 0xE0, 0xB4, 0x01, 0x06, 0x90, 0x81,
0xAE, 0x74, 0x01, 0xF0, 0x90, 0x81, 0xAE, 0xE0, 0xB4, 0x01, 0x08, 0x12, 0x56, 0x12, 0x12, 0x52,
0x15, 0x41, 0x01, 0xE4, 0x90, 0x81, 0xAE, 0xF0, 0x90, 0x81, 0xEA, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0,
0xA3, 0xF0, 0xA3, 0xF0, 0x90, 0x81, 0xAD, 0xF0, 0x90, 0x80, 0xFE, 0xE0, 0xFF, 0x90, 0x81, 0xAD,
0xE0, 0xFE, 0xC3, 0x9F, 0x50, 0x15, 0x74, 0xEA, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83,
0x74, 0x01, 0xF0, 0x90, 0x81, 0xAD, 0xE0, 0x04, 0xF0, 0x80, 0xDD, 0x90, 0x81, 0xA3, 0xE0, 0xFE,
0xA3, 0xE0, 0xFF, 0x11, 0x92, 0x41, 0x01, 0x22, 0x90, 0x82, 0x3A, 0x12, 0x42, 0x53, 0xE4, 0xFF,
0x90, 0x82, 0x40, 0xE0, 0xFE, 0xEF, 0xC3, 0x9E, 0x50, 0x26, 0x90, 0x82, 0x3D, 0x12, 0x42, 0x4A,
0x8F, 0x82, 0x75, 0x83, 0x00, 0x12, 0x1F, 0xBD, 0xFE, 0x90, 0x82, 0x3A, 0x12, 0x42, 0x4A, 0x8F,
0x82, 0x75, 0x83, 0x00, 0x12, 0x1F, 0xBD, 0x6E, 0x60, 0x03, 0x7F, 0x00, 0x22, 0x0F, 0x80, 0xD0,
0x7F, 0x01, 0x22, 0x90, 0x04, 0x24, 0xEF, 0xF0, 0x22, 0x90, 0x80, 0xFE, 0xE0, 0xFD, 0x7C, 0x00,
0xA3, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, 0x12, 0x20, 0x30, 0xED, 0x4C, 0x70, 0x05, 0x90, 0x81, 0x0B,
0x80, 0x2A, 0xED, 0x64, 0x01, 0x4C, 0x70, 0x05, 0x90, 0x81, 0x0C, 0x80, 0x1F, 0xED, 0x64, 0x02,
0x4C, 0x70, 0x05, 0x90, 0x81, 0x0D, 0x80, 0x14, 0xED, 0x64, 0x03, 0x4C, 0x70, 0x05, 0x90, 0x81,
0x0E, 0x80, 0x09, 0xED, 0x64, 0x04, 0x4C, 0x70, 0x11, 0x90, 0x81, 0x0F, 0xE0, 0xFF, 0xD1, 0x73,
0x90, 0x80, 0xFF, 0xE4, 0x75, 0xF0, 0x01, 0x12, 0x41, 0xF6, 0x22, 0x00, 0x5E, 0x83,
};
#endif // CONFIG_RTL_88E_SUPPORT
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS.c
Executable
+1933
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_S.c
Executable
+7206
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/Hal8188EFWImg_CE_PS_T.c
Executable
+7686
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/Hal8188ERateAdaptive.c
Executable
+1497
View File
File diff suppressed because it is too large Load Diff
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/Hal8188ERateAdaptive.h
Executable
+108
View File
@@ -0,0 +1,108 @@
#ifndef __INC_RA_H
#define __INC_RA_H
/*++
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
Module Name:
RateAdaptive.h
Abstract:
Prototype of RA and related data structure.
Major Change History:
When Who What
---------- --------------- -------------------------------
2011-08-12 Page Create.
--*/
// Rate adaptive define
#define PERENTRY 23
#define RETRYSIZE 5
#define RATESIZE 28
#define TX_RPT2_ITEM_SIZE 8
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
//
// TX report 2 format in Rx desc
//
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 9)
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+16, 0, 32)
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) LE_BITS_TO_4BYTE( __pAddr, 0, 16)
#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+2, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) LE_BITS_TO_1BYTE( __pAddr+3, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4, 0, 8)
#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+1, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+2, 0, 8)
#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) LE_BITS_TO_1BYTE( __pAddr+4+3, 0, 8)
#endif
// End rate adaptive define
VOID
ODM_RASupport_Init(
IN PDM_ODM_T pDM_Odm
);
int
ODM_RAInfo_Init_all(
IN PDM_ODM_T pDM_Odm
);
int
ODM_RAInfo_Init(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetShortGI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetDecisionRate_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
u1Byte
ODM_RA_GetHwPwrStatus_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID
);
VOID
ODM_RA_UpdateRateInfo_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte RateID,
IN u4Byte RateMask,
IN u1Byte SGIEnable
);
VOID
ODM_RA_SetRSSI_8188E(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
);
VOID
ODM_RA_TxRPT2Handle_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte TxRPT_Buf,
IN u2Byte TxRPT_Len,
IN u4Byte MacIDValidEntry0,
IN u4Byte MacIDValidEntry1
);
VOID
ODM_RA_Set_TxRPT_Time(
IN PDM_ODM_T pDM_Odm,
IN u2Byte minRptTime
);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/Hal8188EReg.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: Hal8188EReg.h
//
// Description:
//
// This file is for RTL8188E register definition.
//
//
//============================================================
#ifndef __HAL_8188E_REG_H__
#define __HAL_8188E_REG_H__
//
// Register Definition
//
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8188E 0xc50
//
// Bitmap Definition
//
#define BIT_FA_RESET_8188E BIT0
#define REG_ADAPTIVE_DATA_RATE_0 0x2B0
#define REG_DBI_WDATA_8188 0x0348 // DBI Write Data
#define REG_DBI_RDATA_8188 0x034C // DBI Read Data
#define REG_DBI_ADDR_8188 0x0350 // DBI Address
#define REG_DBI_FLAG_8188 0x0352 // DBI Read/Write Flag
#define REG_MDIO_WDATA_8188E 0x0354 // MDIO for Write PCIE PHY
#define REG_MDIO_RDATA_8188E 0x0356 // MDIO for Reads PCIE PHY
#define REG_MDIO_CTL_8188E 0x0358 // MDIO for Control
// [0-63]
#define REG_MACID_NO_LINK 0x484 // No Link register (bit[x] enabled means dropping packets for MACID in HW queue)
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalHWImg8188E_BB.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalHWImg8188E_BB.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8188E_H
#define __INC_MP_BB_HW_IMG_8188E_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_AGC_TAB(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_PHY_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_PHY_REG(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_PHY_REG_PG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalHWImg8188E_FW.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalHWImg8188E_FW.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_FW_8188E_HW_IMG_H
#define __INC_FW_8188E_HW_IMG_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
#ifdef CONFIG_POWER_SAVE
#define ArrayLength_8188E_FW_AP_T 16220
#define ArrayLength_8188E_FW_AP_S 22192
#elif defined(SDIO_AP_OFFLOAD)
#define ArrayLength_8188E_FW_AP 14062
#else
#define ArrayLength_8188E_FW_AP_T 16220
#define ArrayLength_8188E_FW_AP_S 22192
#endif
extern u1Byte Array_8188E_FW_AP_T[ArrayLength_8188E_FW_AP_T];
extern u1Byte Array_8188E_FW_AP_S[ArrayLength_8188E_FW_AP_S];
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
#if 0
#define ArrayLength_8188E_FW_NIC 14490
extern u1Byte Array_8188E_FW_NIC[ArrayLength_8188E_FW_NIC];
#endif
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
#if 0
#define ArrayLength_8188E_FW_WoWLAN 14702
extern u1Byte Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
#endif
#endif
#endif // end of HWIMG_SUPPORT
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalHWImg8188E_MAC.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
static BOOLEAN
CheckPositive(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2,
IN const u4Byte Condition3,
IN const u4Byte Condition4
)
{
u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/
u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4;
u4Byte driver1 = pDM_Odm->CutVersion << 24 |
(pDM_Odm->SupportInterface & 0xF0) << 16 |
pDM_Odm->SupportPlatform << 16 |
pDM_Odm->PackageType << 12 |
(pDM_Odm->SupportInterface & 0x0F) << 8 |
_BoardType;
u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 |
(pDM_Odm->TypeGPA & 0xFF) << 8 |
(pDM_Odm->TypeALNA & 0xFF) << 16 |
(pDM_Odm->TypeAPA & 0xFF) << 24;
u4Byte driver3 = 0;
u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 |
(pDM_Odm->TypeGPA & 0xFF00) |
(pDM_Odm->TypeALNA & 0xFF00) << 8 |
(pDM_Odm->TypeAPA & 0xFF00) << 16;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType));
/*============== Value Defined Check ===============*/
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return FALSE;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return FALSE;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u4Byte bitMask = 0;
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
return TRUE;
if ((cond1 & BIT0) != 0) /*GLNA*/
bitMask |= 0x000000FF;
if ((cond1 & BIT1) != 0) /*GPA*/
bitMask |= 0x0000FF00;
if ((cond1 & BIT2) != 0) /*ALNA*/
bitMask |= 0x00FF0000;
if ((cond1 & BIT3) != 0) /*APA*/
bitMask |= 0xFF000000;
if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/
return TRUE;
else
return FALSE;
} else
return FALSE;
}
static BOOLEAN
CheckNegative(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2
)
{
return TRUE;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u4Byte Array_MP_8188E_MAC_REG[] = {
0x026, 0x00000041,
0x027, 0x00000035,
0x80000003, 0x00000000, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0x90000001, 0x00000000, 0x40000000, 0x00000000,
0x040, 0x0000000C,
0xA0000000, 0x00000000,
0x040, 0x00000000,
0xB0000000, 0x00000000,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000001,
0x432, 0x00000002,
0x433, 0x00000004,
0x434, 0x00000005,
0x435, 0x00000006,
0x436, 0x00000007,
0x437, 0x00000008,
0x438, 0x00000000,
0x439, 0x00000000,
0x43A, 0x00000001,
0x43B, 0x00000002,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000006,
0x43F, 0x00000007,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000015,
0x445, 0x000000F0,
0x446, 0x0000000F,
0x447, 0x00000000,
0x458, 0x00000041,
0x459, 0x000000A8,
0x45A, 0x00000072,
0x45B, 0x000000B9,
0x460, 0x00000066,
0x461, 0x00000066,
0x480, 0x00000008,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4D3, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x63C, 0x00000008,
0x63D, 0x00000008,
0x63E, 0x0000000C,
0x63F, 0x0000000C,
0x640, 0x00000040,
0x652, 0x00000020,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
void
ODM_ReadAndConfig_MP_8188E_MAC_REG(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte i = 0;
u1Byte cCond;
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
u4Byte ArrayLen = sizeof(Array_MP_8188E_MAC_REG)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8188E_MAC_REG;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188E_MAC_REG\n"));
while ((i + 1) < ArrayLen) {
v1 = Array[i];
v2 = Array[i + 1];
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
if (v1 & BIT31) {/* positive condition*/
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
if (cCond == COND_ENDIF) {/*end*/
bMatched = TRUE;
bSkipped = FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (cCond == COND_ELSE) { /*else*/
bMatched = bSkipped?FALSE:TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
}
else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT30) { /*negative condition*/
if (bSkipped == FALSE) {
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
bMatched = TRUE;
bSkipped = TRUE;
} else {
bMatched = FALSE;
bSkipped = FALSE;
}
} else
bMatched = FALSE;
}
} else {
if (bMatched)
odm_ConfigMAC_8188E(pDM_Odm, v1, (u1Byte)v2);
}
i = i + 2;
}
}
u4Byte
ODM_GetVersion_MP_8188E_MAC_REG(void)
{
return 63;
}
#endif /* end of HWIMG_SUPPORT*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalHWImg8188E_MAC.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8188E_H
#define __INC_MP_MAC_HW_IMG_8188E_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_MAC_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_MAC_REG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalHWImg8188E_RF.c
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalHWImg8188E_RF.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8188E_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8188E_H
#define __INC_MP_RF_HW_IMG_8188E_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_RadioA(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_RadioA(void);
/******************************************************************************
* TxPowerTrack_AP.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_AP(void);
/******************************************************************************
* TxPowerTrack_PCIE.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_PCIE(void);
/******************************************************************************
* TxPowerTrack_SDIO.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_SDIO(void);
/******************************************************************************
* TxPowerTrack_USB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_TxPowerTrack_USB(void);
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_TXPWR_LMT(void);
/******************************************************************************
* TXPWR_LMT_88EE_M2_for_MSI.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8188E_TXPWR_LMT_88EE_M2_for_MSI(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalPhyRf_8188e_AP.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/HalPhyRf_8188e_AP.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8188E_H__
#define __HAL_PHY_RF_8188E_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_88E 10 //ms
#define index_mapping_NUM_88E 15
#define AVG_THERMAL_NUM_88E 4
#include "../HalPhyRf_AP.h"
void ConfigureTxpowerTrack_8188E(
PTXPWRTRACK_CFG pConfig
);
void DoIQK_8188E(
PVOID pDM_VOID,
u1Byte DeltaThermalIndex,
u1Byte ThermalValue,
u1Byte Threshold
);
VOID
ODM_TxPwrTrackSetPwr88E(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
);
//1 7. IQK
void
PHY_IQCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER Adapter,
#endif
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
//
// AP calibrate
//
void
PHY_APCalibrate_8188E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8188E( IN PADAPTER pAdapter);
VOID
_PHY_SaveADDARegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
VOID
_PHY_PathAStandBy(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/phydm_RTL8188E.c
Executable
+479
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@@ -0,0 +1,479 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
VOID
ODM_DIG_LowerBound_88E(
IN PDM_ODM_T pDM_Odm
)
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
pDM_DigTable->rx_gain_range_min = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_DIG_LowerBound_88E(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
}
//If only one Entry connected
}
/*=============================================================
* AntDiv Before Link
===============================================================*/
VOID
ODM_SwAntDivResetBeforeLink(
IN PDM_ODM_T pDM_Odm
)
{
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
pDM_SWAT_Table->SWAS_NoLink_State = 0;
}
//3============================================================
//3 Dynamic Primary CCA
//3============================================================
VOID
odm_PrimaryCCA_Init(
IN PDM_ODM_T pDM_Odm)
{
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->Monitor_flag = 0;
PrimaryCCA->PriCCA_flag = 0;
}
BOOLEAN
ODM_DynamicPrimaryCCA_DupRTS(
IN PDM_ODM_T pDM_Odm
)
{
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
return PrimaryCCA->DupRTS_flag;
}
VOID
odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm
)
{
#if(DM_ODM_SUPPORT_TYPE !=ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter; // for NIC
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
PRT_WLAN_STA pEntry;
#endif
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
BOOLEAN Is40MHz;
BOOLEAN Client_40MHz = FALSE, Client_tmp = FALSE; // connected client BW
BOOLEAN bConnected = FALSE; // connected or not
static u1Byte Client_40MHz_pre = 0;
static u8Byte lastTxOkCnt = 0;
static u8Byte lastRxOkCnt = 0;
static u4Byte Counter = 0;
static u1Byte Delay = 1;
u8Byte curTxOkCnt;
u8Byte curRxOkCnt;
u1Byte SecCHOffset;
u1Byte i;
if(!(pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA))
return;
if(pDM_Odm->SupportICType != ODM_RTL8188E)
return;
Is40MHz = *(pDM_Odm->pBandWidth);
SecCHOffset = *(pDM_Odm->pSecChOffset);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset));
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if(Is40MHz==1)
SecCHOffset = SecCHOffset%2+1; // NIC's definition is reverse to AP 1:secondary below, 2: secondary above
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Second CH Offset = %d\n", SecCHOffset));
//3 Check Current WLAN Traffic
curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
//3 Check Current WLAN Traffic
curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;
curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;
lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
#endif
//==================Debug Message====================
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("TP = %llu\n", curTxOkCnt+curRxOkCnt));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is40MHz = %d\n", Is40MHz));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_LSC = %d\n", FalseAlmCnt->Cnt_BW_LSC));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("BW_USC = %d\n", FalseAlmCnt->Cnt_BW_USC));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA OFDM = %d\n", FalseAlmCnt->Cnt_OFDM_CCA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCA CCK = %d\n", FalseAlmCnt->Cnt_CCK_CCA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("OFDM FA = %d\n", FalseAlmCnt->Cnt_Ofdm_fail));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("CCK FA = %d\n", FalseAlmCnt->Cnt_Cck_fail));
//================================================
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
if (ACTING_AS_AP(Adapter)) // primary cca process only do at AP mode
#endif
{
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("ACTING as AP mode=%d\n", ACTING_AS_AP(Adapter)));
//3 To get entry's connection and BW infomation status.
for(i=0;i<ASSOCIATE_ENTRY_NUM;i++)
{
if(IsAPModeExist(Adapter)&&GetFirstExtAdapter(Adapter)!=NULL)
pEntry=AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
else
pEntry=AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
if(pEntry!=NULL)
{
Client_tmp = pEntry->BandWidth; // client BW
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Client_BW=%d\n", Client_tmp));
if(Client_tmp>Client_40MHz)
Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High
if(pEntry->bAssociated)
{
bConnected=TRUE; // client is connected or not
break;
}
}
else
{
break;
}
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
//3 To get entry's connection and BW infomation status.
PSTA_INFO_T pstat;
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
{
pstat = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat) )
{
Client_tmp = pstat->tx_bw;
if(Client_tmp>Client_40MHz)
Client_40MHz = Client_tmp; // 40M/20M coexist => 40M priority is High
bConnected = TRUE;
}
}
#endif
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("bConnected=%d\n", bConnected));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Is Client 40MHz=%d\n", Client_40MHz));
//1 Monitor whether the interference exists or not
if(PrimaryCCA->Monitor_flag == 1)
{
if(SecCHOffset == 1) // secondary channel is below the primary channel
{
if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_LSC > FalseAlmCnt->Cnt_BW_USC+500))
{
if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
{
PrimaryCCA->intf_type = 1;
PrimaryCCA->PriCCA_flag = 1;
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2); // USC MF
if(PrimaryCCA->DupRTS_flag == 1)
PrimaryCCA->DupRTS_flag = 0;
}
else
{
PrimaryCCA->intf_type = 2;
if(PrimaryCCA->DupRTS_flag == 0)
PrimaryCCA->DupRTS_flag = 1;
}
}
else // interferecne disappear
{
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
}
}
else if(SecCHOffset == 2) // secondary channel is above the primary channel
{
if((FalseAlmCnt->Cnt_OFDM_CCA > 500)&&(FalseAlmCnt->Cnt_BW_USC > FalseAlmCnt->Cnt_BW_LSC+500))
{
if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
{
PrimaryCCA->intf_type = 1;
PrimaryCCA->PriCCA_flag = 1;
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1); // LSC MF
if(PrimaryCCA->DupRTS_flag == 1)
PrimaryCCA->DupRTS_flag = 0;
}
else
{
PrimaryCCA->intf_type = 2;
if(PrimaryCCA->DupRTS_flag == 0)
PrimaryCCA->DupRTS_flag = 1;
}
}
else // interferecne disappear
{
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
}
}
PrimaryCCA->Monitor_flag = 0;
}
//1 Dynamic Primary CCA Main Function
if(PrimaryCCA->Monitor_flag == 0)
{
if(Is40MHz) // if RFBW==40M mode which require to process primary cca
{
//2 STA is NOT Connected
if(!bConnected)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA NOT Connected!!!!\n"));
if(PrimaryCCA->PriCCA_flag == 1) // reset primary cca when STA is disconnected
{
PrimaryCCA->PriCCA_flag = 0;
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0);
}
if(PrimaryCCA->DupRTS_flag == 1) // reset Duplicate RTS when STA is disconnected
PrimaryCCA->DupRTS_flag = 0;
if(SecCHOffset == 1) // secondary channel is below the primary channel
{
if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9))
{
PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!!
if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
}
else
{
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
}
}
else if(SecCHOffset == 2) // secondary channel is above the primary channel
{
if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9))
{
PrimaryCCA->intf_flag = 1; // secondary channel interference is detected!!!
if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
}
else
{
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
}
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("PrimaryCCA=%d\n",PrimaryCCA->PriCCA_flag));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Intf_Type=%d\n", PrimaryCCA->intf_type));
}
//2 STA is Connected
else
{
if(Client_40MHz == 0) //3 // client BW = 20MHz
{
if(PrimaryCCA->PriCCA_flag == 0)
{
PrimaryCCA->PriCCA_flag = 1;
if(SecCHOffset==1)
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2);
else if(SecCHOffset==2)
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1);
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("STA Connected 20M!!! PrimaryCCA=%d\n", PrimaryCCA->PriCCA_flag));
}
else //3 // client BW = 40MHz
{
if(PrimaryCCA->intf_flag == 1) // interference is detected!!
{
if(PrimaryCCA->intf_type == 1)
{
if(PrimaryCCA->PriCCA_flag!=1)
{
PrimaryCCA->PriCCA_flag = 1;
if(SecCHOffset==1)
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 2);
else if(SecCHOffset==2)
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 1);
}
}
else if(PrimaryCCA->intf_type == 2)
{
if(PrimaryCCA->DupRTS_flag!=1)
PrimaryCCA->DupRTS_flag = 1;
}
}
else // if intf_flag==0
{
if((curTxOkCnt+curRxOkCnt)<10000) //idle mode or TP traffic is very low
{
if(SecCHOffset == 1)
{
if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_LSC*5 > FalseAlmCnt->Cnt_BW_USC*9))
{
PrimaryCCA->intf_flag = 1;
if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
}
}
else if(SecCHOffset == 2)
{
if((FalseAlmCnt->Cnt_OFDM_CCA > 800)&&(FalseAlmCnt->Cnt_BW_USC*5 > FalseAlmCnt->Cnt_BW_LSC*9))
{
PrimaryCCA->intf_flag = 1;
if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
}
}
}
else // TP Traffic is High
{
if(SecCHOffset == 1)
{
if(FalseAlmCnt->Cnt_BW_LSC > (FalseAlmCnt->Cnt_BW_USC+500))
{
if(Delay == 0) // add delay to avoid interference occurring abruptly, jump one time
{
PrimaryCCA->intf_flag = 1;
if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
Delay = 1;
}
else
Delay = 0;
}
}
else if(SecCHOffset == 2)
{
if(FalseAlmCnt->Cnt_BW_USC > (FalseAlmCnt->Cnt_BW_LSC+500))
{
if(Delay == 0) // add delay to avoid interference occurring abruptly
{
PrimaryCCA->intf_flag = 1;
if(FalseAlmCnt->Cnt_Ofdm_fail > FalseAlmCnt->Cnt_OFDM_CCA>>1)
PrimaryCCA->intf_type = 1; // interference is shift
else
PrimaryCCA->intf_type = 2; // interference is in-band
Delay = 1;
}
else
Delay = 0;
}
}
}
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Primary CCA=%d\n", PrimaryCCA->PriCCA_flag));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Duplicate RTS=%d\n", PrimaryCCA->DupRTS_flag));
}
}// end of connected
}
}
//1 Dynamic Primary CCA Monitor Counter
if((PrimaryCCA->PriCCA_flag == 1)||(PrimaryCCA->DupRTS_flag == 1))
{
if(Client_40MHz == 0) // client=20M no need to monitor primary cca flag
{
Client_40MHz_pre = Client_40MHz;
return;
}
Counter++;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("Counter=%d\n", Counter));
if((Counter == 30)||((Client_40MHz -Client_40MHz_pre)==1)) // Every 60 sec to monitor one time
{
PrimaryCCA->Monitor_flag = 1; // monitor flag is triggered!!!!!
if(PrimaryCCA->PriCCA_flag == 1)
{
PrimaryCCA->PriCCA_flag = 0;
ODM_SetBBReg(pDM_Odm, 0xc6c, BIT8|BIT7, 0);
}
Counter = 0;
}
}
}
Client_40MHz_pre = Client_40MHz;
#endif
}
#else //#if (RTL8188E_SUPPORT == 1)
VOID
odm_PrimaryCCA_Init(
IN PDM_ODM_T pDM_Odm)
{
}
VOID
odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm
)
{
}
BOOLEAN
ODM_DynamicPrimaryCCA_DupRTS(
IN PDM_ODM_T pDM_Odm
)
{
return FALSE;
}
#endif //#if (RTL8188E_SUPPORT == 1)
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/phydm_RTL8188E.h
Executable
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@@ -0,0 +1,69 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8188E_H__
#define __ODM_RTL8188E_H__
#define MAIN_ANT_CG_TRX 1
#define AUX_ANT_CG_TRX 0
#define MAIN_ANT_CGCS_RX 0
#define AUX_ANT_CGCS_RX 1
VOID
ODM_DIG_LowerBound_88E(
IN PDM_ODM_T pDM_Odm
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
#define SwAntDivResetBeforeLink ODM_SwAntDivResetBeforeLink
VOID ODM_SwAntDivResetBeforeLink(IN PDM_ODM_T pDM_Odm);
VOID
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo_88E(
IN PDM_ODM_T pDM_Odm
);
#endif
VOID
odm_PrimaryCCA_Init(
IN PDM_ODM_T pDM_Odm);
BOOLEAN
ODM_DynamicPrimaryCCA_DupRTS(
IN PDM_ODM_T pDM_Odm);
VOID
odm_DynamicPrimaryCCA(
IN PDM_ODM_T pDM_Odm);
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/phydm_RegConfig8188E.c
Executable
+245
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@@ -0,0 +1,245 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8188E_SUPPORT == 1)
void
odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#ifndef SMP_SYNC
unsigned long x;
#endif
struct rtl8192cd_priv *priv = pDM_Odm->priv;
#endif
if(Addr == 0xffe)
{
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else if (Addr == 0xfd)
{
ODM_delay_ms(5);
}
else if (Addr == 0xfc)
{
ODM_delay_ms(1);
}
else if (Addr == 0xfb)
{
ODM_delay_us(50);
}
else if (Addr == 0xfa)
{
ODM_delay_us(5);
}
else if (Addr == 0xf9)
{
ODM_delay_us(1);
}
else
{
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
SAVE_INT_AND_CLI(x);
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
RESTORE_INT(x);
#else
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
#endif
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
}
}
void
odm_ConfigRF_RadioA_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
}
void
odm_ConfigRF_RadioB_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8188E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
)
{
ODM_Write1Byte(pDM_Odm, Addr, Data);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_AGC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe){
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else if (Addr == 0xfd){
ODM_delay_ms(5);
}
else if (Addr == 0xfc){
ODM_delay_ms(1);
}
else if (Addr == 0xfb){
ODM_delay_us(50);
}
else if (Addr == 0xfa){
ODM_delay_us(5);
}
else if (Addr == 0xf9){
ODM_delay_us(1);
}
else {
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
#endif
}
}
void
odm_ConfigBB_TXPWR_LMT_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte Regulation,
IN pu1Byte Band,
IN pu1Byte Bandwidth,
IN pu1Byte RateSection,
IN pu1Byte RfPath,
IN pu1Byte Channel,
IN pu1Byte PowerLimit
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
Bandwidth, RateSection, RfPath, Channel, PowerLimit);
#endif
}
void
odm_ConfigBB_PHY_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe){
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else if (Addr == 0xfd){
ODM_delay_ms(5);
}
else if (Addr == 0xfc){
ODM_delay_ms(1);
}
else if (Addr == 0xfb){
ODM_delay_us(50);
}
else if (Addr == 0xfa){
ODM_delay_us(5);
}
else if (Addr == 0xf9){
ODM_delay_us(1);
}
else {
if (Addr == 0xa24)
pDM_Odm->RFCalibrateInfo.RegA24 = Data;
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/phydm_RegConfig8188E.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8188E
#define __INC_ODM_REGCONFIG_H_8188E
#if (RTL8188E_SUPPORT == 1)
void
odm_ConfigRFReg_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
);
void
odm_ConfigRF_RadioA_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigRF_RadioB_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigMAC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
);
void
odm_ConfigBB_AGC_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_REG_PG_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_8188E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_TXPWR_LMT_8188E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte Regulation,
IN pu1Byte Band,
IN pu1Byte Bandwidth,
IN pu1Byte RateSection,
IN pu1Byte RfPath,
IN pu1Byte Channel,
IN pu1Byte PowerLimit
);
#endif
#endif // end of SUPPORT
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8188e/version_rtl8188e.h
Executable
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/*RTL8188E PHY Parameters*/
#define SVN_COMMIT_VERSION_8188E 65
#define RELEASE_DATE_8188E 20150610
#define COMMIT_BY_8188E "BB_LUKE"
#define RELEASE_VERSION_8188E 63
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/Hal8192EReg.h
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_BB.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_BB.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8192E_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8192E_H
#define __INC_MP_BB_HW_IMG_8192E_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_AGC_TAB(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_PHY_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_PHY_REG(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_PHY_REG_PG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_FW.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_FW.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8192E_SUPPORT == 1)
#ifndef __INC_MP_FW_HW_IMG_8192E_H
#define __INC_MP_FW_HW_IMG_8192E_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8192E_FW_AP(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
/******************************************************************************
* FW_AP_PCIE.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8192E_FW_AP_PCIE(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8192E_FW_NIC(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8192E_FW_WoWLAN(
IN PDM_ODM_T pDM_Odm,
OUT u1Byte *pFirmware,
OUT u4Byte *pFirmwareSize
);
#endif
#endif // end of HWIMG_SUPPORT
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_MAC.c
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8192E_SUPPORT == 1)
static BOOLEAN
CheckPositive(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2,
IN const u4Byte Condition3,
IN const u4Byte Condition4
)
{
u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/
((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/
((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/
((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */
((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/
u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4;
u4Byte driver1 = pDM_Odm->CutVersion << 24 |
(pDM_Odm->SupportInterface & 0xF0) << 16 |
pDM_Odm->SupportPlatform << 16 |
pDM_Odm->PackageType << 12 |
(pDM_Odm->SupportInterface & 0x0F) << 8 |
_BoardType;
u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 |
(pDM_Odm->TypeGPA & 0xFF) << 8 |
(pDM_Odm->TypeALNA & 0xFF) << 16 |
(pDM_Odm->TypeAPA & 0xFF) << 24;
u4Byte driver3 = 0;
u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 |
(pDM_Odm->TypeGPA & 0xFF00) |
(pDM_Odm->TypeALNA & 0xFF00) << 8 |
(pDM_Odm->TypeAPA & 0xFF00) << 16;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType));
/*============== Value Defined Check ===============*/
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return FALSE;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return FALSE;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u4Byte bitMask = 0;
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
return TRUE;
if ((cond1 & BIT0) != 0) /*GLNA*/
bitMask |= 0x000000FF;
if ((cond1 & BIT1) != 0) /*GPA*/
bitMask |= 0x0000FF00;
if ((cond1 & BIT2) != 0) /*ALNA*/
bitMask |= 0x00FF0000;
if ((cond1 & BIT3) != 0) /*APA*/
bitMask |= 0xFF000000;
if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/
return TRUE;
else
return FALSE;
} else
return FALSE;
}
static BOOLEAN
CheckNegative(
IN PDM_ODM_T pDM_Odm,
IN const u4Byte Condition1,
IN const u4Byte Condition2
)
{
return TRUE;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u4Byte Array_MP_8192E_MAC_REG[] = {
0x011, 0x000000EB,
0x012, 0x00000007,
0x014, 0x00000075,
0x303, 0x000000A7,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x00000000,
0x446, 0x00000000,
0x447, 0x00000000,
0x448, 0x00000000,
0x449, 0x000000F0,
0x44A, 0x0000000F,
0x44B, 0x0000003E,
0x44C, 0x00000010,
0x44D, 0x00000000,
0x44E, 0x00000000,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x000000F0,
0x452, 0x0000000F,
0x453, 0x00000000,
0x456, 0x0000005E,
0x460, 0x00000066,
0x461, 0x00000066,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x540, 0x00000012,
0x541, 0x00000064,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000050,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000050,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x0000002B,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
};
void
ODM_ReadAndConfig_MP_8192E_MAC_REG(
IN PDM_ODM_T pDM_Odm
)
{
u4Byte i = 0;
u1Byte cCond;
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
u4Byte ArrayLen = sizeof(Array_MP_8192E_MAC_REG)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8192E_MAC_REG;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8192E_MAC_REG\n"));
while ((i + 1) < ArrayLen) {
v1 = Array[i];
v2 = Array[i + 1];
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
if (v1 & BIT31) {/* positive condition*/
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
if (cCond == COND_ENDIF) {/*end*/
bMatched = TRUE;
bSkipped = FALSE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (cCond == COND_ELSE) { /*else*/
bMatched = bSkipped?FALSE:TRUE;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
}
else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT30) { /*negative condition*/
if (bSkipped == FALSE) {
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
bMatched = TRUE;
bSkipped = TRUE;
} else {
bMatched = FALSE;
bSkipped = FALSE;
}
} else
bMatched = FALSE;
}
} else {
if (bMatched)
odm_ConfigMAC_8192E(pDM_Odm, v1, (u1Byte)v2);
}
i = i + 2;
}
}
u4Byte
ODM_GetVersion_MP_8192E_MAC_REG(void)
{
return 51;
}
#endif /* end of HWIMG_SUPPORT*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_MAC.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8192E_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8192E_H
#define __INC_MP_MAC_HW_IMG_8192E_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_MAC_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_MAC_REG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_RF.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalHWImg8192E_RF.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.14*/
#if (RTL8192E_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8192E_H
#define __INC_MP_RF_HW_IMG_8192E_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_RadioA(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_RadioA(void);
/******************************************************************************
* RadioB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_RadioB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_RadioB(void);
/******************************************************************************
* TxPowerTrack_AP.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_AP(void);
/******************************************************************************
* TxPowerTrack_PCIE.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TxPowerTrack_PCIE(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_PCIE(void);
/******************************************************************************
* TxPowerTrack_SDIO.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_SDIO(void);
/******************************************************************************
* TxPowerTrack_USB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TxPowerTrack_USB(void);
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TXPWR_LMT(void);
/******************************************************************************
* TXPWR_LMT_8192E_SAR_5mm.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8192E_TXPWR_LMT_8192E_SAR_5mm(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8192E_TXPWR_LMT_8192E_SAR_5mm(void);
#endif
#endif /* end of HWIMG_SUPPORT*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalPhyRf_8192e_AP.c
Executable
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wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/HalPhyRf_8192e_AP.h
Executable
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8192E_H__
#define __HAL_PHY_RF_8192E_H__
/*--------------------------Define Parameters-------------------------------*/
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
#define IQK_DELAY_TIME_92E 15 //ms
#else
#define IQK_DELAY_TIME_92E 10
#endif
#define index_mapping_NUM_92E 15
#define AVG_THERMAL_NUM_92E 4
#define RF_T_METER_92E 0x42
#include "../HalPhyRf_AP.h"
void ConfigureTxpowerTrack_8192E(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8192E(
IN PVOID pDM_VOID,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
);
void DoIQK_8192E(
PVOID pDM_VOID,
u1Byte DeltaThermalIndex,
u1Byte ThermalValue,
u1Byte Threshold
);
VOID
ODM_TxPwrTrackSetPwr92E(
IN PVOID pDM_VOID,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
);
//1 7. IQK
void
PHY_IQCalibrate_8192E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER Adapter,
#endif
IN BOOLEAN bReCovery);
//
// LC calibrate
//
void
PHY_LCCalibrate_8192E(
IN PVOID pDM_VOID
);
//
// AP calibrate
//
void
PHY_APCalibrate_8192E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8192E(IN PADAPTER pAdapter);
VOID
_PHY_SaveADDARegisters_92E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn_92E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration_92E(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
VOID
_PHY_PathAStandBy(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif /* #ifndef __HAL_PHY_RF_8192E_H__*/
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/phydm_RTL8192E.c
Executable
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@@ -0,0 +1,455 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8192E_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_Write_Dynamic_CCA(
IN PDM_ODM_T pDM_Odm,
IN u1Byte CurrentMFstate
)
{
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
if (PrimaryCCA->MF_state != CurrentMFstate){
ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, CurrentMFstate);
}
PrimaryCCA->MF_state = CurrentMFstate;
}
VOID
odm_PrimaryCCA_Check_Init(
IN PDM_ODM_T pDM_Odm)
{
#if((DM_ODM_SUPPORT_TYPE==ODM_WIN) ||(DM_ODM_SUPPORT_TYPE==ODM_AP))
PADAPTER pAdapter = pDM_Odm->Adapter;
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->Monitor_flag = 0;
PrimaryCCA->PriCCA_flag = 0;
PrimaryCCA->CH_offset = 0;
PrimaryCCA->MF_state = 0;
#endif
}
VOID
odm_DynamicPrimaryCCA_Check(
IN PDM_ODM_T pDM_Odm
)
{
if(pDM_Odm->SupportICType != ODM_RTL8192E)
return;
if(!(pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA))
return;
switch (pDM_Odm->SupportPlatform)
{
case ODM_WIN:
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
odm_DynamicPrimaryCCAMP(pDM_Odm);
#endif
break;
case ODM_CE:
#if(DM_ODM_SUPPORT_TYPE==ODM_CE)
#endif
break;
case ODM_AP:
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_DynamicPrimaryCCAAP(pDM_Odm);
#endif
break;
}
}
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_DynamicPrimaryCCAMP(
IN PDM_ODM_T pDM_Odm
)
{
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
#else
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
#endif
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
BOOLEAN Is40MHz = FALSE;
u8Byte OFDM_CCA, OFDM_FA, BW_USC_Cnt, BW_LSC_Cnt;
u1Byte SecCHOffset;
u1Byte CurMFstate;
static u1Byte CountDown = Monitor_TIME;
OFDM_CCA = FalseAlmCnt->Cnt_OFDM_CCA;
OFDM_FA = FalseAlmCnt->Cnt_Ofdm_fail;
BW_USC_Cnt = FalseAlmCnt->Cnt_BW_USC;
BW_LSC_Cnt = FalseAlmCnt->Cnt_BW_LSC;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: OFDM CCA=%d\n", OFDM_CCA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: OFDM FA=%d\n", OFDM_FA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: BW_USC=%d\n", BW_USC_Cnt));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: BW_LSC=%d\n", BW_LSC_Cnt));
Is40MHz = *(pDM_Odm->pBandWidth);
SecCHOffset = *(pDM_Odm->pSecChOffset); // NIC: 2: sec is below, 1: sec is above
//DbgPrint("92E: SecCHOffset = %d\n", SecCHOffset);
if(IsAPModeExist(pAdapter)){
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
return;
}
if(!pDM_Odm->bLinked){
return;
}
else{
if(Is40MHz){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Cont Down= %d\n", CountDown));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Primary_CCA_flag=%d\n", PrimaryCCA->PriCCA_flag));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Intf_Type=%d\n", PrimaryCCA->intf_type));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Intf_flag=%d\n", PrimaryCCA->intf_flag ));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("92E: Duplicate RTS Flag=%d\n", PrimaryCCA->DupRTS_flag));
//DbgPrint("92E RTS_EN=%d\n", pHalData->RTSEN);
if(PrimaryCCA->PriCCA_flag == 0){
if(SecCHOffset == 2){ // Primary channel is above NOTE: duplicate CTS can remove this condition
if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias))
&& (OFDM_FA>(OFDM_CCA>>1))){
PrimaryCCA->intf_type = 1;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
}
else if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias))
&& (OFDM_FA < (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 2;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
PrimaryCCA->DupRTS_flag = 1;
pHalData->RTSEN = 1;
}
else{
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
}
}
else if (SecCHOffset == 1){
if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt > (BW_LSC_Cnt + BW_Ind_Bias))
&& (OFDM_FA > (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 1;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
}
else if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt>(BW_LSC_Cnt + BW_Ind_Bias))
&& (OFDM_FA < (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 2;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
PrimaryCCA->DupRTS_flag = 1;
pHalData->RTSEN = 1;
}
else{
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
}
}
}
else{ // PrimaryCCA->PriCCA_flag==1
CountDown--;
if(CountDown == 0){
CountDown = Monitor_TIME;
PrimaryCCA->PriCCA_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); // default
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
}
}
}
else{
return;
}
}
}
#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
odm_DynamicPrimaryCCAAP(
IN PDM_ODM_T pDM_Odm
)
{
PADAPTER Adapter = pDM_Odm->Adapter;
prtl8192cd_priv priv = pDM_Odm->priv;
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
#else
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
#endif
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte i;
static u4Byte Count_Down = Monitor_TIME;
BOOLEAN STA_BW = FALSE, STA_BW_pre = FALSE, STA_BW_TMP = FALSE;
BOOLEAN bConnected = FALSE;
BOOLEAN Is40MHz = FALSE;
u1Byte SecCHOffset;
u1Byte CurMFstate;
PSTA_INFO_T pstat;
Is40MHz = *(pDM_Odm->pBandWidth);
SecCHOffset = *(pDM_Odm->pSecChOffset); // AP: 1: sec is below, 2: sec is above
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
pstat = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat)){
STA_BW_TMP = pstat->tx_bw;
if(STA_BW_TMP > STA_BW){
STA_BW = STA_BW_TMP;
}
bConnected = TRUE;
}
}
if(Is40MHz){
if(PrimaryCCA->PriCCA_flag == 0){
if(bConnected){
if(STA_BW == 0){ //2 STA BW=20M
PrimaryCCA->PriCCA_flag = 1;
if(SecCHOffset==1){
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
}
else if(SecCHOffset==2){
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
}
}
else{ //2 STA BW=40M
if(PrimaryCCA->intf_flag == 0){
odm_Intf_Detection(pDM_Odm);
}
else{ // intf_flag = 1
if(PrimaryCCA->intf_type == 1){
if(PrimaryCCA->CH_offset == 1){
CurMFstate = MF_USC;
if(SecCHOffset == 1){ // AP, 1: primary is above 2: primary is below
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
}
}
else if(PrimaryCCA->CH_offset == 2){
CurMFstate = MF_LSC;
if(SecCHOffset == 2){
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
}
}
}
else if(PrimaryCCA->intf_type==2){
if(PrimaryCCA->CH_offset==1){
//ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_USC);
pHalData->RTSEN = 1;
}
else if(PrimaryCCA->CH_offset==2){
//ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_LSC);
pHalData->RTSEN = 1;
}
}
}
}
}
else{ // disconnected interference detection
odm_Intf_Detection(pDM_Odm);
}// end of disconnected
}
else{ // PrimaryCCA->PriCCA_flag == 1
if(STA_BW==0){
STA_BW_pre = STA_BW;
return;
}
Count_Down--;
if((Count_Down == 0) || ((STA_BW & STA_BW_pre) != 1)){
Count_Down = Monitor_TIME;
PrimaryCCA->PriCCA_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate); // default
pHalData->RTSEN = 0;
}
}
STA_BW_pre = STA_BW;
}
else{
//2 Reset
odm_PrimaryCCA_Check_Init(pDM_Odm);
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA(pDM_Odm, CurMFstate);
Count_Down = Monitor_TIME;
}
}
VOID
odm_Intf_Detection(
IN PDM_ODM_T pDM_Odm
)
{
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT);
#else
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
#endif
pPri_CCA_T PrimaryCCA = &(pDM_Odm->DM_PriCCA);
if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH)
&&(FalseAlmCnt->Cnt_BW_LSC>(FalseAlmCnt->Cnt_BW_USC+BW_Ind_Bias))){
PrimaryCCA->intf_flag = 1;
PrimaryCCA->CH_offset = 1; // 1:LSC, 2:USC
if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){
PrimaryCCA->intf_type = 1;
}
else{
PrimaryCCA->intf_type = 2;
}
}
else if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH)
&&(FalseAlmCnt->Cnt_BW_USC>(FalseAlmCnt->Cnt_BW_LSC+BW_Ind_Bias))){
PrimaryCCA->intf_flag = 1;
PrimaryCCA->CH_offset = 2; // 1:LSC, 2:USC
if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){
PrimaryCCA->intf_type = 1;
}
else{
PrimaryCCA->intf_type = 2;
}
}
else{
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->CH_offset = 0;
}
}
#endif
#endif
#endif // RTL8192E_SUPPORT == 1
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/phydm_RTL8192E.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8192E_H__
#define __ODM_RTL8192E_H__
#define OFDMCCA_TH 500
#define BW_Ind_Bias 500
#define MF_USC 2
#define MF_LSC 1
#define MF_USC_LSC 0
#define Monitor_TIME 30
VOID
odm_Write_Dynamic_CCA(
IN PDM_ODM_T pDM_Odm,
IN u1Byte CurrentMFstate
);
VOID
odm_PrimaryCCA_Check_Init(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_DynamicPrimaryCCA_Check(
IN PDM_ODM_T pDM_Odm
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_DynamicPrimaryCCAMP(
IN PDM_ODM_T pDM_Odm
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
odm_DynamicPrimaryCCAAP(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_Intf_Detection(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/phydm_RegConfig8192E.c
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Mp_Precomp.h"
#include "../phydm_precomp.h"
#if (RTL8192E_SUPPORT == 1)
void
odm_ConfigRFReg_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
)
{
if(Addr == 0xfe || Addr == 0xffe)
{
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else
{
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
//For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by Ed 20130.
if(Addr == 0xb6)
{
u4Byte getvalue=0;
u1Byte count =0;
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_delay_us(1);
while((getvalue>>8)!=(Data>>8))
{
count++;
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
ODM_delay_us(1);
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
if(count>5)
break;
}
}
if(Addr == 0xb2)
{
u4Byte getvalue=0;
u1Byte count =0;
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_delay_us(1);
while(getvalue!=Data)
{
count++;
ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
ODM_delay_us(1);
//Do LCK againg
ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07);
ODM_delay_us(1);
getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count));
if(count>5)
break;
}
}
}
}
void
odm_ConfigRF_RadioA_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
}
void
odm_ConfigRF_RadioB_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8192E(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigMAC_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
)
{
ODM_Write1Byte(pDM_Odm, Addr, Data);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_AGC_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_PHY_REG_PG_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe || Addr == 0xffe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else
{
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
#endif
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
}
void
odm_ConfigBB_PHY_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
)
{
if (Addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (Addr == 0xfd)
ODM_delay_ms(5);
else if (Addr == 0xfc)
ODM_delay_ms(1);
else if (Addr == 0xfb)
ODM_delay_us(50);
else if (Addr == 0xfa)
ODM_delay_us(5);
else if (Addr == 0xf9)
ODM_delay_us(1);
else
{
ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
}
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_TXPWR_LMT_8192E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte Regulation,
IN pu1Byte Band,
IN pu1Byte Bandwidth,
IN pu1Byte RateSection,
IN pu1Byte RfPath,
IN pu1Byte Channel,
IN pu1Byte PowerLimit
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band,
Bandwidth, RateSection, RfPath, Channel, PowerLimit);
#endif
}
#endif
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/phydm_RegConfig8192E.h
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8192E
#define __INC_ODM_REGCONFIG_H_8192E
#if (RTL8192E_SUPPORT == 1)
void
odm_ConfigRFReg_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
);
void
odm_ConfigRF_RadioA_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigRF_RadioB_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigMAC_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
);
void
odm_ConfigBB_AGC_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_REG_PG_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_8192E(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_TXPWR_LMT_8192E(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte Regulation,
IN pu1Byte Band,
IN pu1Byte Bandwidth,
IN pu1Byte RateSection,
IN pu1Byte RfPath,
IN pu1Byte Channel,
IN pu1Byte PowerLimit
);
#endif
#endif // end of SUPPORT
wlan/8192es/DriverSrcPkg/Driver/rtl8192cd_92es/OUTSRC/rtl8192e/version_rtl8192e.h
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/*RTL8192E PHY Parameters*/
#define SVN_COMMIT_VERSION_8192E 53
#define RELEASE_DATE_8192E 20150617
#define COMMIT_BY_8192E "BB_DINO"
#define RELEASE_VERSION_8192E 51