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M7350v3_en_gpl

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T
2024-09-09 08:55:19 +00:00
parent 801e6d2ad8
commit 2d95e8761a
2791 changed files with 89608 additions and 390711 deletions
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23
kernel/drivers/gpu/msm/adreno.c
View File

@ -822,7 +822,9 @@ static void adreno_iommu_setstate(struct kgsl_device *device,
uint32_t flags)
{
phys_addr_t pt_val;
unsigned int *link = NULL, *cmds;
unsigned int link[230];
unsigned int *cmds = &link[0];
int sizedwords = 0;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
int num_iommu_units;
struct kgsl_context *context;
@ -846,12 +848,6 @@ static void adreno_iommu_setstate(struct kgsl_device *device,
adreno_ctx = context->devctxt;
link = kmalloc(PAGE_SIZE, GFP_KERNEL);
if (link == NULL)
goto done;
cmds = link;
if (kgsl_mmu_enable_clk(&device->mmu,
KGSL_IOMMU_CONTEXT_USER))
return;
@ -870,11 +866,17 @@ static void adreno_iommu_setstate(struct kgsl_device *device,
cmds += _adreno_iommu_setstate_v1(device, cmds, pt_val,
num_iommu_units, flags);
sizedwords += (cmds - &link[0]);
if (sizedwords == 0) {
KGSL_DRV_ERR(device, "no commands generated\n");
BUG();
}
/* invalidate all base pointers */
*cmds++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
*cmds++ = 0x7fff;
sizedwords += 2;
if ((unsigned int) (cmds - link) > (PAGE_SIZE / sizeof(unsigned int))) {
if (sizedwords > (ARRAY_SIZE(link))) {
KGSL_DRV_ERR(device, "Temp command buffer overflow\n");
BUG();
}
@ -882,15 +884,12 @@ static void adreno_iommu_setstate(struct kgsl_device *device,
* This returns the per context timestamp but we need to
* use the global timestamp for iommu clock disablement
*/
adreno_ringbuffer_issuecmds(device, adreno_ctx, KGSL_CMD_FLAGS_PMODE,
link, (unsigned int) (cmds - link));
&link[0], sizedwords);
kgsl_mmu_disable_clk_on_ts(&device->mmu,
rb->timestamp[KGSL_MEMSTORE_GLOBAL], true);
done:
kfree(link);
kgsl_context_put(context);
}

45
kernel/drivers/gpu/msm/adreno.h
View File

@ -19,8 +19,6 @@
#include "kgsl_iommu.h"
#include <mach/ocmem.h>
#include "a3xx_reg.h"
#define DEVICE_3D_NAME "kgsl-3d"
#define DEVICE_3D0_NAME "kgsl-3d0"
@ -508,11 +506,6 @@ static inline int adreno_add_read_cmds(struct kgsl_device *device,
*cmds++ = val;
*cmds++ = 0xFFFFFFFF;
*cmds++ = 0xFFFFFFFF;
/* WAIT_REG_MEM turns back on protected mode - push it off */
*cmds++ = cp_type3_packet(CP_SET_PROTECTED_MODE, 1);
*cmds++ = 0;
cmds += __adreno_add_idle_indirect_cmds(cmds, nop_gpuaddr);
return cmds - start;
}
@ -561,42 +554,4 @@ static inline int adreno_wait_reg_eq(unsigned int *cmds, unsigned int addr,
return cmds - start;
}
/*
* adreno_set_protected_registers() - Protect the specified range of registers
* from being accessed by the GPU
* @device: pointer to the KGSL device
* @index: Pointer to the index of the protect mode register to write to
* @reg: Starting dword register to write
* @mask_len: Size of the mask to protect (# of registers = 2 ** mask_len)
*
* Add the range of registers to the list of protected mode registers that will
* cause an exception if the GPU accesses them. There are 16 available
* protected mode registers. Index is used to specify which register to write
* to - the intent is to call this function multiple times with the same index
* pointer for each range and the registers will be magically programmed in
* incremental fashion
*/
static inline void adreno_set_protected_registers(struct kgsl_device *device,
unsigned int *index, unsigned int reg, int mask_len)
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
unsigned int val;
/* This function is only for adreno A3XX and beyond */
BUG_ON(adreno_is_a2xx(adreno_dev));
/* There are only 16 registers available */
BUG_ON(*index >= 16);
val = 0x60000000 | ((mask_len & 0x1F) << 24) | ((reg << 2) & 0x1FFFF);
/*
* Write the protection range to the next available protection
* register
*/
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_0 + *index, val);
*index = *index + 1;
}
#endif /*__ADRENO_H */

59
kernel/drivers/gpu/msm/adreno_a3xx.c
View File

@ -2526,8 +2526,8 @@ static int a3xx_rb_init(struct adreno_device *adreno_dev,
GSL_RB_WRITE(rb->device, cmds, cmds_gpu, 0x00000001);
GSL_RB_WRITE(rb->device, cmds, cmds_gpu, 0x00000000);
GSL_RB_WRITE(rb->device, cmds, cmds_gpu, 0x00000000);
/* Enable protected mode */
GSL_RB_WRITE(rb->device, cmds, cmds_gpu, 0x20000000);
/* Protected mode control - turned off for A3XX */
GSL_RB_WRITE(rb->device, cmds, cmds_gpu, 0x00000000);
GSL_RB_WRITE(rb->device, cmds, cmds_gpu, 0x00000000);
GSL_RB_WRITE(rb->device, cmds, cmds_gpu, 0x00000000);
@ -2589,16 +2589,9 @@ static void a3xx_err_callback(struct adreno_device *adreno_dev, int bit)
case A3XX_INT_CP_HW_FAULT:
err = "ringbuffer hardware fault";
break;
case A3XX_INT_CP_REG_PROTECT_FAULT: {
unsigned int reg;
kgsl_regread(device, A3XX_CP_PROTECT_STATUS, &reg);
KGSL_DRV_CRIT(device,
"CP | Protected mode error| %s | addr=%x\n",
reg & (1 << 24) ? "WRITE" : "READ",
(reg & 0x1FFFF) >> 2);
return;
}
case A3XX_INT_CP_REG_PROTECT_FAULT:
err = "ringbuffer protected mode error interrupt";
break;
case A3XX_INT_CP_AHB_ERROR_HALT:
err = "ringbuffer AHB error interrupt";
break;
@ -3171,46 +3164,6 @@ static void a3xx_perfcounter_init(struct adreno_device *adreno_dev)
NULL, PERFCOUNTER_FLAG_KERNEL);
}
/**
* a3xx_protect_init() - Initializes register protection on a3xx
* @device: Pointer to the device structure
* Performs register writes to enable protected access to sensitive
* registers
*/
static void a3xx_protect_init(struct kgsl_device *device)
{
int index = 0;
/* enable access protection to privileged registers */
kgsl_regwrite(device, A3XX_CP_PROTECT_CTRL, 0x00000007);
/* RBBM registers */
adreno_set_protected_registers(device, &index, 0x18, 0);
adreno_set_protected_registers(device, &index, 0x20, 2);
adreno_set_protected_registers(device, &index, 0x33, 0);
adreno_set_protected_registers(device, &index, 0x42, 0);
adreno_set_protected_registers(device, &index, 0x50, 4);
adreno_set_protected_registers(device, &index, 0x63, 0);
adreno_set_protected_registers(device, &index, 0x100, 4);
/* CP registers */
adreno_set_protected_registers(device, &index, 0x1C0, 5);
adreno_set_protected_registers(device, &index, 0x1EC, 1);
adreno_set_protected_registers(device, &index, 0x1F6, 1);
adreno_set_protected_registers(device, &index, 0x1F8, 2);
adreno_set_protected_registers(device, &index, 0x45E, 2);
adreno_set_protected_registers(device, &index, 0x460, 4);
/* RB registers */
adreno_set_protected_registers(device, &index, 0xCC0, 0);
/* VBIF registers */
adreno_set_protected_registers(device, &index, 0x3000, 6);
/* SMMU registers */
adreno_set_protected_registers(device, &index, 0x4000, 14);
}
static void a3xx_start(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = &adreno_dev->dev;
@ -3275,8 +3228,6 @@ static void a3xx_start(struct adreno_device *adreno_dev)
adreno_regwrite(device, A3XX_RB_GMEM_BASE_ADDR,
(unsigned int)(adreno_dev->ocmem_base >> 14));
}
/* Turn on protection */
a3xx_protect_init(device);
/* Turn on performance counters */
adreno_regwrite(device, A3XX_RBBM_PERFCTR_CTL, 0x01);

26
kernel/drivers/gpu/msm/adreno_ringbuffer.c
View File

@ -407,6 +407,32 @@ int _ringbuffer_start_common(struct adreno_ringbuffer *rb)
rb->memptrs_desc.gpuaddr +
GSL_RB_MEMPTRS_RPTR_OFFSET);
if (adreno_is_a3xx(adreno_dev)) {
/* enable access protection to privileged registers */
adreno_regwrite(device, A3XX_CP_PROTECT_CTRL, 0x00000007);
/* RBBM registers */
adreno_regwrite(device, A3XX_CP_PROTECT_REG_0, 0x63000040);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_1, 0x62000080);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_2, 0x600000CC);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_3, 0x60000108);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_4, 0x64000140);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_5, 0x66000400);
/* CP registers */
adreno_regwrite(device, A3XX_CP_PROTECT_REG_6, 0x65000700);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_7, 0x610007D8);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_8, 0x620007E0);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_9, 0x61001178);
adreno_regwrite(device, A3XX_CP_PROTECT_REG_A, 0x64001180);
/* RB registers */
adreno_regwrite(device, A3XX_CP_PROTECT_REG_B, 0x60003300);
/* VBIF registers */
adreno_regwrite(device, A3XX_CP_PROTECT_REG_C, 0x6B00C000);
}
if (adreno_is_a2xx(adreno_dev)) {
/* explicitly clear all cp interrupts */
adreno_regwrite(device, REG_CP_INT_ACK, 0xFFFFFFFF);

16
kernel/drivers/gpu/msm/kgsl_iommu.c
View File

@ -989,10 +989,6 @@ inline unsigned int kgsl_iommu_sync_lock(struct kgsl_mmu *mmu,
*cmds++ = 0x1;
*cmds++ = 0x1;
/* WAIT_REG_MEM turns back on protected mode - push it off */
*cmds++ = cp_type3_packet(CP_SET_PROTECTED_MODE, 1);
*cmds++ = 0;
*cmds++ = cp_type3_packet(CP_MEM_WRITE, 2);
*cmds++ = lock_vars->turn;
*cmds++ = 0;
@ -1007,19 +1003,11 @@ inline unsigned int kgsl_iommu_sync_lock(struct kgsl_mmu *mmu,
*cmds++ = 0x1;
*cmds++ = 0x1;
/* WAIT_REG_MEM turns back on protected mode - push it off */
*cmds++ = cp_type3_packet(CP_SET_PROTECTED_MODE, 1);
*cmds++ = 0;
*cmds++ = cp_type3_packet(CP_TEST_TWO_MEMS, 3);
*cmds++ = lock_vars->flag[PROC_APPS];
*cmds++ = lock_vars->turn;
*cmds++ = 0;
/* TEST_TWO_MEMS turns back on protected mode - push it off */
*cmds++ = cp_type3_packet(CP_SET_PROTECTED_MODE, 1);
*cmds++ = 0;
cmds += adreno_add_idle_cmds(adreno_dev, cmds);
return cmds - start;
@ -1057,10 +1045,6 @@ inline unsigned int kgsl_iommu_sync_unlock(struct kgsl_mmu *mmu,
*cmds++ = 0x1;
*cmds++ = 0x1;
/* WAIT_REG_MEM turns back on protected mode - push it off */
*cmds++ = cp_type3_packet(CP_SET_PROTECTED_MODE, 1);
*cmds++ = 0;
cmds += adreno_add_idle_cmds(adreno_dev, cmds);
return cmds - start;

4
kernel/drivers/gpu/msm/kgsl_mmu.c
View File

@ -372,10 +372,6 @@ int kgsl_mmu_init(struct kgsl_device *device)
status = kgsl_allocate_contiguous(&mmu->setstate_memory, PAGE_SIZE);
if (status)
return status;
/* Mark the setstate memory as read only */
mmu->setstate_memory.flags |= KGSL_MEMFLAGS_GPUREADONLY;
kgsl_sharedmem_set(device, &mmu->setstate_memory, 0, 0,
mmu->setstate_memory.size);