53 lines
1.6 KiB
Plaintext
53 lines
1.6 KiB
Plaintext
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* Qualcomm MSM IOMMU v0
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Required properties:
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- compatible : one of:
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- "qcom,msm-smmu-v0"
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- reg : offset and length of the register set for the device.
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- qcom,glb-offset : Offset for the global register base.
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Optional properties:
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- interrupts : should contain the performance monitor overflow interrupt number.
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- qcom,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups.
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- qcom,iommu-pmu-ncounters: Number of PMU counters per group.
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- qcom,iommu-pmu-event-classes: List of event classes supported.
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- qcom,needs-alt-core-clk : boolean to enable the secondary core clock for
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access to the IOMMU configuration registers
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- Bus scaling properties: See msm_bus.txt
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- List of sub nodes, one for each of the translation context banks supported.
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Required properties for each sub-node:
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- compatible : "qcom,msm-smmu-v0-ctx"
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- reg : offset and length of the register set for the context bank.
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- interrupts : should contain the context bank interrupt.
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- qcom,iommu-ctx-mids : List of machine identifiers associated with this
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translation context.
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- label : Name of the context bank
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Optional properties for each sub-node:
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- none
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Example:
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qcom,iommu@fd000000 {
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compatible = "qcom,msm-smmu-v0";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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reg = <0xfd890000 0x10000>;
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qcom,glb-offset = <0xF000>;
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interrupts = <0 38 0>;
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qcom,iommu-pmu-ngroups = <1>;
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qcom,iommu-pmu-ncounters = <4>;
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qcom,iommu-pmu-event-classes = <0x08
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0x11>;
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qcom,iommu-ctx@fd000000 {
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compatible = "qcom,msm-smmu-v0-ctx";
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reg = <0xfd000000 0x1000>;
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interrupts = <0 250 0>;
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qcom,iommu-ctx-mids = <0 3>;
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label = "a_label";
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};
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