* Qualcomm MSM IOMMU v0

Required properties:
- compatible : one of:
	- "qcom,msm-smmu-v0"
- reg : offset and length of the register set for the device.
- qcom,glb-offset : Offset for the global register base.

Optional properties:
- interrupts : should contain the performance monitor overflow interrupt number.
- qcom,iommu-pmu-ngroups: Number of Performance Monitor Unit (PMU) groups.
- qcom,iommu-pmu-ncounters: Number of PMU counters per group.
- qcom,iommu-pmu-event-classes: List of event classes supported.
- qcom,needs-alt-core-clk : boolean to enable the secondary core clock for
  access to the IOMMU configuration registers
- Bus scaling properties: See msm_bus.txt

- List of sub nodes, one for each of the translation context banks supported.
    Required properties for each sub-node:

    - compatible : "qcom,msm-smmu-v0-ctx"
    - reg : offset and length of the register set for the context bank.
    - interrupts : should contain the context bank interrupt.
    - qcom,iommu-ctx-mids : List of machine identifiers associated with this
      translation context.
    - label : Name of the context bank

    Optional properties for each sub-node:
    - none

Example:

	qcom,iommu@fd000000 {
		compatible = "qcom,msm-smmu-v0";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		reg = <0xfd890000 0x10000>;
		qcom,glb-offset = <0xF000>;
		interrupts = <0 38 0>;
		qcom,iommu-pmu-ngroups = <1>;
		qcom,iommu-pmu-ncounters = <4>;
		qcom,iommu-pmu-event-classes = <0x08
						0x11>;

		qcom,iommu-ctx@fd000000 {
			compatible = "qcom,msm-smmu-v0-ctx";
			reg = <0xfd000000 0x1000>;
			interrupts = <0 250 0>;
			qcom,iommu-ctx-mids = <0 3>;
			label = "a_label";
		};