541 lines
16 KiB
Plaintext
541 lines
16 KiB
Plaintext
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/* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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mdss_mdp: qcom,mdss_mdp@900000 {
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compatible = "qcom,mdss_mdp";
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reg = <0x00900000 0x90000>,
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<0x009b0000 0x1040>,
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<0x009b8000 0x1040>;
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reg-names = "mdp_phys", "vbif_phys", "vbif_nrt_phys";
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interrupts = <0 83 0>;
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vdd-supply = <&gdsc_mdss>;
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/* Bus Scale Settings */
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qcom,msm-bus,name = "mdss_mdp";
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qcom,msm-bus,num-cases = <3>;
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qcom,msm-bus,num-paths = <3>;
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qcom,msm-bus,vectors-KBps =
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<22 512 0 0>, <23 512 0 0>, <25 512 0 0>,
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<22 512 0 6400000>, <23 512 0 6400000>, <25 512 0 6400000>,
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<22 512 0 6400000>, <23 512 0 6400000>, <25 512 0 6400000>;
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qcom,mdss-num-nrt-paths = <1>;
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/* Fudge factors */
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qcom,mdss-ab-factor = <1 1>; /* 1 time */
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qcom,mdss-ib-factor = <1 1>; /* 1 time */
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qcom,mdss-clk-factor = <105 100>; /* 1.05 times */
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qcom,max-mixer-width = <2560>;
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qcom,max-pipe-width = <2560>;
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/* VBIF QoS remapper settings*/
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qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>;
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qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>;
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qcom,mdss-has-panic-ctrl;
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qcom,mdss-per-pipe-panic-luts = <0x000f>,
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<0xffff>,
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<0xfffc>,
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<0xff00>;
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qcom,mdss-mdp-reg-offset = <0x00001000>;
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qcom,max-bandwidth-low-kbps = <9600000>;
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qcom,max-bandwidth-high-kbps = <9600000>;
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qcom,max-bandwidth-per-pipe-kbps = <4500000>;
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qcom,max-clk-rate = <412500000>;
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qcom,mdss-default-ot-rd-limit = <32>;
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qcom,mdss-default-ot-wr-limit = <16>;
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qcom,mdss-dram-channels = <2>;
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qcom,mdss-pipe-vig-off = <0x00005000 0x00007000
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0x00009000 0x0000B000>;
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qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000
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0x00019000 0x0001B000>;
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qcom,mdss-pipe-dma-off = <0x00025000 0x00027000>;
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qcom,mdss-pipe-cursor-off = <0x00035000 0x00037000>;
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qcom,mdss-pipe-vig-xin-id = <0 4 8 12>;
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qcom,mdss-pipe-rgb-xin-id = <1 5 9 13>;
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qcom,mdss-pipe-dma-xin-id = <2 10>;
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qcom,mdss-pipe-cursor-xin-id = <7 7>;
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/* These Offsets are relative to "mdp_phys + mdp-reg-offset" address */
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qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>,
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<0x2B4 0 0>,
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<0x2BC 0 0>,
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<0x2C4 0 0>;
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qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>,
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<0x2B4 4 8>,
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<0x2BC 4 8>,
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<0x2C4 4 8>;
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qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>,
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<0x2B4 8 12>;
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qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>,
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<0x3B0 16 15>;
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qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400
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0x00002600 0x00002800>;
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qcom,mdss-mixer-intf-off = <0x00045000 0x00046000
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0x00047000 0x0004A000>;
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qcom,mdss-mixer-wb-off = <0x00048000 0x00049000>;
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qcom,mdss-dspp-off = <0x00055000 0x00057000>;
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qcom,mdss-wb-off = <0x00065000 0x00065800 0x00066000>;
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qcom,mdss-intf-off = <0x0006B000 0x0006B800
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0x0006C000 0x0006C800>;
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qcom,mdss-pingpong-off = <0x00071000 0x00071800
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0x00072000 0x00072800>;
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qcom,mdss-slave-pingpong-off = <0x00073000>;
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qcom,mdss-ppb-off = <0x00000330 0x00000338>;
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qcom,mdss-has-pingpong-split;
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qcom,mdss-ad-off = <0x0079000 0x00079800 0x0007a000>;
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qcom,mdss-cdm-off = <0x0007a200>;
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qcom,mdss-dsc-off = <0x00081000 0x00081400>;
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qcom,mdss-wfd-mode = "intf";
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qcom,mdss-has-source-split;
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qcom,mdss-highest-bank-bit = <0x2>;
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qcom,mdss-has-decimation;
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qcom,mdss-has-rotator-downscale;
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qcom,mdss-idle-power-collapse-enabled;
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clocks = <&clock_mmss clk_mdss_ahb_clk>,
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<&clock_mmss clk_mdss_axi_clk>,
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<&clock_mmss clk_mdp_clk_src>,
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<&clock_mmss clk_mdss_mdp_vote_clk>,
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<&clock_mmss clk_mdss_vsync_clk>;
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clock-names = "iface_clk", "bus_clk", "core_clk_src",
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"core_clk", "vsync_clk";
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qcom,mdp-settings = <0x01190 0x00000000>,
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<0x012ac 0xc0000ccc>,
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<0x012b4 0xc0000ccc>,
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<0x012bc 0x00cccccc>,
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<0x012c4 0x000000cc>,
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<0x013a8 0x0cccc0c0>,
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<0x013b0 0xccccc0c0>,
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<0x013b8 0xcccc0000>,
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<0x013d0 0x00cc0000>,
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<0x0506c 0x00000000>,
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<0x0706c 0x00000000>,
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<0x0906c 0x00000000>,
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<0x0b06c 0x00000000>,
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<0x1506c 0x00000000>,
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<0x1706c 0x00000000>,
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<0x1906c 0x00000000>,
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<0x1b06c 0x00000000>,
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<0x2506c 0x00000000>,
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<0x2706c 0x00000000>;
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qcom,regs-dump-mdp = <0x01000 0x01454>,
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<0x02000 0x02064>,
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<0x02200 0x02264>,
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<0x02400 0x02464>,
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<0x02600 0x02664>,
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<0x02800 0x02864>,
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<0x05000 0x05150>,
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<0x05200 0x05230>,
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<0x07000 0x07150>,
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<0x07200 0x07230>,
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<0x09000 0x09150>,
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<0x09200 0x09230>,
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<0x0b000 0x0b150>,
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<0x0b200 0x0b230>,
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<0x15000 0x15150>,
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<0x15200 0x15230>,
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<0x17000 0x17150>,
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<0x17200 0x17230>,
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<0x19000 0x19150>,
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<0x19200 0x19230>,
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<0x1b000 0x1b150>,
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<0x1b200 0x1b230>,
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<0x25000 0x25150>,
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<0x27000 0x27150>,
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<0x35000 0x35150>,
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<0x37000 0x37150>,
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<0x45000 0x452bc>,
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<0x46000 0x462bc>,
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<0x47000 0x472bc>,
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<0x48000 0x482bc>,
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<0x49000 0x492bc>,
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<0x4a000 0x4a2bc>,
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<0x55000 0x5522c>,
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<0x57000 0x5722c>,
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<0x65000 0x652c0>,
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<0x65800 0x65ac0>,
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<0x66000 0x662c0>,
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<0x6b800 0x6ba68>,
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<0x6c000 0x6c268>,
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<0x6c800 0x6ca68>,
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<0x71000 0x710d4>,
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<0x71800 0x718d4>,
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<0x73000 0x730d4>,
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<0x81000 0x81140>,
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<0x81400 0x81540>;
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qcom,regs-dump-names-mdp = "MDP",
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"CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4",
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"VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1",
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"VIG2_SSPP", "VIG2", "VIG3_SSPP", "VIG3",
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"RGB0_SSPP", "RGB0", "RGB1_SSPP", "RGB1",
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"RGB2_SSPP", "RGB2", "RGB3_SSPP", "RGB3",
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"DMA0_SSPP", "DMA1_SSPP",
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"CURSOR0_SSPP", "CURSOR1_SSPP",
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"LAYER_0", "LAYER_1", "LAYER_2",
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"LAYER_3", "LAYER_4", "LAYER_5",
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"DSPP_0", "DSPP_1",
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"WB_0", "WB_1", "WB_2",
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"INTF_1", "INTF_2", "INTF_3",
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"PP_0", "PP_1", "PP_4",
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"DSC_0", "DSC_1";
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/* buffer parameters to calculate prefill bandwidth */
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qcom,mdss-prefill-outstanding-buffer-bytes = <0>;
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qcom,mdss-prefill-y-buffer-bytes = <0>;
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qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;
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qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;
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qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>;
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qcom,mdss-prefill-pingpong-buffer-pixels = <5120>;
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qcom,mdss-pp-offsets {
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qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
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qcom,mdss-sspp-vig-pcc-off = <0x1780>;
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qcom,mdss-sspp-rgb-pcc-off = <0x380>;
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qcom,mdss-sspp-dma-pcc-off = <0x380>;
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qcom,mdss-lm-pgc-off = <0x3C0>;
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qcom,mdss-dspp-gamut-off = <0x1600>;
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qcom,mdss-dspp-pcc-off = <0x1700>;
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qcom,mdss-dspp-pgc-off = <0x17C0>;
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};
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smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
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compatible = "qcom,smmu_mdp_unsec";
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iommus = <&mdp_smmu 0>;
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gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
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clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>,
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<&clock_mmss clk_mmagic_mdss_axi_clk>,
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<&clock_mmss clk_smmu_mdp_axi_clk>;
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clock-names = "mdp_ahb_clk", "mmagic_mdss_axi_clk",
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"mdp_axi_clk";
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};
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smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
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compatible = "qcom,smmu_rot_unsec";
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iommus = <&rot_smmu 0>;
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gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
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clocks = <&clock_mmss clk_smmu_rot_ahb_clk>,
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<&clock_mmss clk_mmagic_mdss_axi_clk>,
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<&clock_mmss clk_smmu_rot_axi_clk>;
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clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk",
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"rot_axi_clk";
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};
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smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
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compatible = "qcom,smmu_mdp_sec";
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iommus = <&mdp_smmu 1>;
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gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
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clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>,
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<&clock_mmss clk_mmagic_mdss_axi_clk>,
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<&clock_mmss clk_smmu_mdp_axi_clk>;
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clock-names = "mdp_ahb_clk", "mmagic_mdss_axi_clk",
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"mdp_axi_clk";
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};
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smmu_rot_sec: qcom,smmu_rot_sec_cb {
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compatible = "qcom,smmu_rot_sec";
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iommus = <&rot_smmu 1>;
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gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>;
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clocks = <&clock_mmss clk_smmu_rot_ahb_clk>,
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<&clock_mmss clk_mmagic_mdss_axi_clk>,
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<&clock_mmss clk_smmu_rot_axi_clk>;
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clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk",
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"rot_axi_clk";
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};
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mdss_fb0: qcom,mdss_fb_primary {
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cell-index = <0>;
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compatible = "qcom,mdss-fb";
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qcom,cont-splash-memory {
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linux,contiguous-region = <&cont_splash_mem>;
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};
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};
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mdss_fb1: qcom,mdss_fb_wfd {
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cell-index = <1>;
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compatible = "qcom,mdss-fb";
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};
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mdss_fb2: qcom,mdss_fb_hdmi {
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cell-index = <2>;
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compatible = "qcom,mdss-fb";
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};
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mdss_fb3: qcom,mdss_fb_secondary {
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cell-index = <3>;
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compatible = "qcom,mdss-fb";
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};
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};
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mdss_dsi: qcom,mdss_dsi@0 {
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compatible = "qcom,mdss-dsi";
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#address-cells = <1>;
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#size-cells = <1>;
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gdsc-supply = <&gdsc_mdss>;
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vdda-supply = <&pm8994_l2>;
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vcca-supply = <&pm8994_l28>;
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ranges = <0x994000 0x994000 0x400
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0x994400 0x994400 0x558
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0x828000 0x828000 0x108
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0x996000 0x996000 0x400
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0x996400 0x996400 0x558
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0x828000 0x828000 0x108>;
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/* Bus Scale Settings */
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qcom,msm-bus,name = "mdss_dsi";
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qcom,msm-bus,num-cases = <2>;
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|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<22 512 0 0>,
|
||
|
|
<22 512 0 1000>;
|
||
|
|
|
||
|
|
qcom,mmss-ulp-clamp-ctrl-offset = <0x14>;
|
||
|
|
|
||
|
|
qcom,mdss-fb-map-prim = <&mdss_fb0>;
|
||
|
|
qcom,mdss-fb-map-sec = <&mdss_fb3>;
|
||
|
|
|
||
|
|
clocks = <&clock_mmss clk_mdss_mdp_vote_clk>,
|
||
|
|
<&clock_mmss clk_mdss_ahb_clk>,
|
||
|
|
<&clock_mmss clk_mmss_misc_ahb_clk>,
|
||
|
|
<&clock_mmss clk_mdss_axi_clk>,
|
||
|
|
<&clock_mmss clk_ext_byte0_clk_src>,
|
||
|
|
<&clock_mmss clk_ext_byte1_clk_src>,
|
||
|
|
<&clock_mmss clk_ext_pclk0_clk_src>,
|
||
|
|
<&clock_mmss clk_ext_pclk1_clk_src>;
|
||
|
|
clock-names = "mdp_core_clk", "iface_clk",
|
||
|
|
"core_mmss_clk", "bus_clk",
|
||
|
|
"ext_byte0_clk", "ext_byte1_clk",
|
||
|
|
"ext_pixel0_clk", "ext_pixel1_clk";
|
||
|
|
|
||
|
|
qcom,core-supply-entries {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
qcom,core-supply-entry@0 {
|
||
|
|
reg = <0>;
|
||
|
|
qcom,supply-name = "gdsc";
|
||
|
|
qcom,supply-min-voltage = <0>;
|
||
|
|
qcom,supply-max-voltage = <0>;
|
||
|
|
qcom,supply-enable-load = <0>;
|
||
|
|
qcom,supply-disable-load = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,ctrl-supply-entries {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
qcom,ctrl-supply-entry@0 {
|
||
|
|
reg = <0>;
|
||
|
|
qcom,supply-name = "vdda";
|
||
|
|
qcom,supply-min-voltage = <1250000>;
|
||
|
|
qcom,supply-max-voltage = <1250000>;
|
||
|
|
qcom,supply-enable-load = <18160>;
|
||
|
|
qcom,supply-disable-load = <1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,phy-supply-entries {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
qcom,phy-supply-entry@0 {
|
||
|
|
reg = <0>;
|
||
|
|
qcom,supply-name = "vcca";
|
||
|
|
qcom,supply-min-voltage = <925000>;
|
||
|
|
qcom,supply-max-voltage = <925000>;
|
||
|
|
qcom,supply-enable-load = <17000>;
|
||
|
|
qcom,supply-disable-load = <32>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mdss_dsi0: qcom,mdss_dsi_ctrl0@994000 {
|
||
|
|
compatible = "qcom,mdss-dsi-ctrl";
|
||
|
|
label = "MDSS DSI CTRL->0";
|
||
|
|
cell-index = <0>;
|
||
|
|
reg = <0x994000 0x400>,
|
||
|
|
<0x994400 0x588>,
|
||
|
|
<0x828000 0x108>;
|
||
|
|
reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
|
||
|
|
|
||
|
|
qcom,timing-db-mode;
|
||
|
|
oled-vdda-supply = <&pm8994_l19>;
|
||
|
|
vddio-supply = <&pm8994_l14>;
|
||
|
|
lab-supply = <&lab_regulator>;
|
||
|
|
ibb-supply = <&ibb_regulator>;
|
||
|
|
qcom,mdss-mdp = <&mdss_mdp>;
|
||
|
|
|
||
|
|
clocks = <&clock_mmss clk_mdss_byte0_clk>,
|
||
|
|
<&clock_mmss clk_mdss_pclk0_clk>,
|
||
|
|
<&clock_mmss clk_mdss_esc0_clk>,
|
||
|
|
<&clock_mmss clk_byte0_clk_src>,
|
||
|
|
<&clock_mmss clk_pclk0_clk_src>,
|
||
|
|
<&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>,
|
||
|
|
<&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>,
|
||
|
|
<&mdss_dsi0_pll clk_dsi0pll_byte_clk_src>,
|
||
|
|
<&mdss_dsi0_pll clk_dsi0pll_pixel_clk_src>,
|
||
|
|
<&mdss_dsi0_pll
|
||
|
|
clk_dsi0pll_shadow_byte_clk_src>,
|
||
|
|
<&mdss_dsi0_pll
|
||
|
|
clk_dsi0pll_shadow_pixel_clk_src>;
|
||
|
|
clock-names = "byte_clk", "pixel_clk", "core_clk",
|
||
|
|
"byte_clk_rcg", "pixel_clk_rcg",
|
||
|
|
"pll_byte_clk_mux", "pll_pixel_clk_mux",
|
||
|
|
"pll_byte_clk_src", "pll_pixel_clk_src",
|
||
|
|
"pll_shadow_byte_clk_src",
|
||
|
|
"pll_shadow_pixel_clk_src";
|
||
|
|
|
||
|
|
qcom,null-insertion-enabled;
|
||
|
|
qcom,platform-strength-ctrl = [ff 06
|
||
|
|
ff 06
|
||
|
|
ff 06
|
||
|
|
ff 06
|
||
|
|
ff 00];
|
||
|
|
qcom,platform-regulator-settings = [1d
|
||
|
|
1d 1d 1d 1d];
|
||
|
|
qcom,platform-lane-config = [00 00 10 0f
|
||
|
|
00 00 10 0f
|
||
|
|
00 00 10 0f
|
||
|
|
00 00 10 0f
|
||
|
|
00 00 10 8f];
|
||
|
|
};
|
||
|
|
|
||
|
|
mdss_dsi1: qcom,mdss_dsi_ctrl1@996000 {
|
||
|
|
compatible = "qcom,mdss-dsi-ctrl";
|
||
|
|
label = "MDSS DSI CTRL->1";
|
||
|
|
cell-index = <1>;
|
||
|
|
reg = <0x996000 0x400>,
|
||
|
|
<0x996400 0x558>,
|
||
|
|
<0x828000 0x108>;
|
||
|
|
reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
|
||
|
|
|
||
|
|
qcom,timing-db-mode;
|
||
|
|
oled-vdda-supply = <&pm8994_l19>;
|
||
|
|
vddio-supply = <&pm8994_l14>;
|
||
|
|
lab-supply = <&lab_regulator>;
|
||
|
|
ibb-supply = <&ibb_regulator>;
|
||
|
|
qcom,mdss-mdp = <&mdss_mdp>;
|
||
|
|
|
||
|
|
clocks = <&clock_mmss clk_mdss_byte1_clk>,
|
||
|
|
<&clock_mmss clk_mdss_pclk1_clk>,
|
||
|
|
<&clock_mmss clk_mdss_esc1_clk>,
|
||
|
|
<&clock_mmss clk_byte1_clk_src>,
|
||
|
|
<&clock_mmss clk_pclk1_clk_src>,
|
||
|
|
<&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>,
|
||
|
|
<&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>,
|
||
|
|
<&mdss_dsi1_pll clk_dsi1pll_byte_clk_src>,
|
||
|
|
<&mdss_dsi1_pll clk_dsi1pll_pixel_clk_src>,
|
||
|
|
<&mdss_dsi1_pll
|
||
|
|
clk_dsi1pll_shadow_byte_clk_src>,
|
||
|
|
<&mdss_dsi1_pll
|
||
|
|
clk_dsi1pll_shadow_pixel_clk_src>;
|
||
|
|
clock-names = "byte_clk", "pixel_clk", "core_clk",
|
||
|
|
"byte_clk_rcg", "pixel_clk_rcg",
|
||
|
|
"pll_byte_clk_mux", "pll_pixel_clk_mux",
|
||
|
|
"pll_byte_clk_src", "pll_pixel_clk_src",
|
||
|
|
"pll_byte_clk_src", "pll_pixel_clk_src",
|
||
|
|
"pll_shadow_byte_clk_src",
|
||
|
|
"pll_shadow_pixel_clk_src";
|
||
|
|
|
||
|
|
qcom,null-insertion-enabled;
|
||
|
|
qcom,platform-strength-ctrl = [ff 06
|
||
|
|
ff 06
|
||
|
|
ff 06
|
||
|
|
ff 06
|
||
|
|
ff 00];
|
||
|
|
qcom,platform-regulator-settings = [1d
|
||
|
|
1d 1d 1d 1d];
|
||
|
|
qcom,platform-lane-config = [00 00 10 0f
|
||
|
|
00 00 10 0f
|
||
|
|
00 00 10 0f
|
||
|
|
00 00 10 0f
|
||
|
|
00 00 10 8f];
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
qcom,mdss_wb_panel {
|
||
|
|
compatible = "qcom,mdss_wb";
|
||
|
|
qcom,mdss_pan_res = <640 480>;
|
||
|
|
qcom,mdss_pan_bpp = <24>;
|
||
|
|
qcom,mdss-fb-map = <&mdss_fb1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mdss_hdmi_tx: qcom,hdmi_tx@9a0000 {
|
||
|
|
cell-index = <0>;
|
||
|
|
compatible = "qcom,hdmi-tx";
|
||
|
|
|
||
|
|
reg = <0x9a0000 0x50c>,
|
||
|
|
<0x70000 0x6158>,
|
||
|
|
<0x9e0000 0xFFF>;
|
||
|
|
reg-names = "core_physical", "qfprom_physical", "hdcp_physical";
|
||
|
|
|
||
|
|
hpd-gdsc-supply = <&gdsc_mdss>;
|
||
|
|
|
||
|
|
qcom,supply-names = "hpd-gdsc";
|
||
|
|
qcom,min-voltage-level = <0>;
|
||
|
|
qcom,max-voltage-level = <0>;
|
||
|
|
qcom,enable-load = <0>;
|
||
|
|
qcom,disable-load = <0>;
|
||
|
|
|
||
|
|
clocks = <&clock_mmss clk_mdss_mdp_vote_clk>,
|
||
|
|
<&clock_mmss clk_mdss_ahb_clk>,
|
||
|
|
<&clock_mmss clk_mdss_hdmi_clk>,
|
||
|
|
<&clock_mmss clk_mdss_hdmi_ahb_clk>,
|
||
|
|
<&clock_mmss clk_mdss_extpclk_clk>;
|
||
|
|
clock-names = "mdp_core_clk", "iface_clk",
|
||
|
|
"core_clk", "alt_iface_clk", "extp_clk";
|
||
|
|
|
||
|
|
qcom,hdmi-tx-hpd = <&pm8994_mpps 4 0>;
|
||
|
|
qcom,mdss-fb-map = <&mdss_fb2>;
|
||
|
|
qcom,pluggable;
|
||
|
|
|
||
|
|
hdmi_audio: qcom,msm-hdmi-audio-rx {
|
||
|
|
compatible = "qcom,msm-hdmi-audio-codec-rx";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mdss_rotator: qcom,mdss_rotator {
|
||
|
|
compatible = "qcom,mdss_rotator";
|
||
|
|
qcom,mdss-wb-count = <2>;
|
||
|
|
qcom,mdss-has-downscale;
|
||
|
|
qcom,mdss-has-ubwc;
|
||
|
|
qcom,mdss-has-reg-bus;
|
||
|
|
/* Bus Scale Settings */
|
||
|
|
qcom,msm-bus,name = "mdss_rotator";
|
||
|
|
qcom,msm-bus,num-cases = <3>;
|
||
|
|
qcom,msm-bus,num-paths = <1>;
|
||
|
|
qcom,msm-bus,vectors-KBps =
|
||
|
|
<25 512 0 0>,
|
||
|
|
<25 512 0 6400000>,
|
||
|
|
<25 512 0 6400000>;
|
||
|
|
|
||
|
|
rot-vdd-supply = <&gdsc_mdss>;
|
||
|
|
rot-mmagic-mdss-gdsc-supply = <&gdsc_mmagic_mdss>;
|
||
|
|
|
||
|
|
qcom,supply-names = "rot-mmagic-mdss-gdsc", "rot-vdd";
|
||
|
|
|
||
|
|
clocks = <&clock_mmss clk_mmss_misc_ahb_clk>,
|
||
|
|
<&clock_mmss clk_mdss_rotator_vote_clk>;
|
||
|
|
clock-names = "iface_clk", "rot_core_clk";
|
||
|
|
};
|
||
|
|
};
|