/* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ &soc { mdss_mdp: qcom,mdss_mdp@900000 { compatible = "qcom,mdss_mdp"; reg = <0x00900000 0x90000>, <0x009b0000 0x1040>, <0x009b8000 0x1040>; reg-names = "mdp_phys", "vbif_phys", "vbif_nrt_phys"; interrupts = <0 83 0>; vdd-supply = <&gdsc_mdss>; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_mdp"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <3>; qcom,msm-bus,vectors-KBps = <22 512 0 0>, <23 512 0 0>, <25 512 0 0>, <22 512 0 6400000>, <23 512 0 6400000>, <25 512 0 6400000>, <22 512 0 6400000>, <23 512 0 6400000>, <25 512 0 6400000>; qcom,mdss-num-nrt-paths = <1>; /* Fudge factors */ qcom,mdss-ab-factor = <1 1>; /* 1 time */ qcom,mdss-ib-factor = <1 1>; /* 1 time */ qcom,mdss-clk-factor = <105 100>; /* 1.05 times */ qcom,max-mixer-width = <2560>; qcom,max-pipe-width = <2560>; /* VBIF QoS remapper settings*/ qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>; qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>; qcom,mdss-has-panic-ctrl; qcom,mdss-per-pipe-panic-luts = <0x000f>, <0xffff>, <0xfffc>, <0xff00>; qcom,mdss-mdp-reg-offset = <0x00001000>; qcom,max-bandwidth-low-kbps = <9600000>; qcom,max-bandwidth-high-kbps = <9600000>; qcom,max-bandwidth-per-pipe-kbps = <4500000>; qcom,max-clk-rate = <412500000>; qcom,mdss-default-ot-rd-limit = <32>; qcom,mdss-default-ot-wr-limit = <16>; qcom,mdss-dram-channels = <2>; qcom,mdss-pipe-vig-off = <0x00005000 0x00007000 0x00009000 0x0000B000>; qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000 0x00019000 0x0001B000>; qcom,mdss-pipe-dma-off = <0x00025000 0x00027000>; qcom,mdss-pipe-cursor-off = <0x00035000 0x00037000>; qcom,mdss-pipe-vig-xin-id = <0 4 8 12>; qcom,mdss-pipe-rgb-xin-id = <1 5 9 13>; qcom,mdss-pipe-dma-xin-id = <2 10>; qcom,mdss-pipe-cursor-xin-id = <7 7>; /* These Offsets are relative to "mdp_phys + mdp-reg-offset" address */ qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>, <0x2B4 0 0>, <0x2BC 0 0>, <0x2C4 0 0>; qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>, <0x2B4 4 8>, <0x2BC 4 8>, <0x2C4 4 8>; qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>, <0x2B4 8 12>; qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>, <0x3B0 16 15>; qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 0x00002600 0x00002800>; qcom,mdss-mixer-intf-off = <0x00045000 0x00046000 0x00047000 0x0004A000>; qcom,mdss-mixer-wb-off = <0x00048000 0x00049000>; qcom,mdss-dspp-off = <0x00055000 0x00057000>; qcom,mdss-wb-off = <0x00065000 0x00065800 0x00066000>; qcom,mdss-intf-off = <0x0006B000 0x0006B800 0x0006C000 0x0006C800>; qcom,mdss-pingpong-off = <0x00071000 0x00071800 0x00072000 0x00072800>; qcom,mdss-slave-pingpong-off = <0x00073000>; qcom,mdss-ppb-off = <0x00000330 0x00000338>; qcom,mdss-has-pingpong-split; qcom,mdss-ad-off = <0x0079000 0x00079800 0x0007a000>; qcom,mdss-cdm-off = <0x0007a200>; qcom,mdss-dsc-off = <0x00081000 0x00081400>; qcom,mdss-wfd-mode = "intf"; qcom,mdss-has-source-split; qcom,mdss-highest-bank-bit = <0x2>; qcom,mdss-has-decimation; qcom,mdss-has-rotator-downscale; qcom,mdss-idle-power-collapse-enabled; clocks = <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mdss_axi_clk>, <&clock_mmss clk_mdp_clk_src>, <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_vsync_clk>; clock-names = "iface_clk", "bus_clk", "core_clk_src", "core_clk", "vsync_clk"; qcom,mdp-settings = <0x01190 0x00000000>, <0x012ac 0xc0000ccc>, <0x012b4 0xc0000ccc>, <0x012bc 0x00cccccc>, <0x012c4 0x000000cc>, <0x013a8 0x0cccc0c0>, <0x013b0 0xccccc0c0>, <0x013b8 0xcccc0000>, <0x013d0 0x00cc0000>, <0x0506c 0x00000000>, <0x0706c 0x00000000>, <0x0906c 0x00000000>, <0x0b06c 0x00000000>, <0x1506c 0x00000000>, <0x1706c 0x00000000>, <0x1906c 0x00000000>, <0x1b06c 0x00000000>, <0x2506c 0x00000000>, <0x2706c 0x00000000>; qcom,regs-dump-mdp = <0x01000 0x01454>, <0x02000 0x02064>, <0x02200 0x02264>, <0x02400 0x02464>, <0x02600 0x02664>, <0x02800 0x02864>, <0x05000 0x05150>, <0x05200 0x05230>, <0x07000 0x07150>, <0x07200 0x07230>, <0x09000 0x09150>, <0x09200 0x09230>, <0x0b000 0x0b150>, <0x0b200 0x0b230>, <0x15000 0x15150>, <0x15200 0x15230>, <0x17000 0x17150>, <0x17200 0x17230>, <0x19000 0x19150>, <0x19200 0x19230>, <0x1b000 0x1b150>, <0x1b200 0x1b230>, <0x25000 0x25150>, <0x27000 0x27150>, <0x35000 0x35150>, <0x37000 0x37150>, <0x45000 0x452bc>, <0x46000 0x462bc>, <0x47000 0x472bc>, <0x48000 0x482bc>, <0x49000 0x492bc>, <0x4a000 0x4a2bc>, <0x55000 0x5522c>, <0x57000 0x5722c>, <0x65000 0x652c0>, <0x65800 0x65ac0>, <0x66000 0x662c0>, <0x6b800 0x6ba68>, <0x6c000 0x6c268>, <0x6c800 0x6ca68>, <0x71000 0x710d4>, <0x71800 0x718d4>, <0x73000 0x730d4>, <0x81000 0x81140>, <0x81400 0x81540>; qcom,regs-dump-names-mdp = "MDP", "CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4", "VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1", "VIG2_SSPP", "VIG2", "VIG3_SSPP", "VIG3", "RGB0_SSPP", "RGB0", "RGB1_SSPP", "RGB1", "RGB2_SSPP", "RGB2", "RGB3_SSPP", "RGB3", "DMA0_SSPP", "DMA1_SSPP", "CURSOR0_SSPP", "CURSOR1_SSPP", "LAYER_0", "LAYER_1", "LAYER_2", "LAYER_3", "LAYER_4", "LAYER_5", "DSPP_0", "DSPP_1", "WB_0", "WB_1", "WB_2", "INTF_1", "INTF_2", "INTF_3", "PP_0", "PP_1", "PP_4", "DSC_0", "DSC_1"; /* buffer parameters to calculate prefill bandwidth */ qcom,mdss-prefill-outstanding-buffer-bytes = <0>; qcom,mdss-prefill-y-buffer-bytes = <0>; qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>; qcom,mdss-prefill-scaler-buffer-lines-caf = <4>; qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>; qcom,mdss-prefill-pingpong-buffer-pixels = <5120>; qcom,mdss-pp-offsets { qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; qcom,mdss-sspp-vig-pcc-off = <0x1780>; qcom,mdss-sspp-rgb-pcc-off = <0x380>; qcom,mdss-sspp-dma-pcc-off = <0x380>; qcom,mdss-lm-pgc-off = <0x3C0>; qcom,mdss-dspp-gamut-off = <0x1600>; qcom,mdss-dspp-pcc-off = <0x1700>; qcom,mdss-dspp-pgc-off = <0x17C0>; }; smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { compatible = "qcom,smmu_mdp_unsec"; iommus = <&mdp_smmu 0>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>; clock-names = "mdp_ahb_clk", "mmagic_mdss_axi_clk", "mdp_axi_clk"; }; smmu_rot_unsec: qcom,smmu_rot_unsec_cb { compatible = "qcom,smmu_rot_unsec"; iommus = <&rot_smmu 0>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_rot_axi_clk>; clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", "rot_axi_clk"; }; smmu_mdp_sec: qcom,smmu_mdp_sec_cb { compatible = "qcom,smmu_mdp_sec"; iommus = <&mdp_smmu 1>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_mdp_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_mdp_axi_clk>; clock-names = "mdp_ahb_clk", "mmagic_mdss_axi_clk", "mdp_axi_clk"; }; smmu_rot_sec: qcom,smmu_rot_sec_cb { compatible = "qcom,smmu_rot_sec"; iommus = <&rot_smmu 1>; gdsc-mmagic-mdss-supply = <&gdsc_mmagic_mdss>; clocks = <&clock_mmss clk_smmu_rot_ahb_clk>, <&clock_mmss clk_mmagic_mdss_axi_clk>, <&clock_mmss clk_smmu_rot_axi_clk>; clock-names = "rot_ahb_clk", "mmagic_mdss_axi_clk", "rot_axi_clk"; }; mdss_fb0: qcom,mdss_fb_primary { cell-index = <0>; compatible = "qcom,mdss-fb"; qcom,cont-splash-memory { linux,contiguous-region = <&cont_splash_mem>; }; }; mdss_fb1: qcom,mdss_fb_wfd { cell-index = <1>; compatible = "qcom,mdss-fb"; }; mdss_fb2: qcom,mdss_fb_hdmi { cell-index = <2>; compatible = "qcom,mdss-fb"; }; mdss_fb3: qcom,mdss_fb_secondary { cell-index = <3>; compatible = "qcom,mdss-fb"; }; }; mdss_dsi: qcom,mdss_dsi@0 { compatible = "qcom,mdss-dsi"; #address-cells = <1>; #size-cells = <1>; gdsc-supply = <&gdsc_mdss>; vdda-supply = <&pm8994_l2>; vcca-supply = <&pm8994_l28>; ranges = <0x994000 0x994000 0x400 0x994400 0x994400 0x558 0x828000 0x828000 0x108 0x996000 0x996000 0x400 0x996400 0x996400 0x558 0x828000 0x828000 0x108>; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_dsi"; qcom,msm-bus,num-cases = <2>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <22 512 0 0>, <22 512 0 1000>; qcom,mmss-ulp-clamp-ctrl-offset = <0x14>; qcom,mdss-fb-map-prim = <&mdss_fb0>; qcom,mdss-fb-map-sec = <&mdss_fb3>; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mmss_misc_ahb_clk>, <&clock_mmss clk_mdss_axi_clk>, <&clock_mmss clk_ext_byte0_clk_src>, <&clock_mmss clk_ext_byte1_clk_src>, <&clock_mmss clk_ext_pclk0_clk_src>, <&clock_mmss clk_ext_pclk1_clk_src>; clock-names = "mdp_core_clk", "iface_clk", "core_mmss_clk", "bus_clk", "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk", "ext_pixel1_clk"; qcom,core-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,core-supply-entry@0 { reg = <0>; qcom,supply-name = "gdsc"; qcom,supply-min-voltage = <0>; qcom,supply-max-voltage = <0>; qcom,supply-enable-load = <0>; qcom,supply-disable-load = <0>; }; }; qcom,ctrl-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,ctrl-supply-entry@0 { reg = <0>; qcom,supply-name = "vdda"; qcom,supply-min-voltage = <1250000>; qcom,supply-max-voltage = <1250000>; qcom,supply-enable-load = <18160>; qcom,supply-disable-load = <1>; }; }; qcom,phy-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,phy-supply-entry@0 { reg = <0>; qcom,supply-name = "vcca"; qcom,supply-min-voltage = <925000>; qcom,supply-max-voltage = <925000>; qcom,supply-enable-load = <17000>; qcom,supply-disable-load = <32>; }; }; mdss_dsi0: qcom,mdss_dsi_ctrl0@994000 { compatible = "qcom,mdss-dsi-ctrl"; label = "MDSS DSI CTRL->0"; cell-index = <0>; reg = <0x994000 0x400>, <0x994400 0x588>, <0x828000 0x108>; reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; qcom,timing-db-mode; oled-vdda-supply = <&pm8994_l19>; vddio-supply = <&pm8994_l14>; lab-supply = <&lab_regulator>; ibb-supply = <&ibb_regulator>; qcom,mdss-mdp = <&mdss_mdp>; clocks = <&clock_mmss clk_mdss_byte0_clk>, <&clock_mmss clk_mdss_pclk0_clk>, <&clock_mmss clk_mdss_esc0_clk>, <&clock_mmss clk_byte0_clk_src>, <&clock_mmss clk_pclk0_clk_src>, <&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>, <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>, <&mdss_dsi0_pll clk_dsi0pll_byte_clk_src>, <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_src>, <&mdss_dsi0_pll clk_dsi0pll_shadow_byte_clk_src>, <&mdss_dsi0_pll clk_dsi0pll_shadow_pixel_clk_src>; clock-names = "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg", "pll_byte_clk_mux", "pll_pixel_clk_mux", "pll_byte_clk_src", "pll_pixel_clk_src", "pll_shadow_byte_clk_src", "pll_shadow_pixel_clk_src"; qcom,null-insertion-enabled; qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; qcom,platform-lane-config = [00 00 10 0f 00 00 10 0f 00 00 10 0f 00 00 10 0f 00 00 10 8f]; }; mdss_dsi1: qcom,mdss_dsi_ctrl1@996000 { compatible = "qcom,mdss-dsi-ctrl"; label = "MDSS DSI CTRL->1"; cell-index = <1>; reg = <0x996000 0x400>, <0x996400 0x558>, <0x828000 0x108>; reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys"; qcom,timing-db-mode; oled-vdda-supply = <&pm8994_l19>; vddio-supply = <&pm8994_l14>; lab-supply = <&lab_regulator>; ibb-supply = <&ibb_regulator>; qcom,mdss-mdp = <&mdss_mdp>; clocks = <&clock_mmss clk_mdss_byte1_clk>, <&clock_mmss clk_mdss_pclk1_clk>, <&clock_mmss clk_mdss_esc1_clk>, <&clock_mmss clk_byte1_clk_src>, <&clock_mmss clk_pclk1_clk_src>, <&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>, <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>, <&mdss_dsi1_pll clk_dsi1pll_byte_clk_src>, <&mdss_dsi1_pll clk_dsi1pll_pixel_clk_src>, <&mdss_dsi1_pll clk_dsi1pll_shadow_byte_clk_src>, <&mdss_dsi1_pll clk_dsi1pll_shadow_pixel_clk_src>; clock-names = "byte_clk", "pixel_clk", "core_clk", "byte_clk_rcg", "pixel_clk_rcg", "pll_byte_clk_mux", "pll_pixel_clk_mux", "pll_byte_clk_src", "pll_pixel_clk_src", "pll_byte_clk_src", "pll_pixel_clk_src", "pll_shadow_byte_clk_src", "pll_shadow_pixel_clk_src"; qcom,null-insertion-enabled; qcom,platform-strength-ctrl = [ff 06 ff 06 ff 06 ff 06 ff 00]; qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; qcom,platform-lane-config = [00 00 10 0f 00 00 10 0f 00 00 10 0f 00 00 10 0f 00 00 10 8f]; }; }; qcom,mdss_wb_panel { compatible = "qcom,mdss_wb"; qcom,mdss_pan_res = <640 480>; qcom,mdss_pan_bpp = <24>; qcom,mdss-fb-map = <&mdss_fb1>; }; mdss_hdmi_tx: qcom,hdmi_tx@9a0000 { cell-index = <0>; compatible = "qcom,hdmi-tx"; reg = <0x9a0000 0x50c>, <0x70000 0x6158>, <0x9e0000 0xFFF>; reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; hpd-gdsc-supply = <&gdsc_mdss>; qcom,supply-names = "hpd-gdsc"; qcom,min-voltage-level = <0>; qcom,max-voltage-level = <0>; qcom,enable-load = <0>; qcom,disable-load = <0>; clocks = <&clock_mmss clk_mdss_mdp_vote_clk>, <&clock_mmss clk_mdss_ahb_clk>, <&clock_mmss clk_mdss_hdmi_clk>, <&clock_mmss clk_mdss_hdmi_ahb_clk>, <&clock_mmss clk_mdss_extpclk_clk>; clock-names = "mdp_core_clk", "iface_clk", "core_clk", "alt_iface_clk", "extp_clk"; qcom,hdmi-tx-hpd = <&pm8994_mpps 4 0>; qcom,mdss-fb-map = <&mdss_fb2>; qcom,pluggable; hdmi_audio: qcom,msm-hdmi-audio-rx { compatible = "qcom,msm-hdmi-audio-codec-rx"; }; }; mdss_rotator: qcom,mdss_rotator { compatible = "qcom,mdss_rotator"; qcom,mdss-wb-count = <2>; qcom,mdss-has-downscale; qcom,mdss-has-ubwc; qcom,mdss-has-reg-bus; /* Bus Scale Settings */ qcom,msm-bus,name = "mdss_rotator"; qcom,msm-bus,num-cases = <3>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <25 512 0 0>, <25 512 0 6400000>, <25 512 0 6400000>; rot-vdd-supply = <&gdsc_mdss>; rot-mmagic-mdss-gdsc-supply = <&gdsc_mmagic_mdss>; qcom,supply-names = "rot-mmagic-mdss-gdsc", "rot-vdd"; clocks = <&clock_mmss clk_mmss_misc_ahb_clk>, <&clock_mmss clk_mdss_rotator_vote_clk>; clock-names = "iface_clk", "rot_core_clk"; }; };