201 lines
8.7 KiB
Plaintext
201 lines
8.7 KiB
Plaintext
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MSM USB PHY transceivers
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HSUSB PHY
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Required properties:
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- compatible: Should be "qcom,usb-hsphy"
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- reg: Address and length of the register set for the device
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Required regs are:
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"core" : the QSCRATCH base register set
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- <supply-name>-supply: phandle to the regulator device tree node
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Required "supply-name" examples are:
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"vdd" : vdd supply for HSPHY digital circuit operation
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"vdda18" : 1.8v supply for HSPHY
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"vdda33" : 3.3v supply for HSPHY
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- qcom,vdd-voltage-level: This property must be a list of three integer
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values (no, min, max) where each value represents either a voltage in
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microvolts or a value corresponding to voltage corner
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Optional properties:
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- reg: Additional registers
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"tcsr" : top-level CSR register to be written during power-on reset
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initialize the internal MUX that controls whether this PHY is
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used with the USB3 or the USB2 controller.
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- qcom,hsphy-init: Init value used to override HSPHY parameters into
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QSCRATCH register. This 32-bit value represents parameters as follows:
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bits 0-5 PARAMETER_OVERRIDE_A
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bits 6-12 PARAMETER_OVERRIDE_B
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bits 13-19 PARAMETER_OVERRIDE_C
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bits 20-25 PARAMETER_OVERRIDE_D
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- qcom,ext-vbus-id: If present, indicates that the PHY does not handle VBUS and ID changes.
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- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
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the USB PHY and the controller must rely on external VBUS notification in
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order to manually enable the D+ pull-up resistor.
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- qcom,primary-phy: If present, indicates this is a secondary PHY and is
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dependent on the primary PHY referenced by this phandle.
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- qcom,set-pllbtune: If present, PLL tune is required in PHY initialization.
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- qcom,num_ports: Indicates the number of ports that supported by the HS PHY.
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If omitted, defaults to 1
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- qcom,sleep-clk-reset: If present, the HSUSB PHY sleep clock supports the clk_reset
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operation, and should be called during initialization.
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- qcom,vdda-force-on: If present, HW requires a workaround that forces 1.8V and 3.1V
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regulator supplies to be left on even when PHY enters into
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low power mode.
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Example:
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hsphy@f9200000 {
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compatible = "qcom,usb-hsphy";
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reg = <0xf9200000 0xfc000>;
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qcom,hsphy-init = <0x00D191A4>;
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vdd-supply = <&pm8841_s2_corner>;
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vdda18-supply = <&pm8941_l6>;
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vdda33-supply = <&pm8941_l24>;
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qcom,num_of_ports = <3>;
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qcom,vdd-voltage-level = <1 5 7>;
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};
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SSUSB PHY
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Required properties:
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- compatible: Should be "qcom,usb-ssphy" or "qcom,usb-ssphy-qmp-v2"
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- reg: Address and length of the register set for the device
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- <supply-name>-supply: phandle to the regulator device tree node
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Required "supply-name" examples are:
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"vdd" : vdd supply for SSPHY digital circuit operation
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"vdda18" : 1.8v high-voltage analog supply for SSPHY
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- qcom,vdd-voltage-level: This property must be a list of three integer
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values (no, min, max) where each value represents either a voltage in
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microvolts or a value corresponding to voltage corner
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Optional properties:
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- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
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the USB PHY and the controller must rely on external VBUS notification in
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order to manually relay the notification to the SSPHY.
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- qcom,deemphasis-value: This property if present represents ss phy
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deemphasis value to be used for overriding into SSPHY register.
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- qcom,primary-phy: If present, indicates this is a secondary PHY and is
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dependent on the primary PHY referenced by this phandle.
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- qcom,override-pll-calibration: If present, program PHY register to overrride
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the automatic PHY PLL calibration settings.
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- qcom,qmp-misc-config: If present, program PHY miscellaneous device-specific
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registers.
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Example:
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ssphy@f9200000 {
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compatible = "qcom,usb-ssphy";
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reg = <0xf9200000 0xfc000>;
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vdd-supply = <&pm8841_s2_corner>;
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vdda18-supply = <&pm8941_l6>;
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qcom,vdd-voltage-level = <1 5 7>;
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qcom,deemphasis-value = <26>;
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};
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SSUSB-QMP PHY
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Required properties:
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- compatible: Should be "qcom,usb-ssphy-qmp", "qcom,usb-ssphy-qmp-v1" or
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"qcom,usb-ssphy-qmp-v2"
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- reg: Address and length of the register set for the device
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Required regs are:
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"qmp_phy_base" : QMP PHY Base register set.
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- "vls_clamp_reg" : top-level CSR register to be written to enable phy vls
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clamp which allows phy to detect autonomous mode.
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- <supply-name>-supply: phandle to the regulator device tree node
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Required "supply-name" examples are:
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"vdd" : vdd supply for SSPHY digital circuit operation
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"vdda18" : 1.8v high-voltage analog supply for SSPHY
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- qcom,vdd-voltage-level: This property must be a list of three integer
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values (no, min, max) where each value represents either a voltage in
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microvolts or a value corresponding to voltage corner
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Optional properties:
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- reg: Additional register set of address and length to control QMP PHY
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"tcsr_phy_clk_scheme_sel": Read phy clk scheme single ended vs
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differential to determine the value to write to QSERDES_COM_SYSCLK_EN_SEL.
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- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
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the USB PHY and the controller must rely on external VBUS notification in
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order to manually relay the notification to the SSPHY.
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- qcom,emulation: Indicates that we are running on emulation platform.
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- qcom,qmp-phy-init-seq: QMP PHY initialization sequence with reg, diff clk
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value, single ended clk value, delay after register write.
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- qcom,qmp-phy-reg-offset: If present stores phy register offsets in an order
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defined in the phy driver.
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Example:
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ssphy0: ssphy@f9b38000 {
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compatible = "qcom,usb-ssphy-qmp";
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reg = <0xf9b38000 0x16c>,
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<0x01947244 0x4>;
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reg-names = "qmp_phy_base",
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"vls_clamp_reg";
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vdd-supply = <&pmd9635_l4>;
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vdda18-supply = <&pmd9635_l8>;
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qcom,vdd-voltage-level = <0 900000 1050000>;
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qcom,vbus-valid-override;
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};
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QUSB2 High-Speed PHY
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Required properties:
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- compatible: Should be "qcom,qusb2phy"
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- reg: Address and length of the QUSB2 PHY register set
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- reg-names: Should be "qusb_phy_base".
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- <supply-name>-supply: phandle to the regulator device tree node
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Required supplies are:
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"vdd" : vdd supply for digital circuit operation
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"vdda18" : 1.8v high-voltage analog supply
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"vdda33" : 3.3v high-voltage analog supply
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- qcom,vdd-voltage-level: This property must be a list of three integer
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values (no, min, max) where each value represents either a voltage in
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microvolts or a value corresponding to voltage corner
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- clocks: a list of phandles to the PHY clocks. Use as per
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
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property. Required clocks are "cfg_ahb_clk" and "phy_reset".
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- phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.
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Optional properties:
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- reg: Address and length register set to control QUSB2 PHY
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"qscratch_base" : QSCRATCH base register set.
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"tune2_efuse_addr": EFUSE based register address to read TUNE2 parameter.
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via the QSCRATCH interface.
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"emu_phy_base" : phy base address used for programming emulation target phy.
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"ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.
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"tcsr_phy_clk_scheme_sel": address used to determine QUSB PHY clk source.
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- reg-names: Should be "qscratch_base". The qscratch register bank
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allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w
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control in device mode. The reg-names property is required if the
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reg property is specified.
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- qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.
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- qcom,emu-init-seq : emulation initialization sequence with value,reg pair.
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- qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair.
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- qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair.
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- qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register
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- qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble
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- qcom,emulation: Indicates that we are running on emulation platform.
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- qcom,hold-reset: Indicates that hold QUSB PHY into reset state.
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- qcom,enable-dpdm-pulsing: enables dp and dm pulsing for PMIC driver to
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perform charger detection.
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Example:
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qusb_phy: qusb@f9b39000 {
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compatible = "qcom,qusb2phy";
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reg = <0x00079000 0x7000>,
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<0x08af8800 0x400>;
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reg-names = "qusb_phy_base",
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"qscratch_base";
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vdd-supply = <&pm8994_s2_corner>;
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vdda18-supply = <&pm8994_l6>;
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vdda33-supply = <&pm8994_l24>;
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qcom,vdd-voltage-level = <1 5 7>;
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qcom,tune2-efuse-bit-pos = <21>;
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qcom,tune2-efuse-num-bits = <3>;
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clocks = <&clock_rpm clk_ln_bb_clk>,
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<&clock_gcc clk_gcc_rx2_usb1_clkref_clk>,
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<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
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<&clock_gcc clk_gcc_qusb2_phy_reset>;
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clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset";
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};
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