MSM USB PHY transceivers HSUSB PHY Required properties: - compatible: Should be "qcom,usb-hsphy" - reg: Address and length of the register set for the device Required regs are: "core" : the QSCRATCH base register set - -supply: phandle to the regulator device tree node Required "supply-name" examples are: "vdd" : vdd supply for HSPHY digital circuit operation "vdda18" : 1.8v supply for HSPHY "vdda33" : 3.3v supply for HSPHY - qcom,vdd-voltage-level: This property must be a list of three integer values (no, min, max) where each value represents either a voltage in microvolts or a value corresponding to voltage corner Optional properties: - reg: Additional registers "tcsr" : top-level CSR register to be written during power-on reset initialize the internal MUX that controls whether this PHY is used with the USB3 or the USB2 controller. - qcom,hsphy-init: Init value used to override HSPHY parameters into QSCRATCH register. This 32-bit value represents parameters as follows: bits 0-5 PARAMETER_OVERRIDE_A bits 6-12 PARAMETER_OVERRIDE_B bits 13-19 PARAMETER_OVERRIDE_C bits 20-25 PARAMETER_OVERRIDE_D - qcom,ext-vbus-id: If present, indicates that the PHY does not handle VBUS and ID changes. - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to the USB PHY and the controller must rely on external VBUS notification in order to manually enable the D+ pull-up resistor. - qcom,primary-phy: If present, indicates this is a secondary PHY and is dependent on the primary PHY referenced by this phandle. - qcom,set-pllbtune: If present, PLL tune is required in PHY initialization. - qcom,num_ports: Indicates the number of ports that supported by the HS PHY. If omitted, defaults to 1 - qcom,sleep-clk-reset: If present, the HSUSB PHY sleep clock supports the clk_reset operation, and should be called during initialization. - qcom,vdda-force-on: If present, HW requires a workaround that forces 1.8V and 3.1V regulator supplies to be left on even when PHY enters into low power mode. Example: hsphy@f9200000 { compatible = "qcom,usb-hsphy"; reg = <0xf9200000 0xfc000>; qcom,hsphy-init = <0x00D191A4>; vdd-supply = <&pm8841_s2_corner>; vdda18-supply = <&pm8941_l6>; vdda33-supply = <&pm8941_l24>; qcom,num_of_ports = <3>; qcom,vdd-voltage-level = <1 5 7>; }; SSUSB PHY Required properties: - compatible: Should be "qcom,usb-ssphy" or "qcom,usb-ssphy-qmp-v2" - reg: Address and length of the register set for the device - -supply: phandle to the regulator device tree node Required "supply-name" examples are: "vdd" : vdd supply for SSPHY digital circuit operation "vdda18" : 1.8v high-voltage analog supply for SSPHY - qcom,vdd-voltage-level: This property must be a list of three integer values (no, min, max) where each value represents either a voltage in microvolts or a value corresponding to voltage corner Optional properties: - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to the USB PHY and the controller must rely on external VBUS notification in order to manually relay the notification to the SSPHY. - qcom,deemphasis-value: This property if present represents ss phy deemphasis value to be used for overriding into SSPHY register. - qcom,primary-phy: If present, indicates this is a secondary PHY and is dependent on the primary PHY referenced by this phandle. - qcom,override-pll-calibration: If present, program PHY register to overrride the automatic PHY PLL calibration settings. - qcom,qmp-misc-config: If present, program PHY miscellaneous device-specific registers. Example: ssphy@f9200000 { compatible = "qcom,usb-ssphy"; reg = <0xf9200000 0xfc000>; vdd-supply = <&pm8841_s2_corner>; vdda18-supply = <&pm8941_l6>; qcom,vdd-voltage-level = <1 5 7>; qcom,deemphasis-value = <26>; }; SSUSB-QMP PHY Required properties: - compatible: Should be "qcom,usb-ssphy-qmp", "qcom,usb-ssphy-qmp-v1" or "qcom,usb-ssphy-qmp-v2" - reg: Address and length of the register set for the device Required regs are: "qmp_phy_base" : QMP PHY Base register set. - "vls_clamp_reg" : top-level CSR register to be written to enable phy vls clamp which allows phy to detect autonomous mode. - -supply: phandle to the regulator device tree node Required "supply-name" examples are: "vdd" : vdd supply for SSPHY digital circuit operation "vdda18" : 1.8v high-voltage analog supply for SSPHY - qcom,vdd-voltage-level: This property must be a list of three integer values (no, min, max) where each value represents either a voltage in microvolts or a value corresponding to voltage corner Optional properties: - reg: Additional register set of address and length to control QMP PHY "tcsr_phy_clk_scheme_sel": Read phy clk scheme single ended vs differential to determine the value to write to QSERDES_COM_SYSCLK_EN_SEL. - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to the USB PHY and the controller must rely on external VBUS notification in order to manually relay the notification to the SSPHY. - qcom,emulation: Indicates that we are running on emulation platform. - qcom,qmp-phy-init-seq: QMP PHY initialization sequence with reg, diff clk value, single ended clk value, delay after register write. - qcom,qmp-phy-reg-offset: If present stores phy register offsets in an order defined in the phy driver. Example: ssphy0: ssphy@f9b38000 { compatible = "qcom,usb-ssphy-qmp"; reg = <0xf9b38000 0x16c>, <0x01947244 0x4>; reg-names = "qmp_phy_base", "vls_clamp_reg"; vdd-supply = <&pmd9635_l4>; vdda18-supply = <&pmd9635_l8>; qcom,vdd-voltage-level = <0 900000 1050000>; qcom,vbus-valid-override; }; QUSB2 High-Speed PHY Required properties: - compatible: Should be "qcom,qusb2phy" - reg: Address and length of the QUSB2 PHY register set - reg-names: Should be "qusb_phy_base". - -supply: phandle to the regulator device tree node Required supplies are: "vdd" : vdd supply for digital circuit operation "vdda18" : 1.8v high-voltage analog supply "vdda33" : 3.3v high-voltage analog supply - qcom,vdd-voltage-level: This property must be a list of three integer values (no, min, max) where each value represents either a voltage in microvolts or a value corresponding to voltage corner - clocks: a list of phandles to the PHY clocks. Use as per Documentation/devicetree/bindings/clock/clock-bindings.txt - clock-names: Names of the clocks in 1-1 correspondence with the "clocks" property. Required clocks are "cfg_ahb_clk" and "phy_reset". - phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode. Optional properties: - reg: Address and length register set to control QUSB2 PHY "qscratch_base" : QSCRATCH base register set. "tune2_efuse_addr": EFUSE based register address to read TUNE2 parameter. via the QSCRATCH interface. "emu_phy_base" : phy base address used for programming emulation target phy. "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset. "tcsr_phy_clk_scheme_sel": address used to determine QUSB PHY clk source. - reg-names: Should be "qscratch_base". The qscratch register bank allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w control in device mode. The reg-names property is required if the reg property is specified. - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair. - qcom,emu-init-seq : emulation initialization sequence with value,reg pair. - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair. - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair. - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble - qcom,emulation: Indicates that we are running on emulation platform. - qcom,hold-reset: Indicates that hold QUSB PHY into reset state. - qcom,enable-dpdm-pulsing: enables dp and dm pulsing for PMIC driver to perform charger detection. Example: qusb_phy: qusb@f9b39000 { compatible = "qcom,qusb2phy"; reg = <0x00079000 0x7000>, <0x08af8800 0x400>; reg-names = "qusb_phy_base", "qscratch_base"; vdd-supply = <&pm8994_s2_corner>; vdda18-supply = <&pm8994_l6>; vdda33-supply = <&pm8994_l24>; qcom,vdd-voltage-level = <1 5 7>; qcom,tune2-efuse-bit-pos = <21>; qcom,tune2-efuse-num-bits = <3>; clocks = <&clock_rpm clk_ln_bb_clk>, <&clock_gcc clk_gcc_rx2_usb1_clkref_clk>, <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>, <&clock_gcc clk_gcc_qusb2_phy_reset>; clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset"; };