2024-09-09 08:52:07 +00:00
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synopsys DWC3 CORE
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DWC3- USB3 CONTROLLER
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Required properties:
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2024-09-09 08:57:42 +00:00
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- compatible: must be "snps,dwc3"
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2024-09-09 08:52:07 +00:00
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- reg : Address and length of the register set for the device
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- interrupts: Interrupts used by the dwc3 controller.
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Optional properties:
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- usb-phy : array of phandle for the PHY device. The first element
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in the array is expected to be a handle to the USB2/HS PHY and
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the second element is expected to be a handle to the USB3/SS PHY
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- phys: from the *Generic PHY* bindings
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- phy-names: from the *Generic PHY* bindings
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- tx-fifo-resize: determines if the FIFO *has* to be reallocated.
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- snps,nominal-elastic-buffer: When set, the nominal elastic buffer setting
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is used. By default, the half-full setting is used.
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- snps,usb3-u1u2-disable: If present, disable u1u2 low power modes for DWC3 core controller in SS mode.
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- snps,bus-suspend-enable: If present then controller supports low power mode
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during bus suspend.
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- snps,disable-clk-gating: If present, disable controller's internal clock gating. Default it is enabled.
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- snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
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- snps,lpm-nyet-threshold: LPM NYET threshold
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- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
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utmi_l1_suspend_n, false when asserts utmi_sleep_n
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- snps,hird-threshold: HIRD threshold
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- snps,num-normal-evt-buffs: If present, specifies number of normal event buffers. Default is 1.
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- snps,num-gsi-evt-buffs: If present, specifies number of GSI based hardware accelerated event buffers.
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1 event buffer is needed per h/w accelerated endpoint.
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2024-09-09 08:52:07 +00:00
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This is usually a subnode to DWC3 glue to which it is connected.
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dwc3@4a030000 {
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compatible = "snps,dwc3";
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reg = <0x4a030000 0xcfff>;
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interrupts = <0 92 4>
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usb-phy = <&usb2_phy>, <&usb3,phy>;
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tx-fifo-resize;
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snps,usb3-u1u2-disable;
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snps,num-gsi-evt-buffs = <0x2>;
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2024-09-09 08:52:07 +00:00
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};
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