100 lines
4.3 KiB
Plaintext
100 lines
4.3 KiB
Plaintext
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* Qualcomm MSM FD
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Face detection hardware block.
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The Face Detection Hardware Block will offload processing
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on the host and also reduce power consumption.
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Supports:
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Front and back camera face detection concurrently.
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Sizes: QVGA, VGA, WQVGA, WVGA at 20 pix minimum face size.
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Required properties:
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- compatible:
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- "qcom,face-detection"
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- reg: offset and length of the register set for the device.
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- reg-names: should specify relevant names to each reg property defined.
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- "fd_core" - FD CORE hardware register set.
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- "fd_misc" - FD MISC hardware register set.
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- "fd_vbif" - FD VBIF hardware register set.
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- interrupts: should contain the fd interrupts. From fd cores with
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revisions 0x10010000 and higher, power collapse sequence is required.
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Face detection misc irq is needed to perform power collapse.
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- interrupt-names: should specify relevant names to each interrupts
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property defined.
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- vdd-supply: phandle to GDSC regulator controlling face detection hw.
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- clocks: list of entries each of which contains:
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- phandle to the clock controller.
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- macro containing clock's name in hardware.
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- clock-names: should specify relevant names to each clocks
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property defined.
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Optional properties:
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- clock-rates: should specify clock rates in Hz to each clocks
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property defined.
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If we want to have different operating clock frequencies we can define
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rate levels. They should be defined in incremental order.
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- qcom,bus-bandwidth-vectors: Specifies instant and average bus bandwidth
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vectors per clock rate.
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Each of entries contains:
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- ab. Average bus bandwidth (Bps).
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- ib. Instantaneous bus bandwidth (Bps).
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- mmagic-vdd-supply: phandle to GDSC regulator controlling mmagic.
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- camss-vdd-supply: phandle to GDSC regulator controlling camss.
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- qcom,fd-core-reg-settings: relative address offsets and value pairs for
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FD CORE registers and bit mask.
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Format: <reg_addr_offset reg_value reg_mask>
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- qcom,fd-misc-reg-settings: relative address offsets and value pairs for
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FD MISC registers and bit mask.
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Format: <reg_addr_offset reg_value reg_mask>
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- qcom,fd-vbif-reg-settings: relative address offsets and value pairs for
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FD VBIF registers and bit mask.
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Format: <reg_addr_offset reg_value reg_mask>
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Example:
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qcom,fd@fd878000 {
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compatible = "qcom,face-detection";
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reg = <0xfd878000 0x800>,
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<0xfd87c000 0x800>,
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<0xfd860000 0x1000>;
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reg-names = "fd_core", "fd_misc", "fd_vbif";
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interrupts = <0 316 0>;
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interrupt-names = "fd";
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mmagic-vdd-supply = <&gdsc_mmagic_camss>;
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camss-vdd-supply = <&gdsc_camss_top>;
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vdd-supply = <&gdsc_fd>;
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qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
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clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
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<&clock_gcc clk_mmssnoc_axi_clk>,
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<&clock_mmss clk_mmagic_camss_axi_clk>,
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<&clock_mmss clk_camss_top_ahb_clk>,
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<&clock_mmss clk_fd_core_clk_src>,
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<&clock_mmss clk_fd_core_clk>,
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<&clock_mmss clk_fd_core_uar_clk>,
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<&clock_mmss clk_fd_ahb_clk>,
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<&clock_mmss clk_smmu_cpp_axi_clk>,
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<&clock_mmss clk_camss_ahb_clk>,
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<&clock_mmss clk_camss_cpp_axi_clk>,
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<&clock_mmss clk_camss_cpp_vbif_ahb_clk>,
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<&clock_mmss clk_smmu_cpp_ahb_clk>;
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clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk" ,
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"mmagic_camss_axi_clk", "camss_top_ahb_clk",
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"fd_core_clk_src", "fd_core_clk",
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"fd_core_uar_clk", "fd_ahb_clk",
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"smmu_cpp_axi_clk", "camss_ahb_clk",
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"camss_cpp_axi_clk", "cpp_vbif_ahb_clk",
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"smmu_cpp_ahb_clk";
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clock-rates = <0 0 0 0 400000000 400000000 400000000 80000000 0 0 0 0 0>;
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qcom,bus-bandwidth-vectors = <13000000 13000000>,
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<45000000 45000000>,
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<90000000 90000000>;
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qcom,fd-vbif-reg-settings = <0x20 0x10000000 0x30000000>,
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<0x24 0x10000000 0x30000000>,
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<0x28 0x10000000 0x30000000>,
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<0x2c 0x10000000 0x30000000>;
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qcom,fd-misc-reg-settings = <0x20 0x2 0x3>,
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<0x24 0x2 0x3>;
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qcom,fd-core-reg-settings = <0x8 0x20 0xffffffff>;
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};
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