103 lines
3.9 KiB
Plaintext
103 lines
3.9 KiB
Plaintext
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Qualcomm MDSS pll for DSI/EDP/HDMI
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mdss-pll is a pll controller device which supports pll devices that
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are compatable with MIPI display serial interface specification,
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HDMI and edp.
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Required properties:
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- compatible: Compatible name used in the driver. Should be one of:
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"qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939",
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"qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994",
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"qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",
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"qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994",
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"qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",
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"qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",
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"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
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"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_dsi_pll_8952",
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"qcom,mdss_dsi_pll_8937", "qcom,mdss_hdmi_pll_8996_v3_1p8",
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"qcom,mdss_dsi_pll_titanium"
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- cell-index: Specifies the controller used
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- reg: offset and length of the register set for the device.
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- reg-names : names to refer to register sets related to this device
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- gdsc-supply: Phandle for gdsc regulator device node.
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- vddio-supply: Phandle for vddio regulator device node.
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- clocks: List of Phandles for clock device nodes
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needed by the device.
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- clock-names: List of clock names needed by the device.
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- clock-rate: List of clock rates in Hz.
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Optional properties:
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- label: A string used to describe the driver used.
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- vcca-supply: Phandle for vcca regulator device node.
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- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled.
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- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread"
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or "center-spread". Default is "down-spread" if it is not specified.
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- qcom,ssc-frequency-hz: Integer property to specify the spread frequency
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to be programmed for the SSC.
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- qcom,ssc-ppm: Integer property to specify the Parts per Million
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value of SSC.
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- qcom,platform-supply-entries: A node that lists the elements of the supply. There
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can be more than one instance of this binding,
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in which case the entry would be appended with
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the supply entry index.
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e.g. qcom,platform-supply-entry@0
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- reg: offset and length of the register set for the device.
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-- qcom,supply-name: name of the supply (vdd/vdda/vddio)
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-- qcom,supply-min-voltage: minimum voltage level (uV)
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-- qcom,supply-max-voltage: maximum voltage level (uV)
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-- qcom,supply-enable-load: load drawn (uA) from enabled supply
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-- qcom,supply-disable-load: load drawn (uA) from disabled supply
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-- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
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-- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
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-- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
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-- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
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Example:
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mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 {
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compatible = "qcom,mdss_dsi_pll_8974";
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label = "MDSS DSI 0 PLL";
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cell-index = <0>;
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reg = <0xfd922A00 0xD4>,
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<0xfd922900 0x64>,
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<0xfd8c2300 0x8>;
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reg-names = "pll_base", "dynamic_pll_base", "gdsc_base";
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gdsc-supply = <&gdsc_mdss>;
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vddio-supply = <&pm8941_l12>;
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vcca-supply = <&pm8941_l28>;
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clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,
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<&clock_gcc clk_gcc_mdss_ahb_clk>,
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<&clock_gcc clk_gcc_mdss_axi_clk>;
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clock-names = "mdp_core_clk", "iface_clk", "bus_clk";
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clock-rate = <0>, <0>, <0>;
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qcom,dsi-pll-slave;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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qcom,ssc-frequency-hz = <30000>;
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qcom,ssc-ppm = <5000>;
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vddio";
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qcom,supply-min-voltage = <1800000>;
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qcom,supply-max-voltage = <1800000>;
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qcom,supply-enable-load = <100000>;
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qcom,supply-disable-load = <100>;
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qcom,supply-pre-on-sleep = <0>;
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qcom,supply-post-on-sleep = <20>;
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qcom,supply-pre-off-sleep = <0>;
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qcom,supply-post-off-sleep = <0>;
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};
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};
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};
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