38 lines
1.5 KiB
Plaintext
38 lines
1.5 KiB
Plaintext
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* MSM PM-8x60
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PM-8x60 is the low power management device for MSM (Snapdragon class) chipsets.
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This device sets up different components to do low power modes and registers with
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the kernel to be notified of idle and suspend states and when called, follows
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through the set of instructions in putting the application cores to the lowest
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power mode possible.
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The PC debug counter reserves 16 registers in the IMEM memory space which maintains
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a count on the state of power collapse on each core. This count will be useful to
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debug the power collapse state on each core.
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The required properties for PM-8x60 are:
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- compatible: "qcom,pm-8x60"
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The optional properties are:
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- reg: physical IMEM address reserved for PC counters and the size
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- qcom,use-sync-timer: Indicates whether the target uses the synchronized QTimer.
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- qcom,pc-mode: Indicates the type of power collapse used by the target. The
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valid values for this are:
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"tz_l2_int" (Power collapse terminates in TZ; integrated L2 cache controller)
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"no_tz_l2_ext", (Power collapse doesn't terminate in TZ; external L2 cache controller)
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"tz_l2_ext" (Power collapse terminates in TZ; external L2 cache controller)
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- qcom,saw-turns-off-pll: Version of SAW2.1 or can turn off the HFPLL, when
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doing power collapse and so the core need to switch to Global PLL before
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PC.
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- qcom,pc-resets-timer: Indicates that the timer gets reset during power collapse.
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Example:
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qcom,pm-8x60@fe800664 {
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compatible = "qcom,pm-8x60";
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reg = <0xfe800664 0x40>;
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qcom,pc-mode = "tz_l2_int";
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qcom,use-sync-timer;
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};
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