276 lines
9.1 KiB
C
276 lines
9.1 KiB
C
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/*
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* ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
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*
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* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
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*
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* Author: David Lopo
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Description: MIPS USB IP core family device controller
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* Structures, registers and logging macros
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*/
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#ifndef _CI13XXX_h_
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#define _CI13XXX_h_
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/******************************************************************************
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* DEFINE
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*****************************************************************************/
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#define CI13XXX_PAGE_SIZE 4096ul /* page size for TD's */
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#define ENDPT_MAX (32)
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#define CTRL_PAYLOAD_MAX (64)
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#define RX (0) /* similar to USB_DIR_OUT but can be used as an index */
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#define TX (1) /* similar to USB_DIR_IN but can be used as an index */
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/* UDC private data:
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* 16MSb - Vendor ID | 16 LSb Vendor private data
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*/
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#define CI13XX_REQ_VENDOR_ID(id) (id & 0xFFFF0000UL)
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#define MSM_ETD_TYPE BIT(1)
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#define MSM_EP_PIPE_ID_RESET_VAL 0x1F001F
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/******************************************************************************
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* STRUCTURES
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*****************************************************************************/
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/* DMA layout of transfer descriptors */
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struct ci13xxx_td {
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/* 0 */
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u32 next;
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#define TD_TERMINATE BIT(0)
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#define TD_ADDR_MASK (0xFFFFFFEUL << 5)
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/* 1 */
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u32 token;
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#define TD_STATUS (0x00FFUL << 0)
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#define TD_STATUS_TR_ERR BIT(3)
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#define TD_STATUS_DT_ERR BIT(5)
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#define TD_STATUS_HALTED BIT(6)
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#define TD_STATUS_ACTIVE BIT(7)
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#define TD_MULTO (0x0003UL << 10)
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#define TD_IOC BIT(15)
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#define TD_TOTAL_BYTES (0x7FFFUL << 16)
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/* 2 */
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u32 page[5];
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#define TD_CURR_OFFSET (0x0FFFUL << 0)
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#define TD_FRAME_NUM (0x07FFUL << 0)
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#define TD_RESERVED_MASK (0x0FFFUL << 0)
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} __attribute__ ((packed, aligned(4)));
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/* DMA layout of queue heads */
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struct ci13xxx_qh {
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/* 0 */
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u32 cap;
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#define QH_IOS BIT(15)
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#define QH_MAX_PKT (0x07FFUL << 16)
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#define QH_ZLT BIT(29)
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#define QH_MULT (0x0003UL << 30)
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#define QH_MULT_SHIFT 11
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/* 1 */
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u32 curr;
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/* 2 - 8 */
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struct ci13xxx_td td;
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/* 9 */
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u32 RESERVED;
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struct usb_ctrlrequest setup;
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} __attribute__ ((packed, aligned(4)));
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/* cache of larger request's original attributes */
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struct ci13xxx_multi_req {
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unsigned len;
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unsigned actual;
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void *buf;
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};
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/* Extension of usb_request */
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struct ci13xxx_req {
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struct usb_request req;
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unsigned map;
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struct list_head queue;
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struct ci13xxx_td *ptr;
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dma_addr_t dma;
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struct ci13xxx_td *zptr;
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dma_addr_t zdma;
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struct ci13xxx_multi_req multi;
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};
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/* Extension of usb_ep */
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struct ci13xxx_ep {
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struct usb_ep ep;
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const struct usb_endpoint_descriptor *desc;
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u8 dir;
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u8 num;
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u8 type;
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char name[16];
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struct {
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struct list_head queue;
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struct ci13xxx_qh *ptr;
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dma_addr_t dma;
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} qh;
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struct list_head rw_queue;
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int wedge;
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/* global resources */
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spinlock_t *lock;
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struct device *device;
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struct dma_pool *td_pool;
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struct ci13xxx_td *last_zptr;
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dma_addr_t last_zdma;
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unsigned long dTD_update_fail_count;
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unsigned long prime_fail_count;
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int prime_timer_count;
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struct timer_list prime_timer;
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bool multi_req;
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};
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struct ci13xxx;
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struct ci13xxx_udc_driver {
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const char *name;
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unsigned long flags;
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unsigned int nz_itc;
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#define CI13XXX_REGS_SHARED BIT(0)
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#define CI13XXX_REQUIRE_TRANSCEIVER BIT(1)
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#define CI13XXX_PULLUP_ON_VBUS BIT(2)
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#define CI13XXX_DISABLE_STREAMING BIT(3)
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#define CI13XXX_ZERO_ITC BIT(4)
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#define CI13XXX_IS_OTG BIT(5)
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#define CI13XXX_CONTROLLER_RESET_EVENT 0
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#define CI13XXX_CONTROLLER_CONNECT_EVENT 1
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#define CI13XXX_CONTROLLER_SUSPEND_EVENT 2
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#define CI13XXX_CONTROLLER_REMOTE_WAKEUP_EVENT 3
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#define CI13XXX_CONTROLLER_RESUME_EVENT 4
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#define CI13XXX_CONTROLLER_DISCONNECT_EVENT 5
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#define CI13XXX_CONTROLLER_UDC_STARTED_EVENT 6
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void (*notify_event) (struct ci13xxx *udc, unsigned event);
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bool (*in_lpm) (struct ci13xxx *udc);
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void (*set_fpr_flag) (struct ci13xxx *udc);
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};
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/* CI13XXX UDC descriptor & global resources */
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struct ci13xxx {
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spinlock_t *lock; /* ctrl register bank access */
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void __iomem *regs; /* registers address space */
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struct dma_pool *qh_pool; /* DMA pool for queue heads */
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struct dma_pool *td_pool; /* DMA pool for transfer descs */
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struct usb_request *status; /* ep0 status request */
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void *status_buf;/* GET_STATUS buffer */
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struct usb_gadget gadget; /* USB slave device */
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struct ci13xxx_ep ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
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u32 ep0_dir; /* ep0 direction */
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#define ep0out ci13xxx_ep[0]
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#define ep0in ci13xxx_ep[hw_ep_max / 2]
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u8 suspended; /* suspended by the host */
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u8 configured; /* is device configured */
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u8 test_mode; /* the selected test mode */
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bool rw_pending; /* Remote wakeup pending flag */
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struct delayed_work rw_work; /* remote wakeup delayed work */
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struct usb_gadget_driver *driver; /* 3rd party gadget driver */
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struct ci13xxx_udc_driver *udc_driver; /* device controller driver */
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int vbus_active; /* is VBUS active */
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int softconnect; /* is pull-up enable allowed */
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unsigned long dTD_update_fail_count;
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struct usb_phy *transceiver; /* Transceiver struct */
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bool skip_flush; /* skip flushing remaining EP
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upon flush timeout for the
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first EP. */
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};
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/******************************************************************************
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* REGISTERS
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*****************************************************************************/
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/* register size */
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#define REG_BITS (32)
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/* HCCPARAMS */
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#define HCCPARAMS_LEN BIT(17)
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/* DCCPARAMS */
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#define DCCPARAMS_DEN (0x1F << 0)
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#define DCCPARAMS_DC BIT(7)
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/* TESTMODE */
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#define TESTMODE_FORCE BIT(0)
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/* USBCMD */
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#define USBCMD_RS BIT(0)
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#define USBCMD_RST BIT(1)
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#define USBCMD_SUTW BIT(13)
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#define USBCMD_ATDTW BIT(14)
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/* USBSTS & USBINTR */
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#define USBi_UI BIT(0)
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#define USBi_UEI BIT(1)
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#define USBi_PCI BIT(2)
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#define USBi_URI BIT(6)
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#define USBi_SLI BIT(8)
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/* DEVICEADDR */
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#define DEVICEADDR_USBADRA BIT(24)
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#define DEVICEADDR_USBADR (0x7FUL << 25)
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/* PORTSC */
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#define PORTSC_FPR BIT(6)
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#define PORTSC_SUSP BIT(7)
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#define PORTSC_HSP BIT(9)
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#define PORTSC_PTC (0x0FUL << 16)
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/* DEVLC */
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#define DEVLC_PSPD (0x03UL << 25)
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#define DEVLC_PSPD_HS (0x02UL << 25)
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/* USBMODE */
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#define USBMODE_CM (0x03UL << 0)
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#define USBMODE_CM_IDLE (0x00UL << 0)
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#define USBMODE_CM_DEVICE (0x02UL << 0)
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#define USBMODE_CM_HOST (0x03UL << 0)
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#define USBMODE_SLOM BIT(3)
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#define USBMODE_SDIS BIT(4)
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#define USBCMD_ITC(n) (n << 16) /* n = 0, 1, 2, 4, 8, 16, 32, 64 */
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#define USBCMD_ITC_MASK (0xFF << 16)
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/* ENDPTCTRL */
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#define ENDPTCTRL_RXS BIT(0)
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#define ENDPTCTRL_RXT (0x03UL << 2)
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#define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */
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#define ENDPTCTRL_RXE BIT(7)
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#define ENDPTCTRL_TXS BIT(16)
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#define ENDPTCTRL_TXT (0x03UL << 18)
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#define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */
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#define ENDPTCTRL_TXE BIT(23)
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/******************************************************************************
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* LOGGING
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*****************************************************************************/
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#define ci13xxx_printk(level, format, args...) \
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do { \
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if (_udc == NULL) \
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printk(level "[%s] " format "\n", __func__, ## args); \
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else \
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dev_printk(level, _udc->gadget.dev.parent, \
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"[%s] " format "\n", __func__, ## args); \
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} while (0)
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#ifndef err
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#define err(format, args...) ci13xxx_printk(KERN_ERR, format, ## args)
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#endif
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#define warn(format, args...) ci13xxx_printk(KERN_WARNING, format, ## args)
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#define info(format, args...) ci13xxx_printk(KERN_INFO, format, ## args)
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#ifdef TRACE
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#define trace(format, args...) ci13xxx_printk(KERN_DEBUG, format, ## args)
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#define dbg_trace(format, args...) dev_dbg(dev, format, ##args)
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#else
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#define trace(format, args...) do {} while (0)
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#define dbg_trace(format, args...) do {} while (0)
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#endif
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#endif /* _CI13XXX_h_ */
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