315 lines
12 KiB
Diff
315 lines
12 KiB
Diff
Upstream-Status: Pending
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Backport of bugfix in gcc-4.6.x and mainline that address bug 44618 in
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which we get wrong code generation with -Os -frename-registers.
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2011-06-13 Edmar Wienskoski <edmar@freescale.com>
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PR target/44618
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* config/rs6000/rs6000.md (save_gpregs_<mode>): Replaced pattern
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with a set of similar patterns, where the MATCH_OPERAND for the
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function argument is replaced with individual references to hardware
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registers.
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(save_fpregs_<mode>): Ditto
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(restore_gpregs_<mode>): Ditto
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(return_and_restore_gpregs_<mode>): Ditto
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(return_and_restore_fpregs_<mode>): Ditto
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(return_and_restore_fpregs_aix_<mode>): Ditto
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* gcc.target/powerpc/outofline_rnreg.c: New testcase.
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Index: gcc-4.5.1/gcc/config/rs6000/rs6000.md
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===================================================================
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--- gcc-4.5.1.orig/gcc/config/rs6000/rs6000.md
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+++ gcc-4.5.1/gcc/config/rs6000/rs6000.md
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@@ -15256,25 +15256,88 @@
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"{stm|stmw} %2,%1"
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[(set_attr "type" "store_ux")])
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-(define_insn "*save_gpregs_<mode>"
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+; The following comment applies to:
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+; save_gpregs_*
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+; save_fpregs_*
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+; restore_gpregs*
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+; return_and_restore_gpregs*
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+; return_and_restore_fpregs*
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+; return_and_restore_fpregs_aix*
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+;
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+; The out-of-line save / restore functions expects one input argument.
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+; Since those are not standard call_insn's, we must avoid using
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+; MATCH_OPERAND for that argument. That way the register rename
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+; optimization will not try to rename this register.
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+; Each pattern is repeated for each possible register number used in
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+; various ABIs (r11, r1, and for some functions r12)
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+
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+(define_insn "*save_gpregs_<mode>_r11"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(clobber (reg:P 65))
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+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
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+ (use (reg:P 11))
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+ (set (match_operand:P 2 "memory_operand" "=m")
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+ (match_operand:P 3 "gpc_reg_operand" "r"))])]
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+ ""
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+ "bl %1"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*save_gpregs_<mode>_r12"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(clobber (reg:P 65))
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+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
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+ (use (reg:P 12))
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+ (set (match_operand:P 2 "memory_operand" "=m")
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+ (match_operand:P 3 "gpc_reg_operand" "r"))])]
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+ ""
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+ "bl %1"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*save_gpregs_<mode>_r1"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(clobber (reg:P 65))
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+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
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+ (use (reg:P 1))
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+ (set (match_operand:P 2 "memory_operand" "=m")
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+ (match_operand:P 3 "gpc_reg_operand" "r"))])]
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+ ""
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+ "bl %1"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*save_fpregs_<mode>_r11"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(clobber (reg:P 65))
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+ (use (match_operand:P 1 "symbol_ref_operand" "s"))
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+ (use (reg:P 11))
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+ (set (match_operand:DF 2 "memory_operand" "=m")
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+ (match_operand:DF 3 "gpc_reg_operand" "d"))])]
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+ ""
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+ "bl %1"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*save_fpregs_<mode>_r12"
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[(match_parallel 0 "any_parallel_operand"
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[(clobber (reg:P 65))
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(use (match_operand:P 1 "symbol_ref_operand" "s"))
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- (use (match_operand:P 2 "gpc_reg_operand" "r"))
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- (set (match_operand:P 3 "memory_operand" "=m")
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- (match_operand:P 4 "gpc_reg_operand" "r"))])]
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+ (use (reg:P 12))
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+ (set (match_operand:DF 2 "memory_operand" "=m")
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+ (match_operand:DF 3 "gpc_reg_operand" "d"))])]
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""
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"bl %1"
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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-(define_insn "*save_fpregs_<mode>"
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+(define_insn "*save_fpregs_<mode>_r1"
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[(match_parallel 0 "any_parallel_operand"
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[(clobber (reg:P 65))
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(use (match_operand:P 1 "symbol_ref_operand" "s"))
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- (use (match_operand:P 2 "gpc_reg_operand" "r"))
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- (set (match_operand:DF 3 "memory_operand" "=m")
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- (match_operand:DF 4 "gpc_reg_operand" "d"))])]
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+ (use (reg:P 1))
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+ (set (match_operand:DF 2 "memory_operand" "=m")
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+ (match_operand:DF 3 "gpc_reg_operand" "d"))])]
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""
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"bl %1"
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[(set_attr "type" "branch")
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@@ -15372,52 +15435,156 @@
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; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
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; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
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-(define_insn "*restore_gpregs_<mode>"
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+; The following comment applies to:
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+; save_gpregs_*
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+; save_fpregs_*
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+; restore_gpregs*
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+; return_and_restore_gpregs*
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+; return_and_restore_fpregs*
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+; return_and_restore_fpregs_aix*
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+;
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+; The out-of-line save / restore functions expects one input argument.
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+; Since those are not standard call_insn's, we must avoid using
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+; MATCH_OPERAND for that argument. That way the register rename
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+; optimization will not try to rename this register.
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+; Each pattern is repeated for each possible register number used in
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+; various ABIs (r11, r1, and for some functions r12)
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+
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+(define_insn "*restore_gpregs_<mode>_r11"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(clobber (match_operand:P 1 "register_operand" "=l"))
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+ (use (match_operand:P 2 "symbol_ref_operand" "s"))
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+ (use (reg:P 11))
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+ (set (match_operand:P 3 "gpc_reg_operand" "=r")
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+ (match_operand:P 4 "memory_operand" "m"))])]
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+ ""
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+ "bl %2"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*restore_gpregs_<mode>_r12"
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[(match_parallel 0 "any_parallel_operand"
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[(clobber (match_operand:P 1 "register_operand" "=l"))
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(use (match_operand:P 2 "symbol_ref_operand" "s"))
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- (use (match_operand:P 3 "gpc_reg_operand" "r"))
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- (set (match_operand:P 4 "gpc_reg_operand" "=r")
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- (match_operand:P 5 "memory_operand" "m"))])]
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+ (use (reg:P 12))
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+ (set (match_operand:P 3 "gpc_reg_operand" "=r")
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+ (match_operand:P 4 "memory_operand" "m"))])]
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""
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"bl %2"
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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-(define_insn "*return_and_restore_gpregs_<mode>"
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+(define_insn "*restore_gpregs_<mode>_r1"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(clobber (match_operand:P 1 "register_operand" "=l"))
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+ (use (match_operand:P 2 "symbol_ref_operand" "s"))
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+ (use (reg:P 1))
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+ (set (match_operand:P 3 "gpc_reg_operand" "=r")
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+ (match_operand:P 4 "memory_operand" "m"))])]
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+ ""
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+ "bl %2"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*return_and_restore_gpregs_<mode>_r11"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(return)
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+ (clobber (match_operand:P 1 "register_operand" "=l"))
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+ (use (match_operand:P 2 "symbol_ref_operand" "s"))
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+ (use (reg:P 11))
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+ (set (match_operand:P 3 "gpc_reg_operand" "=r")
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+ (match_operand:P 4 "memory_operand" "m"))])]
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+ ""
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+ "b %2"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*return_and_restore_gpregs_<mode>_r12"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(return)
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+ (clobber (match_operand:P 1 "register_operand" "=l"))
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+ (use (match_operand:P 2 "symbol_ref_operand" "s"))
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+ (use (reg:P 12))
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+ (set (match_operand:P 3 "gpc_reg_operand" "=r")
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+ (match_operand:P 4 "memory_operand" "m"))])]
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+ ""
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+ "b %2"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*return_and_restore_gpregs_<mode>_r1"
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[(match_parallel 0 "any_parallel_operand"
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[(return)
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(clobber (match_operand:P 1 "register_operand" "=l"))
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(use (match_operand:P 2 "symbol_ref_operand" "s"))
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- (use (match_operand:P 3 "gpc_reg_operand" "r"))
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- (set (match_operand:P 4 "gpc_reg_operand" "=r")
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- (match_operand:P 5 "memory_operand" "m"))])]
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+ (use (reg:P 1))
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+ (set (match_operand:P 3 "gpc_reg_operand" "=r")
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+ (match_operand:P 4 "memory_operand" "m"))])]
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""
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"b %2"
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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-(define_insn "*return_and_restore_fpregs_<mode>"
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+(define_insn "*return_and_restore_fpregs_<mode>_r11"
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[(match_parallel 0 "any_parallel_operand"
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[(return)
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(clobber (match_operand:P 1 "register_operand" "=l"))
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(use (match_operand:P 2 "symbol_ref_operand" "s"))
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- (use (match_operand:P 3 "gpc_reg_operand" "r"))
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- (set (match_operand:DF 4 "gpc_reg_operand" "=d")
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- (match_operand:DF 5 "memory_operand" "m"))])]
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+ (use (reg:P 11))
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+ (set (match_operand:DF 3 "gpc_reg_operand" "=d")
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+ (match_operand:DF 4 "memory_operand" "m"))])]
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+ ""
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+ "b %2"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*return_and_restore_fpregs_<mode>_r12"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(return)
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+ (clobber (match_operand:P 1 "register_operand" "=l"))
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+ (use (match_operand:P 2 "symbol_ref_operand" "s"))
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+ (use (reg:P 12))
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+ (set (match_operand:DF 3 "gpc_reg_operand" "=d")
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+ (match_operand:DF 4 "memory_operand" "m"))])]
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+ ""
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+ "b %2"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*return_and_restore_fpregs_<mode>_r1"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(return)
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+ (clobber (match_operand:P 1 "register_operand" "=l"))
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+ (use (match_operand:P 2 "symbol_ref_operand" "s"))
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+ (use (reg:P 1))
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+ (set (match_operand:DF 3 "gpc_reg_operand" "=d")
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+ (match_operand:DF 4 "memory_operand" "m"))])]
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+ ""
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+ "b %2"
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+ [(set_attr "type" "branch")
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+ (set_attr "length" "4")])
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+
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+(define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
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+ [(match_parallel 0 "any_parallel_operand"
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+ [(return)
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+ (use (match_operand:P 1 "register_operand" "l"))
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+ (use (match_operand:P 2 "symbol_ref_operand" "s"))
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+ (use (reg:P 11))
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+ (set (match_operand:DF 3 "gpc_reg_operand" "=d")
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+ (match_operand:DF 4 "memory_operand" "m"))])]
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""
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"b %2"
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[(set_attr "type" "branch")
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(set_attr "length" "4")])
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-(define_insn "*return_and_restore_fpregs_aix_<mode>"
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+(define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
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[(match_parallel 0 "any_parallel_operand"
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[(return)
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(use (match_operand:P 1 "register_operand" "l"))
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(use (match_operand:P 2 "symbol_ref_operand" "s"))
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- (use (match_operand:P 3 "gpc_reg_operand" "r"))
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- (set (match_operand:DF 4 "gpc_reg_operand" "=d")
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- (match_operand:DF 5 "memory_operand" "m"))])]
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+ (use (reg:P 1))
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+ (set (match_operand:DF 3 "gpc_reg_operand" "=d")
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+ (match_operand:DF 4 "memory_operand" "m"))])]
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""
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"b %2"
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[(set_attr "type" "branch")
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Index: gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/outofline_rnreg.c
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===================================================================
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--- /dev/null
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+++ gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/outofline_rnreg.c
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@@ -0,0 +1,15 @@
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+/* Test that registers used by out of line restore functions does not get renamed.
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+ AIX, and 64 bit targets uses r1, which rnreg stays away from.
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+ Linux 32 bits targets uses r11, which is susceptible to be renamed */
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+/* { dg-do compile } */
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+/* { dg-require-effective-target ilp32 } */
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+/* { dg-options "-Os -frename-registers -fdump-rtl-rnreg" } */
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+/* "* renamed" or "* no available better choice" results are not acceptable */
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+/* { dg-final { scan-rtl-dump-not "Register 11 in insn *" "rnreg" { target powerpc*-*-linux* } } } */
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+/* { dg-final { cleanup-rtl-dump "rnreg" } } */
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+int
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+calc (int j)
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+{
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+ if (j<=1) return 1;
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+ return calc(j-1)*(j+1);
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+}
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