231 lines
6.0 KiB
C
231 lines
6.0 KiB
C
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MSM8X10_WCD_H
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#define MSM8X10_WCD_H
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#include <sound/soc.h>
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#include <sound/jack.h>
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#include "wcd9xxx-mbhc.h"
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#include "wcd9xxx-resmgr.h"
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#define MSM8X10_WCD_NUM_REGISTERS 0x600
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#define MSM8X10_WCD_MAX_REGISTER (MSM8X10_WCD_NUM_REGISTERS-1)
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#define MSM8X10_WCD_CACHE_SIZE MSM8X10_WCD_NUM_REGISTERS
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#define MSM8X10_WCD_NUM_IRQ_REGS 3
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#define MAX_REGULATOR 7
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#define MSM8X10_WCD_REG_VAL(reg, val) {reg, 0, val}
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#define MSM8X10_WCD_IS_DINO_REG(reg) \
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(((reg >= 0x400) && (reg <= 0x5FF)) ? 1 : 0)
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#define MSM8X10_WCD_IS_HELICON_REG(reg) \
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(((reg >= 0x000) && (reg <= 0x1FF)) ? 1 : 0)
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extern const u8 msm8x10_wcd_reg_readable[MSM8X10_WCD_CACHE_SIZE];
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extern const u8 msm8x10_wcd_reset_reg_defaults[MSM8X10_WCD_CACHE_SIZE];
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struct msm8x10_wcd_codec_dai_data {
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u32 rate;
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u32 *ch_num;
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u32 ch_act;
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u32 ch_tot;
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};
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enum msm8x10_wcd_pid_current {
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MSM8X10_WCD_PID_MIC_2P5_UA,
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MSM8X10_WCD_PID_MIC_5_UA,
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MSM8X10_WCD_PID_MIC_10_UA,
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MSM8X10_WCD_PID_MIC_20_UA,
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};
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struct msm8x10_wcd_reg_mask_val {
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u16 reg;
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u8 mask;
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u8 val;
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};
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enum msm8x10_wcd_mbhc_analog_pwr_cfg {
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MSM8X10_WCD_ANALOG_PWR_COLLAPSED = 0,
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MSM8X10_WCD_ANALOG_PWR_ON,
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MSM8X10_WCD_NUM_ANALOG_PWR_CONFIGS,
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};
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/* Number of input and output Slimbus port */
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enum {
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MSM8X10_WCD_RX1 = 0,
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MSM8X10_WCD_RX2,
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MSM8X10_WCD_RX3,
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MSM8X10_WCD_RX_MAX,
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};
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enum {
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MSM8X10_WCD_TX1 = 0,
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MSM8X10_WCD_TX2,
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MSM8X10_WCD_TX3,
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MSM8X10_WCD_TX4,
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MSM8X10_WCD_TX_MAX,
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};
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enum {
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/* INTR_REG 0 */
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MSM8X10_WCD_IRQ_RESERVED_0 = 0,
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MSM8X10_WCD_IRQ_MBHC_REMOVAL,
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MSM8X10_WCD_IRQ_MBHC_SHORT_TERM,
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MSM8X10_WCD_IRQ_MBHC_PRESS,
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MSM8X10_WCD_IRQ_MBHC_RELEASE,
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MSM8X10_WCD_IRQ_MBHC_POTENTIAL,
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MSM8X10_WCD_IRQ_MBHC_INSERTION,
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MSM8X10_WCD_IRQ_MBHC_HS_DET,
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/* INTR_REG 1 */
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MSM8X10_WCD_IRQ_PA_STARTUP,
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MSM8X10_WCD_IRQ_BG_PRECHARGE,
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MSM8X10_WCD_IRQ_RESERVED_1,
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MSM8X10_WCD_IRQ_EAR_PA_OCPL_FAULT,
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MSM8X10_WCD_IRQ_EAR_PA_STARTUP,
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MSM8X10_WCD_IRQ_SPKR_PA_OCPL_FAULT,
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MSM8X10_WCD_IRQ_SPKR_CLIP_FAULT,
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MSM8X10_WCD_IRQ_RESERVED_2,
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/* INTR_REG 2 */
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MSM8X10_WCD_IRQ_HPH_L_PA_STARTUP,
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MSM8X10_WCD_IRQ_HPH_R_PA_STARTUP,
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MSM8X10_WCD_IRQ_HPH_PA_OCPL_FAULT,
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MSM8X10_WCD_IRQ_HPH_PA_OCPR_FAULT,
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MSM8X10_WCD_IRQ_RESERVED_3,
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MSM8X10_WCD_IRQ_RESERVED_4,
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MSM8X10_WCD_IRQ_RESERVED_5,
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MSM8X10_WCD_IRQ_RESERVED_6,
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MSM8X10_WCD_NUM_IRQS,
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};
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/*
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* Each micbias can be assigned to one of three cfilters
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* Vbatt_min >= .15V + ldoh_v
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* ldoh_v >= .15v + cfiltx_mv
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* If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
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* If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
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* If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
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* If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
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*/
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struct msm8x10_wcd_micbias_setting {
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u8 ldoh_v;
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u32 cfilt1_mv; /* in mv */
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/*
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* Different WCD9xxx series codecs may not
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* have 4 mic biases. If a codec has fewer
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* mic biases, some of these properties will
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* not be used.
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*/
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u8 bias1_cfilt_sel;
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u8 bias1_cap_mode;
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};
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struct msm8x10_wcd_ocp_setting {
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unsigned int use_pdata:1; /* 0 - use sys default as recommended */
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unsigned int num_attempts:4; /* up to 15 attempts */
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unsigned int run_time:4; /* in duty cycle */
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unsigned int wait_time:4; /* in duty cycle */
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unsigned int hph_ocp_limit:3; /* Headphone OCP current limit */
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};
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struct msm8x10_wcd_regulator {
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const char *name;
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int min_uV;
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int max_uV;
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int optimum_uA;
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struct regulator *regulator;
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};
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struct msm8x10_wcd_pdata {
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int irq;
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int irq_base;
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int num_irqs;
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int reset_gpio;
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void *msm8x10_wcd_ahb_base_vaddr;
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struct msm8x10_wcd_micbias_setting micbias;
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struct msm8x10_wcd_ocp_setting ocp;
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struct msm8x10_wcd_regulator regulator[MAX_REGULATOR];
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u32 mclk_rate;
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};
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enum msm8x10_wcd_micbias_num {
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MSM8X10_WCD_MICBIAS1 = 0,
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};
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struct msm8x10_wcd_mbhc_config {
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struct snd_soc_jack *headset_jack;
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struct snd_soc_jack *button_jack;
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bool read_fw_bin;
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/*
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* void* calibration contains:
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* struct msm8x10_wcd_mbhc_general_cfg generic;
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* struct msm8x10_wcd_mbhc_plug_detect_cfg plug_det;
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* struct msm8x10_wcd_mbhc_plug_type_cfg plug_type;
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* struct msm8x10_wcd_mbhc_btn_detect_cfg btn_det;
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* struct msm8x10_wcd_mbhc_imped_detect_cfg imped_det;
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* Note: various size depends on btn_det->num_btn
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*/
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void *calibration;
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enum msm8x10_wcd_micbias_num micbias;
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int (*mclk_cb_fn) (struct snd_soc_codec*, int, bool);
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unsigned int mclk_rate;
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unsigned int gpio;
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unsigned int gpio_irq;
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int gpio_level_insert;
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bool detect_extn_cable;
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/* swap_gnd_mic returns true if extern GND/MIC swap switch toggled */
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bool (*swap_gnd_mic) (struct snd_soc_codec *);
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};
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enum msm8x10_wcd_pm_state {
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MSM8X10_WCD_PM_SLEEPABLE,
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MSM8X10_WCD_PM_AWAKE,
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MSM8X10_WCD_PM_ASLEEP,
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};
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struct msm8x10_wcd {
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struct device *dev;
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struct mutex io_lock;
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struct mutex xfer_lock;
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struct mutex irq_lock;
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u8 version;
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int reset_gpio;
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int (*read_dev)(struct msm8x10_wcd *msm8x10,
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unsigned short reg, unsigned int *val);
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int (*write_dev)(struct msm8x10_wcd *msm8x10,
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unsigned short reg, u8 val);
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u32 num_of_supplies;
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struct regulator_bulk_data *supplies;
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enum msm8x10_wcd_pm_state pm_state;
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struct mutex pm_lock;
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/* pm_wq notifies change of pm_state */
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wait_queue_head_t pm_wq;
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struct pm_qos_request pm_qos_req;
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int wlock_holders;
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u8 idbyte[4];
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unsigned int irq_base;
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unsigned int irq;
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u8 irq_masks_cur[MSM8X10_WCD_NUM_IRQ_REGS];
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u8 irq_masks_cache[MSM8X10_WCD_NUM_IRQ_REGS];
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bool irq_level_high[MSM8X10_WCD_NUM_IRQS];
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int num_irqs;
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u32 mclk_rate;
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};
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extern int msm8x10_wcd_mclk_enable(struct snd_soc_codec *codec, int mclk_enable,
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bool dapm);
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extern int msm8x10_wcd_hs_detect(struct snd_soc_codec *codec,
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struct msm8x10_wcd_mbhc_config *mbhc_cfg);
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#endif
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