169 lines
4.3 KiB
C
169 lines
4.3 KiB
C
/*******************************************************************************
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Header File to describe the DMA descriptors.
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Enhanced descriptors have been in case of DWMAC1000 Cores.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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struct dma_desc {
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/* Receive descriptor */
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union {
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struct {
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/* RDES0 */
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u32 payload_csum_error:1;
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u32 crc_error:1;
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u32 dribbling:1;
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u32 mii_error:1;
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u32 receive_watchdog:1;
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u32 frame_type:1;
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u32 collision:1;
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u32 ipc_csum_error:1;
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u32 last_descriptor:1;
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u32 first_descriptor:1;
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u32 vlan_tag:1;
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u32 overflow_error:1;
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u32 length_error:1;
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u32 sa_filter_fail:1;
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u32 descriptor_error:1;
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u32 error_summary:1;
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u32 frame_length:14;
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u32 da_filter_fail:1;
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u32 own:1;
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/* RDES1 */
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u32 buffer1_size:11;
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u32 buffer2_size:11;
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u32 reserved1:2;
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u32 second_address_chained:1;
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u32 end_ring:1;
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u32 reserved2:5;
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u32 disable_ic:1;
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} rx;
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struct {
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/* RDES0 */
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u32 payload_csum_error:1;
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u32 crc_error:1;
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u32 dribbling:1;
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u32 error_gmii:1;
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u32 receive_watchdog:1;
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u32 frame_type:1;
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u32 late_collision:1;
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u32 ipc_csum_error:1;
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u32 last_descriptor:1;
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u32 first_descriptor:1;
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u32 vlan_tag:1;
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u32 overflow_error:1;
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u32 length_error:1;
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u32 sa_filter_fail:1;
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u32 descriptor_error:1;
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u32 error_summary:1;
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u32 frame_length:14;
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u32 da_filter_fail:1;
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u32 own:1;
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/* RDES1 */
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u32 buffer1_size:13;
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u32 reserved1:1;
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u32 second_address_chained:1;
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u32 end_ring:1;
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u32 buffer2_size:13;
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u32 reserved2:2;
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u32 disable_ic:1;
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} erx; /* -- enhanced -- */
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/* Transmit descriptor */
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struct {
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/* TDES0 */
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u32 deferred:1;
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u32 underflow_error:1;
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u32 excessive_deferral:1;
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u32 collision_count:4;
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u32 vlan_frame:1;
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u32 excessive_collisions:1;
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u32 late_collision:1;
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u32 no_carrier:1;
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u32 loss_carrier:1;
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u32 payload_error:1;
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u32 frame_flushed:1;
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u32 jabber_timeout:1;
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u32 error_summary:1;
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u32 ip_header_error:1;
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u32 time_stamp_status:1;
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u32 reserved1:13;
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u32 own:1;
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/* TDES1 */
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u32 buffer1_size:11;
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u32 buffer2_size:11;
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u32 time_stamp_enable:1;
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u32 disable_padding:1;
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u32 second_address_chained:1;
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u32 end_ring:1;
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u32 crc_disable:1;
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u32 checksum_insertion:2;
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u32 first_segment:1;
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u32 last_segment:1;
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u32 interrupt:1;
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} tx;
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struct {
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/* TDES0 */
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u32 deferred:1;
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u32 underflow_error:1;
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u32 excessive_deferral:1;
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u32 collision_count:4;
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u32 vlan_frame:1;
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u32 excessive_collisions:1;
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u32 late_collision:1;
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u32 no_carrier:1;
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u32 loss_carrier:1;
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u32 payload_error:1;
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u32 frame_flushed:1;
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u32 jabber_timeout:1;
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u32 error_summary:1;
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u32 ip_header_error:1;
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u32 time_stamp_status:1;
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u32 reserved1:2;
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u32 second_address_chained:1;
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u32 end_ring:1;
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u32 checksum_insertion:2;
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u32 reserved2:1;
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u32 time_stamp_enable:1;
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u32 disable_padding:1;
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u32 crc_disable:1;
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u32 first_segment:1;
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u32 last_segment:1;
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u32 interrupt:1;
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u32 own:1;
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/* TDES1 */
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u32 buffer1_size:13;
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u32 reserved3:3;
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u32 buffer2_size:13;
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u32 reserved4:3;
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} etx; /* -- enhanced -- */
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} des01;
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unsigned int des2;
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unsigned int des3;
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};
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/* Transmit checksum insertion control */
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enum tdes_csum_insertion {
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cic_disabled = 0, /* Checksum Insertion Control */
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cic_only_ip = 1, /* Only IP header */
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cic_no_pseudoheader = 2, /* IP header but pseudoheader
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* is not calculated */
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cic_full = 3, /* IP header and pseudoheader */
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};
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