344 lines
9.3 KiB
C
344 lines
9.3 KiB
C
/*
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* linux/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/firmware.h>
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#include <linux/jiffies.h>
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#include <linux/sched.h>
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#include "regs-mfc.h"
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#include "s5p_mfc_cmd.h"
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#include "s5p_mfc_common.h"
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#include "s5p_mfc_debug.h"
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#include "s5p_mfc_intr.h"
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#include "s5p_mfc_pm.h"
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static void *s5p_mfc_bitproc_buf;
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static size_t s5p_mfc_bitproc_phys;
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static unsigned char *s5p_mfc_bitproc_virt;
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/* Allocate and load firmware */
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int s5p_mfc_alloc_and_load_firmware(struct s5p_mfc_dev *dev)
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{
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struct firmware *fw_blob;
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size_t bank2_base_phys;
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void *b_base;
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int err;
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/* Firmare has to be present as a separate file or compiled
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* into kernel. */
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mfc_debug_enter();
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err = request_firmware((const struct firmware **)&fw_blob,
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"s5p-mfc.fw", dev->v4l2_dev.dev);
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if (err != 0) {
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mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
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return -EINVAL;
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}
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dev->fw_size = ALIGN(fw_blob->size, FIRMWARE_ALIGN);
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if (s5p_mfc_bitproc_buf) {
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mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
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release_firmware(fw_blob);
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return -ENOMEM;
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}
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s5p_mfc_bitproc_buf = vb2_dma_contig_memops.alloc(
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dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], dev->fw_size);
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if (IS_ERR(s5p_mfc_bitproc_buf)) {
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s5p_mfc_bitproc_buf = 0;
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mfc_err("Allocating bitprocessor buffer failed\n");
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release_firmware(fw_blob);
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return -ENOMEM;
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}
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s5p_mfc_bitproc_phys = s5p_mfc_mem_cookie(
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dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], s5p_mfc_bitproc_buf);
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if (s5p_mfc_bitproc_phys & ((1 << MFC_BASE_ALIGN_ORDER) - 1)) {
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mfc_err("The base memory for bank 1 is not aligned to 128KB\n");
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vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
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s5p_mfc_bitproc_phys = 0;
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s5p_mfc_bitproc_buf = 0;
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release_firmware(fw_blob);
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return -EIO;
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}
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s5p_mfc_bitproc_virt = vb2_dma_contig_memops.vaddr(s5p_mfc_bitproc_buf);
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if (!s5p_mfc_bitproc_virt) {
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mfc_err("Bitprocessor memory remap failed\n");
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vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
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s5p_mfc_bitproc_phys = 0;
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s5p_mfc_bitproc_buf = 0;
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release_firmware(fw_blob);
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return -EIO;
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}
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dev->bank1 = s5p_mfc_bitproc_phys;
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b_base = vb2_dma_contig_memops.alloc(
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dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], 1 << MFC_BANK2_ALIGN_ORDER);
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if (IS_ERR(b_base)) {
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vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
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s5p_mfc_bitproc_phys = 0;
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s5p_mfc_bitproc_buf = 0;
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mfc_err("Allocating bank2 base failed\n");
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release_firmware(fw_blob);
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return -ENOMEM;
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}
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bank2_base_phys = s5p_mfc_mem_cookie(
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dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], b_base);
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vb2_dma_contig_memops.put(b_base);
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if (bank2_base_phys & ((1 << MFC_BASE_ALIGN_ORDER) - 1)) {
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mfc_err("The base memory for bank 2 is not aligned to 128KB\n");
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vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
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s5p_mfc_bitproc_phys = 0;
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s5p_mfc_bitproc_buf = 0;
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release_firmware(fw_blob);
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return -EIO;
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}
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dev->bank2 = bank2_base_phys;
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memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
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wmb();
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release_firmware(fw_blob);
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mfc_debug_leave();
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return 0;
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}
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/* Reload firmware to MFC */
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int s5p_mfc_reload_firmware(struct s5p_mfc_dev *dev)
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{
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struct firmware *fw_blob;
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int err;
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/* Firmare has to be present as a separate file or compiled
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* into kernel. */
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mfc_debug_enter();
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err = request_firmware((const struct firmware **)&fw_blob,
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"s5p-mfc.fw", dev->v4l2_dev.dev);
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if (err != 0) {
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mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
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return -EINVAL;
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}
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if (fw_blob->size > dev->fw_size) {
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mfc_err("MFC firmware is too big to be loaded\n");
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release_firmware(fw_blob);
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return -ENOMEM;
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}
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if (s5p_mfc_bitproc_buf == 0 || s5p_mfc_bitproc_phys == 0) {
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mfc_err("MFC firmware is not allocated or was not mapped correctly\n");
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release_firmware(fw_blob);
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return -EINVAL;
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}
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memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
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wmb();
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release_firmware(fw_blob);
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mfc_debug_leave();
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return 0;
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}
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/* Release firmware memory */
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int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
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{
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/* Before calling this function one has to make sure
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* that MFC is no longer processing */
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if (!s5p_mfc_bitproc_buf)
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return -EINVAL;
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vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
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s5p_mfc_bitproc_virt = 0;
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s5p_mfc_bitproc_phys = 0;
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s5p_mfc_bitproc_buf = 0;
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return 0;
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}
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/* Reset the device */
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int s5p_mfc_reset(struct s5p_mfc_dev *dev)
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{
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unsigned int mc_status;
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unsigned long timeout;
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mfc_debug_enter();
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/* Stop procedure */
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/* reset RISC */
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mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
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/* All reset except for MC */
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mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
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mdelay(10);
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timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
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/* Check MC status */
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do {
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if (time_after(jiffies, timeout)) {
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mfc_err("Timeout while resetting MFC\n");
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return -EIO;
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}
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mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
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} while (mc_status & 0x3);
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mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
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mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
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mfc_debug_leave();
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return 0;
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}
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static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
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{
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mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A);
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mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B);
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mfc_debug(2, "Bank1: %08x, Bank2: %08x\n", dev->bank1, dev->bank2);
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}
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static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
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{
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mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
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mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
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mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
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mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
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}
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/* Initialize hardware */
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int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
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{
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unsigned int ver;
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int ret;
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mfc_debug_enter();
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if (!s5p_mfc_bitproc_buf)
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return -EINVAL;
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/* 0. MFC reset */
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mfc_debug(2, "MFC reset..\n");
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s5p_mfc_clock_on();
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ret = s5p_mfc_reset(dev);
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if (ret) {
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mfc_err("Failed to reset MFC - timeout\n");
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return ret;
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}
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mfc_debug(2, "Done MFC reset..\n");
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/* 1. Set DRAM base Addr */
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s5p_mfc_init_memctrl(dev);
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/* 2. Initialize registers of channel I/F */
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s5p_mfc_clear_cmds(dev);
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/* 3. Release reset signal to the RISC */
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s5p_mfc_clean_dev_int_flags(dev);
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mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
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mfc_debug(2, "Will now wait for completion of firmware transfer\n");
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if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_FW_STATUS_RET)) {
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mfc_err("Failed to load firmware\n");
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s5p_mfc_reset(dev);
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s5p_mfc_clock_off();
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return -EIO;
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}
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s5p_mfc_clean_dev_int_flags(dev);
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/* 4. Initialize firmware */
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ret = s5p_mfc_sys_init_cmd(dev);
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if (ret) {
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mfc_err("Failed to send command to MFC - timeout\n");
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s5p_mfc_reset(dev);
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s5p_mfc_clock_off();
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return ret;
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}
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mfc_debug(2, "Ok, now will write a command to init the system\n");
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if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SYS_INIT_RET)) {
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mfc_err("Failed to load firmware\n");
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s5p_mfc_reset(dev);
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s5p_mfc_clock_off();
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return -EIO;
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}
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dev->int_cond = 0;
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if (dev->int_err != 0 || dev->int_type !=
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S5P_FIMV_R2H_CMD_SYS_INIT_RET) {
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/* Failure. */
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mfc_err("Failed to init firmware - error: %d int: %d\n",
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dev->int_err, dev->int_type);
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s5p_mfc_reset(dev);
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s5p_mfc_clock_off();
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return -EIO;
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}
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ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
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mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
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(ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
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s5p_mfc_clock_off();
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mfc_debug_leave();
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return 0;
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}
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int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
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{
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int ret;
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mfc_debug_enter();
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s5p_mfc_clock_on();
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s5p_mfc_clean_dev_int_flags(dev);
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ret = s5p_mfc_sleep_cmd(dev);
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if (ret) {
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mfc_err("Failed to send command to MFC - timeout\n");
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return ret;
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}
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if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SLEEP_RET)) {
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mfc_err("Failed to sleep\n");
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return -EIO;
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}
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s5p_mfc_clock_off();
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dev->int_cond = 0;
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if (dev->int_err != 0 || dev->int_type !=
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S5P_FIMV_R2H_CMD_SLEEP_RET) {
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/* Failure. */
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mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
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dev->int_type);
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return -EIO;
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}
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mfc_debug_leave();
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return ret;
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}
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int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
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{
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int ret;
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mfc_debug_enter();
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/* 0. MFC reset */
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mfc_debug(2, "MFC reset..\n");
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s5p_mfc_clock_on();
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ret = s5p_mfc_reset(dev);
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if (ret) {
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mfc_err("Failed to reset MFC - timeout\n");
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return ret;
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}
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mfc_debug(2, "Done MFC reset..\n");
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/* 1. Set DRAM base Addr */
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s5p_mfc_init_memctrl(dev);
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/* 2. Initialize registers of channel I/F */
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s5p_mfc_clear_cmds(dev);
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s5p_mfc_clean_dev_int_flags(dev);
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/* 3. Initialize firmware */
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ret = s5p_mfc_wakeup_cmd(dev);
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if (ret) {
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mfc_err("Failed to send command to MFC - timeout\n");
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return ret;
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}
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/* 4. Release reset signal to the RISC */
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mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
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mfc_debug(2, "Ok, now will write a command to wakeup the system\n");
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if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_WAKEUP_RET)) {
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mfc_err("Failed to load firmware\n");
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return -EIO;
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}
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s5p_mfc_clock_off();
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dev->int_cond = 0;
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if (dev->int_err != 0 || dev->int_type !=
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S5P_FIMV_R2H_CMD_WAKEUP_RET) {
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/* Failure. */
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mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
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dev->int_type);
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return -EIO;
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}
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mfc_debug_leave();
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return 0;
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}
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