603 lines
18 KiB
C
603 lines
18 KiB
C
/* Copyright (c) 2008-2013, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ADRENO_H
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#define __ADRENO_H
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#include "kgsl_device.h"
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#include "adreno_drawctxt.h"
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#include "adreno_ringbuffer.h"
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#include "kgsl_iommu.h"
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#include <mach/ocmem.h>
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#include "a3xx_reg.h"
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#define DEVICE_3D_NAME "kgsl-3d"
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#define DEVICE_3D0_NAME "kgsl-3d0"
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#define ADRENO_DEVICE(device) \
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KGSL_CONTAINER_OF(device, struct adreno_device, dev)
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#define ADRENO_CHIPID_CORE(_id) (((_id) >> 24) & 0xFF)
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#define ADRENO_CHIPID_MAJOR(_id) (((_id) >> 16) & 0xFF)
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#define ADRENO_CHIPID_MINOR(_id) (((_id) >> 8) & 0xFF)
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#define ADRENO_CHIPID_PATCH(_id) ((_id) & 0xFF)
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/* Flags to control command packet settings */
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#define KGSL_CMD_FLAGS_NONE 0x00000000
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#define KGSL_CMD_FLAGS_PMODE 0x00000001
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#define KGSL_CMD_FLAGS_INTERNAL_ISSUE 0x00000002
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#define KGSL_CMD_FLAGS_GET_INT 0x00000004
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#define KGSL_CMD_FLAGS_EOF 0x00000100
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/* Command identifiers */
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#define KGSL_CONTEXT_TO_MEM_IDENTIFIER 0x2EADBEEF
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#define KGSL_CMD_IDENTIFIER 0x2EEDFACE
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#define KGSL_CMD_INTERNAL_IDENTIFIER 0x2EEDD00D
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#define KGSL_START_OF_IB_IDENTIFIER 0x2EADEABE
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#define KGSL_END_OF_IB_IDENTIFIER 0x2ABEDEAD
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#define KGSL_END_OF_FRAME_IDENTIFIER 0x2E0F2E0F
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#define KGSL_NOP_IB_IDENTIFIER 0x20F20F20
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#ifdef CONFIG_MSM_SCM
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#define ADRENO_DEFAULT_PWRSCALE_POLICY (&kgsl_pwrscale_policy_tz)
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#elif defined CONFIG_MSM_SLEEP_STATS_DEVICE
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#define ADRENO_DEFAULT_PWRSCALE_POLICY (&kgsl_pwrscale_policy_idlestats)
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#else
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#define ADRENO_DEFAULT_PWRSCALE_POLICY NULL
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#endif
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void adreno_debugfs_init(struct kgsl_device *device);
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#define ADRENO_ISTORE_START 0x5000 /* Istore offset */
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#define ADRENO_NUM_CTX_SWITCH_ALLOWED_BEFORE_DRAW 50
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/* One cannot wait forever for the core to idle, so set an upper limit to the
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* amount of time to wait for the core to go idle
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*/
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#define ADRENO_IDLE_TIMEOUT (20 * 1000)
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enum adreno_gpurev {
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ADRENO_REV_UNKNOWN = 0,
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ADRENO_REV_A200 = 200,
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ADRENO_REV_A203 = 203,
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ADRENO_REV_A205 = 205,
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ADRENO_REV_A220 = 220,
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ADRENO_REV_A225 = 225,
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ADRENO_REV_A305 = 305,
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ADRENO_REV_A305C = 306,
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ADRENO_REV_A320 = 320,
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ADRENO_REV_A330 = 330,
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ADRENO_REV_A305B = 335,
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};
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enum coresight_debug_reg {
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DEBUG_BUS_CTL,
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TRACE_STOP_CNT,
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TRACE_START_CNT,
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TRACE_PERIOD_CNT,
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TRACE_CMD,
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TRACE_BUS_CTL,
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};
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struct adreno_gpudev;
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struct adreno_device {
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struct kgsl_device dev; /* Must be first field in this struct */
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unsigned int chip_id;
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enum adreno_gpurev gpurev;
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unsigned long gmem_base;
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unsigned int gmem_size;
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struct adreno_context *drawctxt_active;
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const char *pfp_fwfile;
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unsigned int *pfp_fw;
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size_t pfp_fw_size;
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unsigned int pfp_fw_version;
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const char *pm4_fwfile;
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unsigned int *pm4_fw;
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size_t pm4_fw_size;
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unsigned int pm4_fw_version;
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struct adreno_ringbuffer ringbuffer;
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unsigned int mharb;
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struct adreno_gpudev *gpudev;
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unsigned int wait_timeout;
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unsigned int pm4_jt_idx;
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unsigned int pm4_jt_addr;
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unsigned int pfp_jt_idx;
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unsigned int pfp_jt_addr;
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unsigned int istore_size;
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unsigned int pix_shader_start;
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unsigned int instruction_size;
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unsigned int ib_check_level;
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unsigned int fast_hang_detect;
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unsigned int ft_policy;
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unsigned int long_ib_detect;
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unsigned int long_ib;
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unsigned int long_ib_ts;
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unsigned int ft_pf_policy;
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unsigned int gpulist_index;
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struct ocmem_buf *ocmem_hdl;
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unsigned int ocmem_base;
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unsigned int gpu_cycles;
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};
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#define PERFCOUNTER_FLAG_NONE 0x0
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#define PERFCOUNTER_FLAG_KERNEL 0x1
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/* Structs to maintain the list of active performance counters */
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/**
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* struct adreno_perfcount_register: register state
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* @countable: countable the register holds
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* @refcount: number of users of the register
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* @offset: register hardware offset
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*/
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struct adreno_perfcount_register {
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unsigned int countable;
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unsigned int refcount;
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unsigned int offset;
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unsigned int flags;
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};
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/**
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* struct adreno_perfcount_group: registers for a hardware group
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* @regs: available registers for this group
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* @reg_count: total registers for this group
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*/
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struct adreno_perfcount_group {
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struct adreno_perfcount_register *regs;
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unsigned int reg_count;
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};
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/**
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* adreno_perfcounts: all available perfcounter groups
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* @groups: available groups for this device
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* @group_count: total groups for this device
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*/
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struct adreno_perfcounters {
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struct adreno_perfcount_group *groups;
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unsigned int group_count;
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};
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struct adreno_gpudev {
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/*
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* These registers are in a different location on A3XX, so define
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* them in the structure and use them as variables.
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*/
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unsigned int reg_rbbm_status;
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unsigned int reg_cp_pfp_ucode_data;
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unsigned int reg_cp_pfp_ucode_addr;
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/* keeps track of when we need to execute the draw workaround code */
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int ctx_switches_since_last_draw;
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struct adreno_perfcounters *perfcounters;
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/* GPU specific function hooks */
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int (*ctxt_create)(struct adreno_device *, struct adreno_context *);
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void (*ctxt_save)(struct adreno_device *, struct adreno_context *);
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void (*ctxt_restore)(struct adreno_device *, struct adreno_context *);
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void (*ctxt_draw_workaround)(struct adreno_device *,
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struct adreno_context *);
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irqreturn_t (*irq_handler)(struct adreno_device *);
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void (*irq_control)(struct adreno_device *, int);
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unsigned int (*irq_pending)(struct adreno_device *);
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void * (*snapshot)(struct adreno_device *, void *, int *, int);
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int (*rb_init)(struct adreno_device *, struct adreno_ringbuffer *);
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void (*perfcounter_init)(struct adreno_device *);
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void (*start)(struct adreno_device *);
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unsigned int (*busy_cycles)(struct adreno_device *);
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void (*perfcounter_enable)(struct adreno_device *, unsigned int group,
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unsigned int counter, unsigned int countable);
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uint64_t (*perfcounter_read)(struct adreno_device *adreno_dev,
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unsigned int group, unsigned int counter,
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unsigned int offset);
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int (*coresight_enable) (struct kgsl_device *device);
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void (*coresight_disable) (struct kgsl_device *device);
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void (*coresight_config_debug_reg) (struct kgsl_device *device,
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int debug_reg, unsigned int val);
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void (*soft_reset)(struct adreno_device *device);
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};
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/*
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* struct adreno_ft_data - Structure that contains all information to
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* perform gpu fault tolerance
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* @ib1 - IB1 that the GPU was executing when hang happened
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* @context_id - Context which caused the hang
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* @global_eop - eoptimestamp at time of hang
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* @rb_buffer - Buffer that holds the commands from good contexts
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* @rb_size - Number of valid dwords in rb_buffer
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* @bad_rb_buffer - Buffer that holds commands from the hanging context
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* bad_rb_size - Number of valid dwords in bad_rb_buffer
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* @good_rb_buffer - Buffer that holds commands from good contexts
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* good_rb_size - Number of valid dwords in good_rb_buffer
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* @last_valid_ctx_id - The last context from which commands were placed in
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* ringbuffer before the GPU hung
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* @step - Current fault tolerance step being executed
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* @err_code - Fault tolerance error code
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* @fault - Indicates whether the hang was caused due to a pagefault
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* @start_of_replay_cmds - Offset in ringbuffer from where commands can be
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* replayed during fault tolerance
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* @replay_for_snapshot - Offset in ringbuffer where IB's can be saved for
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* replaying with snapshot
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*/
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struct adreno_ft_data {
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unsigned int ib1;
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unsigned int context_id;
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unsigned int global_eop;
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unsigned int *rb_buffer;
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unsigned int rb_size;
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unsigned int *bad_rb_buffer;
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unsigned int bad_rb_size;
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unsigned int *good_rb_buffer;
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unsigned int good_rb_size;
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unsigned int last_valid_ctx_id;
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unsigned int status;
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unsigned int ft_policy;
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unsigned int err_code;
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unsigned int start_of_replay_cmds;
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unsigned int replay_for_snapshot;
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};
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#define FT_DETECT_REGS_COUNT 12
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/* Fault Tolerance policy flags */
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#define KGSL_FT_DISABLE BIT(0)
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#define KGSL_FT_REPLAY BIT(1)
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#define KGSL_FT_SKIPIB BIT(2)
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#define KGSL_FT_SKIPFRAME BIT(3)
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#define KGSL_FT_TEMP_DISABLE BIT(4)
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#define KGSL_FT_DEFAULT_POLICY (KGSL_FT_REPLAY + KGSL_FT_SKIPIB)
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/* Pagefault policy flags */
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#define KGSL_FT_PAGEFAULT_INT_ENABLE 0x00000001
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#define KGSL_FT_PAGEFAULT_GPUHALT_ENABLE 0x00000002
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#define KGSL_FT_PAGEFAULT_LOG_ONE_PER_PAGE 0x00000004
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#define KGSL_FT_PAGEFAULT_LOG_ONE_PER_INT 0x00000008
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#define KGSL_FT_PAGEFAULT_DEFAULT_POLICY (KGSL_FT_PAGEFAULT_INT_ENABLE + \
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KGSL_FT_PAGEFAULT_GPUHALT_ENABLE)
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extern struct adreno_gpudev adreno_a2xx_gpudev;
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extern struct adreno_gpudev adreno_a3xx_gpudev;
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/* A2XX register sets defined in adreno_a2xx.c */
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extern const unsigned int a200_registers[];
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extern const unsigned int a220_registers[];
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extern const unsigned int a225_registers[];
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extern const unsigned int a200_registers_count;
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extern const unsigned int a220_registers_count;
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extern const unsigned int a225_registers_count;
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/* A3XX register set defined in adreno_a3xx.c */
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extern const unsigned int a3xx_registers[];
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extern const unsigned int a3xx_registers_count;
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extern const unsigned int a3xx_hlsq_registers[];
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extern const unsigned int a3xx_hlsq_registers_count;
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extern const unsigned int a330_registers[];
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extern const unsigned int a330_registers_count;
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extern unsigned int ft_detect_regs[];
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int adreno_coresight_enable(struct coresight_device *csdev);
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void adreno_coresight_disable(struct coresight_device *csdev);
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void adreno_coresight_remove(struct platform_device *pdev);
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int adreno_coresight_init(struct platform_device *pdev);
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int adreno_idle(struct kgsl_device *device);
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void adreno_regread(struct kgsl_device *device, unsigned int offsetwords,
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unsigned int *value);
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void adreno_regwrite(struct kgsl_device *device, unsigned int offsetwords,
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unsigned int value);
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void adreno_shadermem_regread(struct kgsl_device *device,
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unsigned int offsetwords,
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unsigned int *value);
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int adreno_dump(struct kgsl_device *device, int manual);
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unsigned int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device
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*adreno_dev);
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struct kgsl_memdesc *adreno_find_region(struct kgsl_device *device,
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phys_addr_t pt_base,
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unsigned int gpuaddr,
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unsigned int size);
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uint8_t *adreno_convertaddr(struct kgsl_device *device,
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phys_addr_t pt_base, unsigned int gpuaddr, unsigned int size);
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struct kgsl_memdesc *adreno_find_ctxtmem(struct kgsl_device *device,
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phys_addr_t pt_base, unsigned int gpuaddr, unsigned int size);
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void *adreno_snapshot(struct kgsl_device *device, void *snapshot, int *remain,
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int hang);
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int adreno_dump_and_exec_ft(struct kgsl_device *device);
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void adreno_dump_rb(struct kgsl_device *device, const void *buf,
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size_t len, int start, int size);
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unsigned int adreno_ft_detect(struct kgsl_device *device,
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unsigned int *prev_reg_val);
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int adreno_perfcounter_get(struct adreno_device *adreno_dev,
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unsigned int groupid, unsigned int countable, unsigned int *offset,
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unsigned int flags);
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int adreno_perfcounter_put(struct adreno_device *adreno_dev,
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unsigned int groupid, unsigned int countable);
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int adreno_soft_reset(struct kgsl_device *device);
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static inline int adreno_is_a200(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A200);
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}
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static inline int adreno_is_a203(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A203);
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}
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static inline int adreno_is_a205(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A205);
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}
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static inline int adreno_is_a20x(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev <= 209);
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}
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static inline int adreno_is_a220(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A220);
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}
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static inline int adreno_is_a225(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A225);
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}
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static inline int adreno_is_a22x(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A220 ||
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adreno_dev->gpurev == ADRENO_REV_A225);
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}
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static inline int adreno_is_a2xx(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev <= 299);
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}
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static inline int adreno_is_a3xx(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev >= 300);
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}
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static inline int adreno_is_a305(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A305);
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}
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static inline int adreno_is_a305b(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A305B);
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}
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static inline int adreno_is_a305c(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A305C);
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}
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static inline int adreno_is_a320(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A320);
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}
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static inline int adreno_is_a330(struct adreno_device *adreno_dev)
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{
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return (adreno_dev->gpurev == ADRENO_REV_A330);
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}
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static inline int adreno_is_a330v2(struct adreno_device *adreno_dev)
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{
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return ((adreno_dev->gpurev == ADRENO_REV_A330) &&
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(ADRENO_CHIPID_PATCH(adreno_dev->chip_id) > 0));
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}
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static inline int adreno_rb_ctxtswitch(unsigned int *cmd)
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{
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return (cmd[0] == cp_nop_packet(1) &&
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cmd[1] == KGSL_CONTEXT_TO_MEM_IDENTIFIER);
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}
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/**
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* adreno_encode_istore_size - encode istore size in CP format
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* @adreno_dev - The 3D device.
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*
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* Encode the istore size into the format expected that the
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* CP_SET_SHADER_BASES and CP_ME_INIT commands:
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* bits 31:29 - istore size as encoded by this function
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* bits 27:16 - vertex shader start offset in instructions
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* bits 11:0 - pixel shader start offset in instructions.
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*/
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static inline int adreno_encode_istore_size(struct adreno_device *adreno_dev)
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{
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unsigned int size;
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/* in a225 the CP microcode multiplies the encoded
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* value by 3 while decoding.
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*/
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if (adreno_is_a225(adreno_dev))
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size = adreno_dev->istore_size/3;
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else
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size = adreno_dev->istore_size;
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return (ilog2(size) - 5) << 29;
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}
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static inline int __adreno_add_idle_indirect_cmds(unsigned int *cmds,
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unsigned int nop_gpuaddr)
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{
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/* Adding an indirect buffer ensures that the prefetch stalls until
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* the commands in indirect buffer have completed. We need to stall
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* prefetch with a nop indirect buffer when updating pagetables
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* because it provides stabler synchronization */
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*cmds++ = CP_HDR_INDIRECT_BUFFER_PFD;
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*cmds++ = nop_gpuaddr;
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*cmds++ = 2;
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*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
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*cmds++ = 0x00000000;
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return 5;
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}
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static inline int adreno_add_change_mh_phys_limit_cmds(unsigned int *cmds,
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unsigned int new_phys_limit,
|
|
unsigned int nop_gpuaddr)
|
|
{
|
|
unsigned int *start = cmds;
|
|
|
|
*cmds++ = cp_type0_packet(MH_MMU_MPU_END, 1);
|
|
*cmds++ = new_phys_limit;
|
|
cmds += __adreno_add_idle_indirect_cmds(cmds, nop_gpuaddr);
|
|
return cmds - start;
|
|
}
|
|
|
|
static inline int adreno_add_bank_change_cmds(unsigned int *cmds,
|
|
int cur_ctx_bank,
|
|
unsigned int nop_gpuaddr)
|
|
{
|
|
unsigned int *start = cmds;
|
|
|
|
*cmds++ = cp_type0_packet(REG_CP_STATE_DEBUG_INDEX, 1);
|
|
*cmds++ = (cur_ctx_bank ? 0 : 0x20);
|
|
cmds += __adreno_add_idle_indirect_cmds(cmds, nop_gpuaddr);
|
|
return cmds - start;
|
|
}
|
|
|
|
/*
|
|
* adreno_read_cmds - Add pm4 packets to perform read
|
|
* @device - Pointer to device structure
|
|
* @cmds - Pointer to memory where read commands need to be added
|
|
* @addr - gpu address of the read
|
|
* @val - The GPU will wait until the data at address addr becomes
|
|
* equal to value
|
|
*/
|
|
static inline int adreno_add_read_cmds(struct kgsl_device *device,
|
|
unsigned int *cmds, unsigned int addr,
|
|
unsigned int val, unsigned int nop_gpuaddr)
|
|
{
|
|
unsigned int *start = cmds;
|
|
|
|
*cmds++ = cp_type3_packet(CP_WAIT_REG_MEM, 5);
|
|
/* MEM SPACE = memory, FUNCTION = equals */
|
|
*cmds++ = 0x13;
|
|
*cmds++ = addr;
|
|
*cmds++ = val;
|
|
*cmds++ = 0xFFFFFFFF;
|
|
*cmds++ = 0xFFFFFFFF;
|
|
|
|
/* WAIT_REG_MEM turns back on protected mode - push it off */
|
|
*cmds++ = cp_type3_packet(CP_SET_PROTECTED_MODE, 1);
|
|
*cmds++ = 0;
|
|
|
|
cmds += __adreno_add_idle_indirect_cmds(cmds, nop_gpuaddr);
|
|
return cmds - start;
|
|
}
|
|
|
|
/*
|
|
* adreno_idle_cmds - Add pm4 packets for GPU idle
|
|
* @adreno_dev - Pointer to device structure
|
|
* @cmds - Pointer to memory where idle commands need to be added
|
|
*/
|
|
static inline int adreno_add_idle_cmds(struct adreno_device *adreno_dev,
|
|
unsigned int *cmds)
|
|
{
|
|
unsigned int *start = cmds;
|
|
|
|
*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
|
|
*cmds++ = 0;
|
|
|
|
if ((adreno_dev->gpurev == ADRENO_REV_A305) ||
|
|
(adreno_dev->gpurev == ADRENO_REV_A305C) ||
|
|
(adreno_dev->gpurev == ADRENO_REV_A320)) {
|
|
*cmds++ = cp_type3_packet(CP_WAIT_FOR_ME, 1);
|
|
*cmds++ = 0;
|
|
}
|
|
|
|
return cmds - start;
|
|
}
|
|
|
|
/*
|
|
* adreno_wait_reg_eq() - Add a CP_WAIT_REG_EQ command
|
|
* @cmds: Pointer to memory where commands are to be added
|
|
* @addr: Regiater address to poll for
|
|
* @val: Value to poll for
|
|
* @mask: The value against which register value is masked
|
|
* @interval: wait interval
|
|
*/
|
|
static inline int adreno_wait_reg_eq(unsigned int *cmds, unsigned int addr,
|
|
unsigned int val, unsigned int mask,
|
|
unsigned int interval)
|
|
{
|
|
unsigned int *start = cmds;
|
|
*cmds++ = cp_type3_packet(CP_WAIT_REG_EQ, 4);
|
|
*cmds++ = addr;
|
|
*cmds++ = val;
|
|
*cmds++ = mask;
|
|
*cmds++ = interval;
|
|
return cmds - start;
|
|
}
|
|
|
|
/*
|
|
* adreno_set_protected_registers() - Protect the specified range of registers
|
|
* from being accessed by the GPU
|
|
* @device: pointer to the KGSL device
|
|
* @index: Pointer to the index of the protect mode register to write to
|
|
* @reg: Starting dword register to write
|
|
* @mask_len: Size of the mask to protect (# of registers = 2 ** mask_len)
|
|
*
|
|
* Add the range of registers to the list of protected mode registers that will
|
|
* cause an exception if the GPU accesses them. There are 16 available
|
|
* protected mode registers. Index is used to specify which register to write
|
|
* to - the intent is to call this function multiple times with the same index
|
|
* pointer for each range and the registers will be magically programmed in
|
|
* incremental fashion
|
|
*/
|
|
static inline void adreno_set_protected_registers(struct kgsl_device *device,
|
|
unsigned int *index, unsigned int reg, int mask_len)
|
|
{
|
|
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
|
|
unsigned int val;
|
|
|
|
/* This function is only for adreno A3XX and beyond */
|
|
BUG_ON(adreno_is_a2xx(adreno_dev));
|
|
|
|
/* There are only 16 registers available */
|
|
BUG_ON(*index >= 16);
|
|
|
|
val = 0x60000000 | ((mask_len & 0x1F) << 24) | ((reg << 2) & 0x1FFFF);
|
|
|
|
/*
|
|
* Write the protection range to the next available protection
|
|
* register
|
|
*/
|
|
|
|
kgsl_regwrite(device, A3XX_CP_PROTECT_REG_0 + *index, val);
|
|
*index = *index + 1;
|
|
}
|
|
|
|
#endif /*__ADRENO_H */
|