105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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void
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nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr,
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uint32_t size, uint32_t pitch, uint32_t flags)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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tile->addr = 0x80000000 | addr;
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tile->limit = max(1u, addr + size) - 1;
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tile->pitch = pitch;
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}
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void
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nv10_fb_free_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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tile->addr = tile->limit = tile->pitch = tile->zcomp = 0;
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}
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void
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nv10_fb_set_tile_region(struct drm_device *dev, int i)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
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nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit);
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nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch);
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nv_wr32(dev, NV10_PFB_TILE(i), tile->addr);
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}
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int
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nv1a_fb_vram_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct pci_dev *bridge;
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uint32_t mem, mib;
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bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
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if (!bridge) {
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NV_ERROR(dev, "no bridge device\n");
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return 0;
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}
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if (dev_priv->chipset == 0x1a) {
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pci_read_config_dword(bridge, 0x7c, &mem);
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mib = ((mem >> 6) & 31) + 1;
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} else {
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pci_read_config_dword(bridge, 0x84, &mem);
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mib = ((mem >> 4) & 127) + 1;
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}
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dev_priv->vram_size = mib * 1024 * 1024;
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return 0;
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}
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int
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nv10_fb_vram_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 fifo_data = nv_rd32(dev, NV04_PFB_FIFO_DATA);
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u32 cfg0 = nv_rd32(dev, 0x100200);
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dev_priv->vram_size = fifo_data & NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
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if (cfg0 & 0x00000001)
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dev_priv->vram_type = NV_MEM_TYPE_DDR1;
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else
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dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
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return 0;
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}
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int
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nv10_fb_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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int i;
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/* Turn all the tiling regions off. */
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pfb->num_tiles = NV10_PFB_TILE__SIZE;
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for (i = 0; i < pfb->num_tiles; i++)
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pfb->set_tile_region(dev, i);
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return 0;
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}
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void
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nv10_fb_takedown(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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int i;
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for (i = 0; i < pfb->num_tiles; i++)
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pfb->free_tile_region(dev, i);
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}
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