56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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int
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nv04_fb_vram_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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u32 boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
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if (boot0 & 0x00000100) {
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dev_priv->vram_size = ((boot0 >> 12) & 0xf) * 2 + 2;
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dev_priv->vram_size *= 1024 * 1024;
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} else {
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switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
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case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
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dev_priv->vram_size = 32 * 1024 * 1024;
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break;
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case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
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dev_priv->vram_size = 16 * 1024 * 1024;
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break;
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case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
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dev_priv->vram_size = 8 * 1024 * 1024;
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break;
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case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
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dev_priv->vram_size = 4 * 1024 * 1024;
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break;
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}
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}
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if ((boot0 & 0x00000038) <= 0x10)
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dev_priv->vram_type = NV_MEM_TYPE_SGRAM;
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else
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dev_priv->vram_type = NV_MEM_TYPE_SDRAM;
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return 0;
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}
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int
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nv04_fb_init(struct drm_device *dev)
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{
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/* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows
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* nvidia reading PFB_CFG_0, then writing back its original value.
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* (which was 0x701114 in this case)
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*/
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nv_wr32(dev, NV04_PFB_CFG0, 0x1114);
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return 0;
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}
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void
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nv04_fb_takedown(struct drm_device *dev)
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{
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}
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