226 lines
6.0 KiB
C
226 lines
6.0 KiB
C
/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/bitmap.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <mach/msm_iomap.h>
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#include <mach/gpiomux.h>
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#include "gpio-msm-common.h"
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/* Bits of interest in the GPIO_IN_OUT register.
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*/
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enum {
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GPIO_IN_BIT = 0,
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GPIO_OUT_BIT = 1
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};
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/* Bits of interest in the GPIO_INTR_STATUS register.
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*/
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enum {
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INTR_STATUS_BIT = 0,
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};
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/* Bits of interest in the GPIO_CFG register.
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*/
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enum {
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GPIO_OE_BIT = 9,
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};
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/* Bits of interest in the GPIO_INTR_CFG register.
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*/
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enum {
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INTR_ENABLE_BIT = 0,
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INTR_POL_CTL_BIT = 1,
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INTR_DECT_CTL_BIT = 2,
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INTR_RAW_STATUS_EN_BIT = 3,
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};
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/* Codes of interest in GPIO_INTR_CFG_SU.
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*/
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enum {
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TARGET_PROC_SCORPION = 4,
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TARGET_PROC_NONE = 7,
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};
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/*
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* There is no 'DC_POLARITY_LO' because the GIC is incapable
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* of asserting on falling edge or level-low conditions. Even though
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* the registers allow for low-polarity inputs, the case can never arise.
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*/
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enum {
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DC_POLARITY_HI = BIT(11),
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DC_IRQ_ENABLE = BIT(3),
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};
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/*
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* When a GPIO triggers, two separate decisions are made, controlled
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* by two separate flags.
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*
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* - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS
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* register for that GPIO will be updated to reflect the triggering of that
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* gpio. If this bit is 0, this register will not be updated.
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* - Second, INTR_ENABLE controls whether an interrupt is triggered.
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*
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* If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt
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* can be triggered but the status register will not reflect it.
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*/
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#define INTR_RAW_STATUS_EN BIT(INTR_RAW_STATUS_EN_BIT)
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#define INTR_ENABLE BIT(INTR_ENABLE_BIT)
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#define INTR_DECT_CTL_EDGE BIT(INTR_DECT_CTL_BIT)
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#define INTR_POL_CTL_HI BIT(INTR_POL_CTL_BIT)
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#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio)))
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#define DIR_CONN_INTR_CFG_SU(irq) (MSM_TLMM_BASE + 0x0700 + (0x04 * (irq)))
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#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
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#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
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#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio)))
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#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio)))
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static inline void set_gpio_bits(unsigned n, void __iomem *reg)
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{
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__raw_writel(__raw_readl(reg) | n, reg);
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}
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static inline void clr_gpio_bits(unsigned n, void __iomem *reg)
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{
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__raw_writel(__raw_readl(reg) & ~n, reg);
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}
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unsigned __msm_gpio_get_inout(unsigned gpio)
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{
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return __raw_readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN_BIT);
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}
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void __msm_gpio_set_inout(unsigned gpio, unsigned val)
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{
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__raw_writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(gpio));
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}
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void __msm_gpio_set_config_direction(unsigned gpio, int input, int val)
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{
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if (input)
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clr_gpio_bits(BIT(GPIO_OE_BIT), GPIO_CONFIG(gpio));
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else {
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__msm_gpio_set_inout(gpio, val);
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set_gpio_bits(BIT(GPIO_OE_BIT), GPIO_CONFIG(gpio));
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}
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}
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void __msm_gpio_set_polarity(unsigned gpio, unsigned val)
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{
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if (val)
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clr_gpio_bits(INTR_POL_CTL_HI, GPIO_INTR_CFG(gpio));
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else
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set_gpio_bits(INTR_POL_CTL_HI, GPIO_INTR_CFG(gpio));
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}
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unsigned __msm_gpio_get_intr_status(unsigned gpio)
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{
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return __raw_readl(GPIO_INTR_STATUS(gpio)) &
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BIT(INTR_STATUS_BIT);
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}
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void __msm_gpio_set_intr_status(unsigned gpio)
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{
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__raw_writel(BIT(INTR_STATUS_BIT), GPIO_INTR_STATUS(gpio));
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}
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unsigned __msm_gpio_get_intr_config(unsigned gpio)
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{
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return __raw_readl(GPIO_INTR_CFG(gpio));
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}
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void __msm_gpio_set_intr_cfg_enable(unsigned gpio, unsigned val)
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{
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if (val) {
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set_gpio_bits(INTR_ENABLE, GPIO_INTR_CFG(gpio));
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} else {
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clr_gpio_bits(INTR_ENABLE, GPIO_INTR_CFG(gpio));
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}
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}
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unsigned __msm_gpio_get_intr_cfg_enable(unsigned gpio)
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{
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return __msm_gpio_get_intr_config(gpio) & INTR_ENABLE;
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}
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void __msm_gpio_set_intr_cfg_type(unsigned gpio, unsigned type)
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{
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unsigned cfg;
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/* RAW_STATUS_EN is left on for all gpio irqs. Due to the
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* internal circuitry of TLMM, toggling the RAW_STATUS
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* could cause the INTR_STATUS to be set for EDGE interrupts.
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*/
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cfg = __msm_gpio_get_intr_config(gpio);
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cfg |= INTR_RAW_STATUS_EN;
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__raw_writel(cfg, GPIO_INTR_CFG(gpio));
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__raw_writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio));
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cfg = __msm_gpio_get_intr_config(gpio);
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if (type & IRQ_TYPE_EDGE_BOTH)
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cfg |= INTR_DECT_CTL_EDGE;
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else
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cfg &= ~INTR_DECT_CTL_EDGE;
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if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
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cfg |= INTR_POL_CTL_HI;
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else
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cfg &= ~INTR_POL_CTL_HI;
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__raw_writel(cfg, GPIO_INTR_CFG(gpio));
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/* Sometimes it might take a little while to update
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* the interrupt status after the RAW_STATUS is enabled
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* We clear the interrupt status before enabling the
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* interrupt in the unmask call-back.
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*/
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udelay(5);
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}
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void __gpio_tlmm_config(unsigned config)
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{
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uint32_t flags;
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unsigned gpio = GPIO_PIN(config);
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flags = ((GPIO_DIR(config) << 9) & (0x1 << 9)) |
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((GPIO_DRVSTR(config) << 6) & (0x7 << 6)) |
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((GPIO_FUNC(config) << 2) & (0xf << 2)) |
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((GPIO_PULL(config) & 0x3));
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__raw_writel(flags, GPIO_CONFIG(gpio));
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}
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void __msm_gpio_install_direct_irq(unsigned gpio, unsigned irq,
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unsigned int input_polarity)
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{
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uint32_t bits;
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__raw_writel(__raw_readl(GPIO_CONFIG(gpio)) | BIT(GPIO_OE_BIT),
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GPIO_CONFIG(gpio));
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__raw_writel(__raw_readl(GPIO_INTR_CFG(gpio)) &
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~(INTR_RAW_STATUS_EN | INTR_ENABLE),
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GPIO_INTR_CFG(gpio));
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__raw_writel(DC_IRQ_ENABLE | TARGET_PROC_NONE,
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GPIO_INTR_CFG_SU(gpio));
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bits = TARGET_PROC_SCORPION | (gpio << 3);
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if (input_polarity)
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bits |= DC_POLARITY_HI;
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__raw_writel(bits, DIR_CONN_INTR_CFG_SU(irq));
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}
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