175 lines
4.0 KiB
C
175 lines
4.0 KiB
C
/* linux/arch/arm/mach-s3c2443/dma.c
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*
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* Copyright (c) 2007 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2443 DMA selection
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*
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/serial_core.h>
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#include <linux/io.h>
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#include <mach/dma.h>
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#include <plat/dma-s3c24xx.h>
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#include <plat/cpu.h>
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#include <plat/regs-serial.h>
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#include <mach/regs-gpio.h>
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#include <plat/regs-ac97.h>
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#include <plat/regs-dma.h>
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#include <mach/regs-mem.h>
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#include <mach/regs-lcd.h>
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#include <mach/regs-sdi.h>
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#include <plat/regs-iis.h>
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#include <plat/regs-spi.h>
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#define MAP(x) { \
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[0] = (x) | DMA_CH_VALID, \
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[1] = (x) | DMA_CH_VALID, \
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[2] = (x) | DMA_CH_VALID, \
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[3] = (x) | DMA_CH_VALID, \
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[4] = (x) | DMA_CH_VALID, \
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[5] = (x) | DMA_CH_VALID, \
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}
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static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
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[DMACH_XD0] = {
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.name = "xdreq0",
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.channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
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},
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[DMACH_XD1] = {
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.name = "xdreq1",
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.channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
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},
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[DMACH_SDI] = { /* only on S3C2443 */
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.name = "sdi",
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.channels = MAP(S3C2443_DMAREQSEL_SDI),
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},
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[DMACH_SPI0] = {
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.name = "spi0",
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.channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
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},
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[DMACH_SPI1] = { /* only on S3C2443/S3C2450 */
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.name = "spi1",
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.channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
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},
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[DMACH_UART0] = {
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.name = "uart0",
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.channels = MAP(S3C2443_DMAREQSEL_UART0_0),
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},
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[DMACH_UART1] = {
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.name = "uart1",
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.channels = MAP(S3C2443_DMAREQSEL_UART1_0),
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},
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[DMACH_UART2] = {
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.name = "uart2",
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.channels = MAP(S3C2443_DMAREQSEL_UART2_0),
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},
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[DMACH_UART3] = {
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.name = "uart3",
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.channels = MAP(S3C2443_DMAREQSEL_UART3_0),
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},
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[DMACH_UART0_SRC2] = {
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.name = "uart0",
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.channels = MAP(S3C2443_DMAREQSEL_UART0_1),
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},
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[DMACH_UART1_SRC2] = {
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.name = "uart1",
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.channels = MAP(S3C2443_DMAREQSEL_UART1_1),
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},
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[DMACH_UART2_SRC2] = {
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.name = "uart2",
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.channels = MAP(S3C2443_DMAREQSEL_UART2_1),
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},
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[DMACH_UART3_SRC2] = {
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.name = "uart3",
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.channels = MAP(S3C2443_DMAREQSEL_UART3_1),
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},
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[DMACH_TIMER] = {
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.name = "timer",
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.channels = MAP(S3C2443_DMAREQSEL_TIMER),
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},
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[DMACH_I2S_IN] = {
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.name = "i2s-sdi",
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.channels = MAP(S3C2443_DMAREQSEL_I2SRX),
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},
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[DMACH_I2S_OUT] = {
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.name = "i2s-sdo",
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.channels = MAP(S3C2443_DMAREQSEL_I2STX),
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},
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[DMACH_PCM_IN] = {
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.name = "pcm-in",
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.channels = MAP(S3C2443_DMAREQSEL_PCMIN),
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},
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[DMACH_PCM_OUT] = {
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.name = "pcm-out",
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.channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
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},
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[DMACH_MIC_IN] = {
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.name = "mic-in",
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.channels = MAP(S3C2443_DMAREQSEL_MICIN),
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},
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};
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static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
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struct s3c24xx_dma_map *map)
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{
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writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
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chan->regs + S3C2443_DMA_DMAREQSEL);
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}
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static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
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.select = s3c2443_dma_select,
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.dcon_mask = 0,
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.map = s3c2443_dma_mappings,
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.map_size = ARRAY_SIZE(s3c2443_dma_mappings),
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};
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static int __init s3c2443_dma_add(struct device *dev,
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struct subsys_interface *sif)
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{
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s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
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return s3c24xx_dma_init_map(&s3c2443_dma_sel);
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}
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#ifdef CONFIG_CPU_S3C2416
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/* S3C2416 DMA contains the same selection table as the S3C2443 */
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static struct subsys_interface s3c2416_dma_interface = {
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.name = "s3c2416_dma",
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.subsys = &s3c2416_subsys,
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.add_dev = s3c2443_dma_add,
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};
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static int __init s3c2416_dma_init(void)
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{
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return subsys_interface_register(&s3c2416_dma_interface);
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}
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arch_initcall(s3c2416_dma_init);
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#endif
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#ifdef CONFIG_CPU_S3C2443
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static struct subsys_interface s3c2443_dma_interface = {
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.name = "s3c2443_dma",
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.subsys = &s3c2443_subsys,
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.add_dev = s3c2443_dma_add,
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};
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static int __init s3c2443_dma_init(void)
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{
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return subsys_interface_register(&s3c2443_dma_interface);
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}
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arch_initcall(s3c2443_dma_init);
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#endif
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