167 lines
4.0 KiB
C
167 lines
4.0 KiB
C
/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include "sirc.h"
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static unsigned int sirc_int_enable[2];
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static struct sirc_regs_t sirc_regs = {
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.int_enable = SPSS_SIRC_INT_ENABLE,
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.int_type = SPSS_SIRC_INT_TYPE,
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.int_polarity = SPSS_SIRC_INT_POLARITY,
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.int_clear = SPSS_SIRC_INT_CLEAR,
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};
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static inline void sirc_get_group_offset_mask(unsigned int irq,
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unsigned int *group, unsigned int *offset, unsigned int *mask)
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{
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*group = 0;
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*offset = irq - FIRST_SIRC_IRQ;
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if (*offset >= NR_SIRC_IRQS_GROUPA) {
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*group = 1;
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*offset -= NR_SIRC_IRQS_GROUPA;
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}
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*mask = 1 << *offset;
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}
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static void sirc_irq_mask(struct irq_data *d)
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{
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void *reg_enable;
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unsigned int group, offset, mask;
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unsigned int val;
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sirc_get_group_offset_mask(d->irq, &group, &offset, &mask);
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reg_enable = sirc_regs.int_enable + group * 4;
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val = __raw_readl(reg_enable);
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__raw_writel(val & ~mask, reg_enable);
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sirc_int_enable[group] &= ~mask;
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mb();
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}
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static void sirc_irq_unmask(struct irq_data *d)
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{
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void *reg_enable;
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void *reg_clear;
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unsigned int group, offset, mask;
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unsigned int val;
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sirc_get_group_offset_mask(d->irq, &group, &offset, &mask);
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if (irq_desc[d->irq].handle_irq == handle_level_irq) {
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reg_clear = sirc_regs.int_clear + group * 4;
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__raw_writel(mask, reg_clear);
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}
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reg_enable = sirc_regs.int_enable + group * 4;
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val = __raw_readl(reg_enable);
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__raw_writel(val | mask, reg_enable);
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sirc_int_enable[group] |= mask;
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mb();
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}
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static void sirc_irq_ack(struct irq_data *d)
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{
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void *reg_clear;
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unsigned int group, offset, mask;
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sirc_get_group_offset_mask(d->irq, &group, &offset, &mask);
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reg_clear = sirc_regs.int_clear + group * 4;
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__raw_writel(mask, reg_clear);
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}
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static int sirc_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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return 0;
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}
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static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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void *reg_polarity, *reg_type;
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unsigned int group, offset, mask;
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unsigned int val;
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sirc_get_group_offset_mask(d->irq, &group, &offset, &mask);
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reg_polarity = sirc_regs.int_polarity + group * 4;
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val = __raw_readl(reg_polarity);
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if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
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val &= ~mask;
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else
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val |= mask;
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__raw_writel(val, reg_polarity);
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reg_type = sirc_regs.int_type + group * 4;
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val = __raw_readl(reg_type);
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if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
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val |= mask;
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irq_desc[d->irq].handle_irq = handle_edge_irq;
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} else {
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val &= ~mask;
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irq_desc[d->irq].handle_irq = handle_level_irq;
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}
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__raw_writel(val, reg_type);
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return 0;
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}
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/* Finds the pending interrupt on the passed cascade irq and redrives it */
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static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned int sirq;
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for (;;) {
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sirq = __raw_readl(SPSS_SIRC_VEC_INDEX_RD);
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if (sirq >= NR_SIRC_IRQS)
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break;
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generic_handle_irq(sirq + FIRST_SIRC_IRQ);
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}
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irq_desc_get_chip(desc)->irq_ack(irq_get_irq_data(irq));
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}
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static struct irq_chip sirc_irq_chip = {
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.name = "sirc",
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.irq_ack = sirc_irq_ack,
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.irq_mask = sirc_irq_mask,
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.irq_unmask = sirc_irq_unmask,
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.irq_set_wake = sirc_irq_set_wake,
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.irq_set_type = sirc_irq_set_type,
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};
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void __init msm_init_sirc(void)
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{
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int i;
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sirc_int_enable[0] = 0;
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sirc_int_enable[1] = 0;
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for (i = FIRST_SIRC_IRQ; i <= LAST_SIRC_IRQ; i++) {
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irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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irq_set_chained_handler(INT_SIRC_0, sirc_irq_handler);
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irq_set_irq_wake(INT_SIRC_0, 1);
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}
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