264 lines
6.7 KiB
C
264 lines
6.7 KiB
C
/* linux/arch/arm/mach-msm/board-swordfish-mmc.c
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*
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* Copyright (C) 2008 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/sdio_ids.h>
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#include <linux/platform_device.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/mach/mmc.h>
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#include <mach/vreg.h>
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#include <mach/proc_comm.h>
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#include "devices.h"
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#define FPGA_BASE 0x70000000
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#define FPGA_SDIO_STATUS 0x280
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static void __iomem *fpga_base;
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#define DEBUG_SWORDFISH_MMC 1
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extern int msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat,
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unsigned int stat_irq, unsigned long stat_irq_flags);
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static int config_gpio_table(unsigned *table, int len, int enable)
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{
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int n;
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int rc = 0;
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for (n = 0; n < len; n++) {
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unsigned dis = !enable;
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unsigned id = table[n];
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if (msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &id, &dis)) {
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pr_err("%s: id=0x%08x dis=%d\n", __func__, table[n],
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dis);
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rc = -1;
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}
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}
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return rc;
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}
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static unsigned sdc1_gpio_table[] = {
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PCOM_GPIO_CFG(51, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(52, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(53, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(54, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(55, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(56, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA),
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};
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static unsigned sdc2_gpio_table[] = {
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PCOM_GPIO_CFG(62, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA),
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PCOM_GPIO_CFG(63, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(64, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(65, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(66, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(67, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_4MA),
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};
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static unsigned sdc3_gpio_table[] = {
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PCOM_GPIO_CFG(88, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA),
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PCOM_GPIO_CFG(89, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(90, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(91, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(92, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(93, 1, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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};
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static unsigned sdc4_gpio_table[] = {
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PCOM_GPIO_CFG(142, 3, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_4MA),
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PCOM_GPIO_CFG(143, 3, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(144, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(145, 2, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(146, 3, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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PCOM_GPIO_CFG(147, 3, GPIO_OUTPUT, GPIO_PULL_UP, GPIO_8MA),
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};
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struct sdc_info {
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unsigned *table;
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unsigned len;
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};
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static struct sdc_info sdcc_gpio_tables[] = {
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[0] = {
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.table = sdc1_gpio_table,
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.len = ARRAY_SIZE(sdc1_gpio_table),
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},
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[1] = {
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.table = sdc2_gpio_table,
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.len = ARRAY_SIZE(sdc2_gpio_table),
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},
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[2] = {
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.table = sdc3_gpio_table,
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.len = ARRAY_SIZE(sdc3_gpio_table),
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},
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[3] = {
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.table = sdc4_gpio_table,
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.len = ARRAY_SIZE(sdc4_gpio_table),
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},
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};
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static int swordfish_sdcc_setup_gpio(int dev_id, unsigned enable)
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{
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struct sdc_info *info;
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if (dev_id < 1 || dev_id > 4)
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return -1;
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info = &sdcc_gpio_tables[dev_id - 1];
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return config_gpio_table(info->table, info->len, enable);
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}
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struct mmc_vdd_xlat {
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int mask;
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int level;
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};
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static struct mmc_vdd_xlat mmc_vdd_table[] = {
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{ MMC_VDD_165_195, 1800 },
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{ MMC_VDD_20_21, 2050 },
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{ MMC_VDD_21_22, 2150 },
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{ MMC_VDD_22_23, 2250 },
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{ MMC_VDD_23_24, 2350 },
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{ MMC_VDD_24_25, 2450 },
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{ MMC_VDD_25_26, 2550 },
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{ MMC_VDD_26_27, 2650 },
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{ MMC_VDD_27_28, 2750 },
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{ MMC_VDD_28_29, 2850 },
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{ MMC_VDD_29_30, 2950 },
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};
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static struct vreg *vreg_sdcc;
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static unsigned int vreg_sdcc_enabled;
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static unsigned int sdcc_vdd = 0xffffffff;
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static uint32_t sdcc_translate_vdd(struct device *dev, unsigned int vdd)
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{
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int i;
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int rc = 0;
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struct platform_device *pdev;
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pdev = container_of(dev, struct platform_device, dev);
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BUG_ON(!vreg_sdcc);
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if (vdd == sdcc_vdd)
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return 0;
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sdcc_vdd = vdd;
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/* enable/disable the signals to the slot */
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swordfish_sdcc_setup_gpio(pdev->id, !!vdd);
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/* power down */
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if (vdd == 0) {
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#if DEBUG_SWORDFISH_MMC
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pr_info("%s: disable sdcc power\n", __func__);
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#endif
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vreg_disable(vreg_sdcc);
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vreg_sdcc_enabled = 0;
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return 0;
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}
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if (!vreg_sdcc_enabled) {
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rc = vreg_enable(vreg_sdcc);
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if (rc)
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pr_err("%s: Error enabling vreg (%d)\n", __func__, rc);
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vreg_sdcc_enabled = 1;
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}
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for (i = 0; i < ARRAY_SIZE(mmc_vdd_table); i++) {
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if (mmc_vdd_table[i].mask != (1 << vdd))
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continue;
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#if DEBUG_SWORDFISH_MMC
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pr_info("%s: Setting level to %u\n", __func__,
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mmc_vdd_table[i].level);
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#endif
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rc = vreg_set_level(vreg_sdcc, mmc_vdd_table[i].level);
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if (rc)
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pr_err("%s: Error setting vreg level (%d)\n", __func__, rc);
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return 0;
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}
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pr_err("%s: Invalid VDD %d specified\n", __func__, vdd);
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return 0;
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}
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static unsigned int swordfish_sdcc_slot_status (struct device *dev)
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{
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struct platform_device *pdev;
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uint32_t sdcc_stat;
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pdev = container_of(dev, struct platform_device, dev);
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sdcc_stat = readl(fpga_base + FPGA_SDIO_STATUS);
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/* bit 0 - sdcc1 crd_det
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* bit 1 - sdcc1 wr_prt
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* bit 2 - sdcc2 crd_det
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* bit 3 - sdcc2 wr_prt
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* etc...
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*/
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/* crd_det is active low */
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return !(sdcc_stat & (1 << ((pdev->id - 1) << 1)));
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}
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#define SWORDFISH_MMC_VDD (MMC_VDD_165_195 | MMC_VDD_20_21 | MMC_VDD_21_22 \
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| MMC_VDD_22_23 | MMC_VDD_23_24 | MMC_VDD_24_25 \
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| MMC_VDD_25_26 | MMC_VDD_26_27 | MMC_VDD_27_28 \
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| MMC_VDD_28_29 | MMC_VDD_29_30)
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static struct mmc_platform_data swordfish_sdcc_data = {
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.ocr_mask = SWORDFISH_MMC_VDD/*MMC_VDD_27_28 | MMC_VDD_28_29*/,
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.status = swordfish_sdcc_slot_status,
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.translate_vdd = sdcc_translate_vdd,
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};
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int __init swordfish_init_mmc(void)
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{
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vreg_sdcc_enabled = 0;
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vreg_sdcc = vreg_get(NULL, "gp5");
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if (IS_ERR(vreg_sdcc)) {
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pr_err("%s: vreg get failed (%ld)\n",
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__func__, PTR_ERR(vreg_sdcc));
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return PTR_ERR(vreg_sdcc);
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}
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fpga_base = ioremap(FPGA_BASE, SZ_4K);
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if (!fpga_base) {
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pr_err("%s: Can't ioremap FPGA base address (0x%08x)\n",
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__func__, FPGA_BASE);
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vreg_put(vreg_sdcc);
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return -EIO;
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}
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msm_add_sdcc(1, &swordfish_sdcc_data, 0, 0);
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msm_add_sdcc(4, &swordfish_sdcc_data, 0, 0);
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return 0;
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}
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