484 lines
20 KiB
ArmAsm
484 lines
20 KiB
ArmAsm
/*
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* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
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* Copyright (c) 2008-2009, Google Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* TODO:
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* - style cleanup
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* - do we need to do *all* of this at boot?
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*/
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.text
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.code 32
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#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
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#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
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.equ TCSR_SPARE2, 0xA8700060
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SET_SA:
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ldr r0, =TCSR_SPARE2
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ldr r12, [r0]
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/* pack bits 8,2,0 into 2,1,0 */
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and r0, r12, #0x001
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and r1, r12, #0x004
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and r2, r12, #0x100
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orr r0, r1, lsr #1
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orr r0, r2, lsr #6
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adr r1, table_l1_acc
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mov r0, r0, lsl #2
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ldr r3, [r1, r0]
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/* write 3800XXXX to PVR0F0 */
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orr r0, r3, #0x38000000
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mcr p15, 0, r0, c15, c15, 0
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/* write XXXX0000 to PVR2F0 */
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mov r1, r3, lsl #16
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mcr p15, 2, r1, c15, c15, 0
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adr r1, table_l2_acc
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and r0, r12, #0x008
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and r2, r12, #0x002
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orr r0, r0, r2, lsl #1
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ldr r2, [r1, r0]
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/* write to L2VR3F1 */
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mcr p15, 3, r2, c15, c15, 1
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bx lr
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table_l1_acc:
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.word 0xFC00
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.word 0xFC00
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.word 0x7C00
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.word 0xFC00
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.word 0x3C00
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.word 0x0400
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.word 0x0C00
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.word 0x1C00
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table_l2_acc:
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.word 0x010102
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.word 0x010102
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.word 0x010101
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.word 0x212102
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.globl __cpu_early_init
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__cpu_early_init:
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//; Zero out r0 for use throughout this code. All other GPRs
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//; (r1-r3) are set throughout this code to help establish
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//; a consistent startup state for any code that follows.
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//; Users should add code at the end of this routine to establish
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//; their own stack address (r13), add translation page tables, enable
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//; the caches, etc.
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MOV r0, #0x0
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//; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
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//; API to dynamically configure cache for slow/nominal/fast parts
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//; DCIALL to invalidate L2 cache bank (needs to be run 4 times, once per bank)
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//; This must be done early in code (prior to enabling the caches)
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MOV r1, #0x2
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MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
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ORR r1, r1, #0x00004000
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MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
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ADD r1, r1, #0x00004000
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MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
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ADD r1, r1, #0x00004000
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MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
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//; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
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//; and have all address bits (AM) participate.
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//; Different settings can be used to improve performance
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// MOVW r1, #0x01FF
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.word 0xe30011ff // hardcoded MOVW instruction due to lack of compiler support
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// MOVT r1, #0x01FF
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.word 0xe34011ff // hardcoded MOVT instruction due to lack of compiler support
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MCR p15, 7, r1, c15, c0, 2 //; WCP15_BPCR
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//; Initialize all I$ Victim Registers to 0 for startup
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MCR p15, 0, r0, c9, c1, 0 //; WCP15_ICVIC0 r0
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MCR p15, 0, r0, c9, c1, 1 //; WCP15_ICVIC1 r0
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MCR p15, 0, r0, c9, c1, 2 //; WCP15_ICVIC2 r0
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MCR p15, 0, r0, c9, c1, 3 //; WCP15_ICVIC3 r0
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MCR p15, 0, r0, c9, c1, 4 //; WCP15_ICVIC4 r0
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MCR p15, 0, r0, c9, c1, 5 //; WCP15_ICVIC5 r0
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MCR p15, 0, r0, c9, c1, 6 //; WCP15_ICVIC5 r0
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MCR p15, 0, r0, c9, c1, 7 //; WCP15_ICVIC7 r0
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//; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
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MCR p15, 1, r0, c9, c1, 0 //; WCP15_ICFLOOR0 r0
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MCR p15, 1, r0, c9, c1, 1 //; WCP15_ICFLOOR1 r0
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MCR p15, 1, r0, c9, c1, 2 //; WCP15_ICFLOOR2 r0
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MCR p15, 1, r0, c9, c1, 3 //; WCP15_ICFLOOR3 r0
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MCR p15, 1, r0, c9, c1, 4 //; WCP15_ICFLOOR4 r0
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MCR p15, 1, r0, c9, c1, 5 //; WCP15_ICFLOOR5 r0
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MCR p15, 1, r0, c9, c1, 6 //; WCP15_ICFLOOR6 r0
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MCR p15, 1, r0, c9, c1, 7 //; WCP15_ICFLOOR7 r0
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//; Initialize all D$ Victim Registers to 0
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MCR p15, 2, r0, c9, c1, 0 //; WP15_DCVIC0 r0
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MCR p15, 2, r0, c9, c1, 1 //; WP15_DCVIC1 r0
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MCR p15, 2, r0, c9, c1, 2 //; WP15_DCVIC2 r0
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MCR p15, 2, r0, c9, c1, 3 //; WP15_DCVIC3 r0
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MCR p15, 2, r0, c9, c1, 4 //; WP15_DCVIC4 r0
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MCR p15, 2, r0, c9, c1, 5 //; WP15_DCVIC5 r0
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MCR p15, 2, r0, c9, c1, 6 //; WP15_DCVIC6 r0
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MCR p15, 2, r0, c9, c1, 7 //; WP15_DCVIC7 r0
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//; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
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MCR p15, 3, r0, c9, c1, 0 //; WCP15_DCFLOOR0 r0
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MCR p15, 3, r0, c9, c1, 1 //; WCP15_DCFLOOR1 r0
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MCR p15, 3, r0, c9, c1, 2 //; WCP15_DCFLOOR2 r0
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MCR p15, 3, r0, c9, c1, 3 //; WCP15_DCFLOOR3 r0
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MCR p15, 3, r0, c9, c1, 4 //; WCP15_DCFLOOR4 r0
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MCR p15, 3, r0, c9, c1, 5 //; WCP15_DCFLOOR5 r0
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MCR p15, 3, r0, c9, c1, 6 //; WCP15_DCFLOOR6 r0
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MCR p15, 3, r0, c9, c1, 7 //; WCP15_DCFLOOR7 r0
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//; Initialize ASID to zero
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MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
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//; ICIALL to invalidate entire I-Cache
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MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
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//; DCIALL to invalidate entire D-Cache
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MCR p15, 0, r0, c9, c0, 6 //; DCIALL r0
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//; The VBAR (Vector Base Address Register) should be initialized
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//; early in your code. We are setting it to zero
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MCR p15, 0, r0, c12, c0, 0 //; WCP15_VBAR r0
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//; Ensure the MCR's above have completed their operation before continuing
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DSB
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ISB
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//;-------------------------------------------------------------------
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//; There are a number of registers that must be set prior to enabling
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//; the MMU. The DCAR is one of these registers. We are setting
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//; it to zero (no access) to easily detect improper setup in subsequent
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//; code sequences
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//;-------------------------------------------------------------------
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//; Setup DACR (Domain Access Control Register) to zero
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MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
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//; Setup DCLKCR to allow normal D-Cache line fills
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MCR p15, 1, r0, c9, c0, 7 //; WCP15_DCLKCR r0
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//; Initialize the ADFSR and EFSR registers.
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MCR p15, 0, r0, c5, c1, 0 //; ADFSR
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MCR p15, 7, r0, c15, c0, 1 //; EFSR
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//; Setup the TLBLKCR
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//; Victim = 6'b000000; Floor = 6'b000000;
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//; IASIDCFG = 2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
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MOV r1, #0x02
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MCR p15, 0, r1, c10, c1, 3 //; WCP15_TLBLKCR r1
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//;Make sure TLBLKCR is complete before continuing
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ISB
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//; Invalidate the UTLB
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MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
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//; Make sure UTLB request has been presented to macro before continuing
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ISB
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//; setup L2CR1 to some default Instruction and data prefetching values
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//; Users may want specific settings for various performance enhancements
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//; In Halcyon we do not have broadcasting barriers. So we need to turn
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// ; on bit 8 of L2CR1; which DBB:( Disable barrier broadcast )
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MOV r2, #0x100
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MCR p15, 3, r2, c15, c0, 3 //; WCP15_L2CR1 r0
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//; Enable Z bit to enable branch prediction (default is off)
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MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
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ORR r2, r2, #0x00000800
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MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
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#ifdef CONFIG_ARCH_QSD8X50
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/* disable predecode repair cache for thumb2 (DPRC, set bit 4 in PVR0F2) */
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mrc p15, 0, r2, c15, c15, 2
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orr r2, r2, #0x10
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mcr p15, 0, r2, c15, c15, 2
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#endif
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mov r1, lr
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//; Make sure Link stack is initialized with branch and links to sequential addresses
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//; This aids in creating a predictable startup environment
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BL SEQ1
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SEQ1: BL SEQ2
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SEQ2: BL SEQ3
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SEQ3: BL SEQ4
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SEQ4: BL SEQ5
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SEQ5: BL SEQ6
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SEQ6: BL SEQ7
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SEQ7: BL SEQ8
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SEQ8:
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mov lr, r1
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//; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
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//;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
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//; Writing anything but the "secret code" to the DBGOSLAR clears the DBGOSLSR[LOCK] bit
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MCR p14, 0, r0, c1, c0, 4 //; WCP14_DBGOSLAR r0
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//; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
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//; Any read to DBGPRSR clear the STICKYPD bit
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//; ISB guarantees the read completes before attempting to
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//; execute a CP14 instruction.
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MRC p14, 0, r3, c1, c5, 4 //; RCP14_DBGPRSR r3
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ISB
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//; Initialize the Watchpoint Control Registers to zero (optional)
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//;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
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//;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
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//;----------------------------------------------------------------------
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//; The saved Program Status Registers (SPSRs) should be setup
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//; prior to any automatic mode switches. The following
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//; code sets these registers up to a known state. Users will need to
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//; customize these settings to meet their needs.
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//;----------------------------------------------------------------------
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MOV r2, #0x1f
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MOV r1, #0x17 //;ABT mode
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msr cpsr_c, r1 //;ABT mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0x1b //;UND mode
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msr cpsr_c, r1 //;UND mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0x11 //;FIQ mode
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msr cpsr_c, r1 //;FIQ mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0x12 //;IRQ mode
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msr cpsr_c, r1 //;IRQ mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0x16 //;Monitor mode
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msr cpsr_c, r1 //;Monitor mode
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msr spsr_cxfs, r2 //;clear the spsr
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MOV r1, #0x13 //;SVC mode
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msr cpsr_c, r1 //;SVC mode
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msr spsr_cxfs, r2 //;clear the spsr
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//;----------------------------------------------------------------------
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//; Enabling Error reporting is something users may want to do at
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//; some other point in time. We have chosen some default settings
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//; that should be reviewed. Most of these registers come up in an
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//; unpredictable state after reset.
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//;----------------------------------------------------------------------
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//;Start of error and control setting
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//; setup L2CR0 with various L2/TCM control settings
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//; enable out of order bus attributes and error reporting
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//; this register comes up unpredictable after reset
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// MOVW r1, #0x0F0F
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.word 0xe3001f0f // hardcoded MOVW instruction due to lack of compiler support
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// MOVT r1, #0xC005
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.word 0xe34c1005 // hardcoded MOVW instruction due to lack of compiler support
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MCR p15, 3, r1, c15, c0, 1 //; WCP15_L2CR0 r1
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//; setup L2CPUCR
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//; MOV r2, #0xFF
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//; Enable I and D cache parity
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//;L2CPUCR[7:5] = 3~Rh7 ~V enable parity error reporting for modified,
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//;tag, and data parity errors
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MOV r2, #0xe0
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MCR p15, 3, r2, c15, c0, 2 //; WCP15_L2CPUCR r2
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//; setup SPCR
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//; enable all error reporting (reset value is unpredicatble for most bits)
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MOV r3, #0x0F
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MCR p15, 0, r3, c9, c7, 0 //; WCP15_SPCR r3
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//; setup DMACHCRs (reset value unpredictable)
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//; control setting and enable all error reporting
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MOV r1, #0x0F
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//; DMACHCR0 = 0000000F
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MOV r2, #0x00 //; channel 0
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MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
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MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
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//; DMACHCR1 = 0000000F
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MOV r2, #0x01 //; channel 1
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MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
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MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
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//; DMACHCR2 = 0000000F
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MOV r2, #0x02 //; channel 2
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MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
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MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
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//; DMACHCR3 = 0000000F
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MOV r2, #0x03 //; channel 3
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MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
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MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
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//; Set ACTLR (reset unpredictable)
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//; Set AVIVT control, error reporting, etc.
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//; MOV r3, #0x07
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//; Enable I and D cache parity
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//;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
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//;ACTLR[5:4] = 2'h3 - enable parity
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//;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled).
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//;Value to be written #0xC0037
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// MOVW r3, #0x0037
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.word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support
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// MOVT r3, #0x000C
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.word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support
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//; read the version_id to determine if d-cache should be disabled
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LDR r2, = 0xa8e00270 //;Read HW_REVISION_NUMBER, HWIO_HW_REVISION_NUMBER_ADDR
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LDR r2,[r2]
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AND r2,r2,#0xf0000000 //;hw_revision mask off bits 28-31
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//;if HW_revision is 1.0 or older, (revision==0)
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CMP r2,#0
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//; Disable d-cache on older QSD8650 (Rev 1.0) silicon
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orreq r3, r3, #0x4000 //;disable dcache
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MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
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//;End of error and control setting
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//;----------------------------------------------------------------------
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//; Unlock ETM and read StickyPD to halt the ETM clocks from running.
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//; This is required for power saving whether the ETM is used or not.
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//;----------------------------------------------------------------------
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//;Clear ETMOSLSR[LOCK] bit
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MOV r1, #0x00000000
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MCR p14, 1, r1, c1, c0, 4 //; WCP14_ETMOSLAR r1
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//;Clear ETMPDSR[STICKYPD] bit
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MRC p14, 1, r2, c1, c5, 4 //; RCP14_ETMPDSR r2
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/*
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#ifdef APPSBL_ETM_ENABLE
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;----------------------------------------------------------------------
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; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
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;----------------------------------------------------------------------
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; enable ETM clock if disabled
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MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
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ORR r1, r1, #0x00000008
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MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
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ISB
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; set trigger event to counter1 being zero
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MOV r3, #0x00000040
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MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
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; clear ETMSR
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MOV r2, #0x00000000
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MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
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|
|
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; clear trace enable single address comparator usage
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MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
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|
|
; set trace enable to always
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MOV r2, #0x0000006F
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MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
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|
|
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; clear trace enable address range comparator usage and exclude nothing
|
|
MOV r2, #0x01000000
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MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
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|
|
|
; set view data to always
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|
MOV r2, #0x0000006F
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|
MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
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|
|
|
; clear view data single address comparator usage
|
|
MOV r2, #0x00000000
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|
MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
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|
|
|
; clear view data address range comparator usage and exclude nothing
|
|
MOV r2, #0x00010000
|
|
MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
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|
|
|
; set counter1 to 194
|
|
MOV r2, #0x000000C2
|
|
MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
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|
|
|
; set counter1 to never reload
|
|
MOV r2, #0x0000406F
|
|
MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
|
|
|
|
; set counter1 to decrement every cycle
|
|
MOV r2, #0x0000006F
|
|
MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
|
|
|
|
; Set trace synchronization frequency 1024 bytes
|
|
MOV r2, #0x00000400
|
|
MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
|
|
|
|
; Program etm control register
|
|
; - Set the CPU to ETM clock ratio to 1:1
|
|
; - Set the ETM to perform data address tracing
|
|
MOV r2, #0x00002008
|
|
MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
|
|
ISB
|
|
#endif *//* APPSBL_ETM_ENABLE */
|
|
|
|
/*
|
|
#ifdef APPSBL_VFP_ENABLE
|
|
;----------------------------------------------------------------------
|
|
; Perform the following operations if you intend to make use of
|
|
; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
|
|
; indicating the VFP unit is present (i.e.Cortex-A8). .
|
|
; Some tools will require full double precision floating point support
|
|
; which will become available in Scorpion pass 2
|
|
;----------------------------------------------------------------------
|
|
; allow full access to CP 10 and 11 space for VFP/NEON use
|
|
MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
|
|
ORR r1, r1, #0x00F00000 ; enable full access for p10,11
|
|
MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
|
|
|
|
;make sure the CPACR is complete before continuing
|
|
ISB
|
|
|
|
; Enable VFP itself (certain OSes may want to dynamically set/clear
|
|
; the enable bit based on the application being executed
|
|
MOV r1, #0x40000000
|
|
FMXR FPEXC, r1
|
|
#endif *//* APPSBL_VFP_ENABLE */
|
|
|
|
/* we have no stack, so just tail-call into the SET_SA routine... */
|
|
b SET_SA
|
|
|
|
.ltorg
|