186 lines
6.2 KiB
Plaintext
186 lines
6.2 KiB
Plaintext
Qualcomm GPU
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Qualcomm Adreno GPU
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Required properties:
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- label: A string used as a descriptive name for the device.
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- compatible: Must be "qcom,kgsl-3d0" and "qcom,kgsl-3d"
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- reg: Specifies the register base address and size. The second interval
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specifies the shader memory base address and size.
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- reg-names: Resource names used for the physical address of device registers
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and shader memory. "kgsl_3d0_reg_memory" gives the physical address
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and length of device registers while "kgsl_3d0_shader_memory" gives
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physical address and length of device shader memory.
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- interrupts: Interrupt mapping for GPU IRQ.
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- interrupt-names: String property to describe the name of the interrupt.
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- qcom,id: An integer used as an identification number for the device.
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- qcom,clk-map: A bit map value for clocks controlled by kgsl.
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KGSL_CLK_SRC 0x00000001
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KGSL_CLK_CORE 0x00000002
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KGSL_CLK_IFACE 0x00000004
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KGSL_CLK_MEM 0x00000008
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KGSL_CLK_MEM_IFACE 0x00000010
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KGSL_CLK_AXI 0x00000020
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Bus Scaling Data:
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- qcom,msm-bus,name: String property to describe the name of the 3D graphics processor.
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- qcom,msm-bus,num-cases: This is the the number of Bus Scaling use cases defined in the vectors property.
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- qcom,msm-bus,active-only: A boolean flag indicating if it is active only.
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- qcom,msm-bus,num-paths: This represents the number of paths in each Bus Scaling Usecase.
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- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, format of which is:
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<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 1
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<src dst ab ib>, <src dst ab ib>, // For Bus Scaling Usecase 2
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<.. .. .. ..>, <.. .. .. ..>; // For Bus Scaling Usecase n
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This property is a series of all vectors for all Bus Scaling Usecases.
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Each set of vectors for each usecase describes bandwidth votes for a combination
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of src/dst ports. The driver will set the desired use case based on the selected
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power level and the desired bandwidth vote will be registered for the port pairs.
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Current values of src are:
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0 = MSM_BUS_MASTER_GRAPHICS_3D
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1 = MSM_BUS_MASTER_GRAPHICS_3D_PORT1
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2 = MSM_BUS_MASTER_V_OCMEM_GFX3D
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Current values of dst are:
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0 = MSM_BUS_SLAVE_EBI_CH0
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1 = MSM_BUS_SLAVE_OCMEM
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ab: Represents aggregated bandwidth. This value is 0 for Graphics.
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ib: Represents instantaneous bandwidth. This value has a range <0 8000 MB/s>
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GDSC Oxili Regulators:
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- vddcx-supply: Phandle for vddcx regulator device node.
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- vdd-supply: Phandle for vdd regulator device node.
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IOMMU Data:
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- iommu: Phandle for the KGSL IOMMU device node
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GPU Power levels:
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- qcom,gpu-pwrlevels: Container for the GPU Power Levels (see
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adreno-pwrlevels.txt)
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DCVS Core info
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- qcom,dcvs-core-info Container for the DCVS core info (see
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dcvs-core-info.txt)
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Optional Properties:
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- qcom,initial-powerlevel: This value indicates which qcom,gpu-pwrlevel should be used at start time
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and when coming back out of resume
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- qcom,step-pwrlevel: How many qcom,gpu-pwrlevel should be decremented at once
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- qcom,idle-timeout: This property represents the time in microseconds for idle timeout.
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- qcom,chipid: If it exists this property is used to replace
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the chip identification read from the GPU hardware.
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This is used to override faulty hardware readings.
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- qcom,strtstp-sleepwake: Boolean. Enables use of GPU SLUMBER instead of SLEEP for power savings
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The following properties are optional as collecting data via coresight might
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not be supported for every chipset. The documentation for coresight
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properties can be found in:
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Documentation/devicetree/bindings/coresight/coresight.txt
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- coresight-id Unique integer identifier for the bus.
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- coresight-name Unique descriptive name of the bus.
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- coresight-nr-inports Number of input ports on the bus.
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- coresight-outports List of output port numbers on the bus.
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- coresight-child-list List of phandles pointing to the children of this
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component.
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- coresight-child-ports List of input port numbers of the children.
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Example of A330 GPU in MSM8974:
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/ {
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qcom,kgsl-3d0@fdb00000 {
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label = "kgsl-3d0";
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compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
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reg = <0xfdb00000 0x10000
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0xfdb20000 0x10000>;
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reg-names = "kgsl_3d0_reg_memory", "kgsl_3d0_shader_memory";
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interrupts = <0 33 0>;
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interrupt-names = "kgsl_3d0_irq";
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qcom,id = <0>;
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qcom,chipid = <0x03030000>;
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/* Power Settings */
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qcom,initial-pwrlevel = <1>;
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qcom,idle-timeout = <83>; //<HZ/12>
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qcom,clk-map = <0x00000016>; //KGSL_CLK_CORE | KGSL_CLK_IFACE | KGSL_CLK_MEM_IFACE
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/* Bus Scale Settings */
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qcom,msm-bus,name = "grp3d";
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qcom,msm-bus,num-cases = <6>;
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qcom,msm-bus,num-paths = <2>;
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qcom,msm-bus,vectors-KBps =
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<26 512 0 0>, <89 604 0 0>,
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<26 512 0 2200000>, <89 604 0 3000000>,
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<26 512 0 4000000>, <89 604 0 3000000>,
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<26 512 0 4000000>, <89 604 0 4500000>,
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<26 512 0 6400000>, <89 604 0 4500000>,
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<26 512 0 6400000>, <89 604 0 7600000>;
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/* GDSC oxili regulators */
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vddcx-supply = <&gdsc_oxili_cx>;
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vdd-supply = <&gdsc_oxili_gx>;
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/* IOMMU Data */
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iommu = <&kgsl>;
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qcom,gpu-pwrlevels {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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qcom,gpu-freq = <5000000000>;
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qcom,bus-freq = <3>;
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qcom,io-fraction = <0>;
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};
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};
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qcom,dcvs-core-info {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,dcvs-core-info";
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qcom,core-max-time-us = <100000>;
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qcom,algo-slack-time-us = <39000>;
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qcom,algo-disable-pc-threshold = <86000>;
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qcom,algo-ss-window-size = <1000000>;
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qcom,algo-ss-util-pct = <95>;
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qcom,algo-em-max-util-pct = <97>;
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qcom,algo-ss-no-corr-below-freq = <0>;
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qcom,dcvs-freq@0 {
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reg = <0>;
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qcom,freq = <0>;
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qcom,idle-energy = <0>;
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qcom,active-energy = <333932>;
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};
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qcom,dcvs-freq@1 {
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reg = <1>;
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qcom,freq = <0>;
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qcom,idle-energy = <0>;
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qcom,active-energy = <497532>;
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};
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qcom,dcvs-freq@2 {
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reg = <2>;
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qcom,freq = <0>;
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qcom,idle-energy = <0>;
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qcom,active-energy = <707610>;
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};
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qcom,dcvs-freq@3 {
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reg = <3>;
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qcom,freq = <0>;
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qcom,idle-energy = <0>;
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qcom,active-energy = <844545>;
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};
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};
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};
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};
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