41 lines
1.0 KiB
Plaintext
41 lines
1.0 KiB
Plaintext
* Qcom Performance Monitor Units
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Qcom cores have several PMUs for counting CPU side, L2 and bus side events.
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For the L1CC PMU:
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In most cases the L1 cache controller PMU is a per cpu unit. The irq-is-percpu
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flag becomes a requirement if this is the case.
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Required Properties:
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- compatible : Should be "qcom,krait-pmu"
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- interrupts : 1 combined interrupt or 1 per core. See the devicetree/bindings/gic.txt for more details on this format.
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Optional:
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- qcom,irq-is-percpu: Define this if the IRQ of the PMU is a PPI. This will tell perf to use
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the per_cpu IRQ API for request and free.
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Example:
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arm-pmu {
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compatible = "qcom,krait-pmu";
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qcom,irq-is-percpu;
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interrupts = <1 7 0xf00>;
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};
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For the L2CC PMU:
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If the L2 cache controller PMU is available, its DT bindings should be defined as
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follows.
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Required Properties:
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- compatible: Should be "qcom,l2-pmu"
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- interrupts : 1 combined interrupt.
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Example:
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l2-pmu {
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compatible = "qcom,l2-pmu";
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interrupts = <0 1 0>;
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};
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