413 lines
14 KiB
C
413 lines
14 KiB
C
#ifndef B43_XMIT_H_
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#define B43_XMIT_H_
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#include "main.h"
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#include <net/mac80211.h>
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#define _b43_declare_plcp_hdr(size) \
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struct b43_plcp_hdr##size { \
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union { \
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__le32 data; \
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__u8 raw[size]; \
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} __packed; \
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} __packed
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/* struct b43_plcp_hdr4 */
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_b43_declare_plcp_hdr(4);
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/* struct b43_plcp_hdr6 */
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_b43_declare_plcp_hdr(6);
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#undef _b43_declare_plcp_hdr
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/* TX header for v4 firmware */
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struct b43_txhdr {
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__le32 mac_ctl; /* MAC TX control */
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__le16 mac_frame_ctl; /* Copy of the FrameControl field */
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__le16 tx_fes_time_norm; /* TX FES Time Normal */
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__le16 phy_ctl; /* PHY TX control */
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__le16 phy_ctl1; /* PHY TX control word 1 */
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__le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */
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__le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */
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__le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */
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__u8 phy_rate; /* PHY rate */
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__u8 phy_rate_rts; /* PHY rate for RTS/CTS */
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__u8 extra_ft; /* Extra Frame Types */
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__u8 chan_radio_code; /* Channel Radio Code */
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__u8 iv[16]; /* Encryption IV */
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__u8 tx_receiver[6]; /* TX Frame Receiver address */
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__le16 tx_fes_time_fb; /* TX FES Time Fallback */
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struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */
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__le16 rts_dur_fb; /* RTS fallback duration */
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struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */
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__le16 dur_fb; /* Fallback duration */
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__le16 mimo_modelen; /* MIMO mode length */
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__le16 mimo_ratelen_fb; /* MIMO fallback rate length */
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__le32 timeout; /* Timeout */
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union {
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/* Tested with 598.314, 644.1001 and 666.2 */
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struct {
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__le16 mimo_antenna; /* MIMO antenna select */
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__le16 preload_size; /* Preload size */
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PAD_BYTES(2);
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__le16 cookie; /* TX frame cookie */
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__le16 tx_status; /* TX status */
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__le16 max_n_mpdus;
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__le16 max_a_bytes_mrt;
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__le16 max_a_bytes_fbr;
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__le16 min_m_bytes;
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struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
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__u8 rts_frame[16]; /* The RTS frame (if used) */
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PAD_BYTES(2);
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struct b43_plcp_hdr6 plcp; /* Main PLCP header */
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} format_598 __packed;
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/* Tested with 410.2160, 478.104 and 508.* */
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struct {
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__le16 mimo_antenna; /* MIMO antenna select */
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__le16 preload_size; /* Preload size */
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PAD_BYTES(2);
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__le16 cookie; /* TX frame cookie */
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__le16 tx_status; /* TX status */
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struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
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__u8 rts_frame[16]; /* The RTS frame (if used) */
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PAD_BYTES(2);
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struct b43_plcp_hdr6 plcp; /* Main PLCP header */
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} format_410 __packed;
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/* Tested with 351.126 */
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struct {
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PAD_BYTES(2);
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__le16 cookie; /* TX frame cookie */
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__le16 tx_status; /* TX status */
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struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */
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__u8 rts_frame[16]; /* The RTS frame (if used) */
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PAD_BYTES(2);
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struct b43_plcp_hdr6 plcp; /* Main PLCP header */
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} format_351 __packed;
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} __packed;
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} __packed;
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struct b43_tx_legacy_rate_phy_ctl_entry {
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u8 bitrate;
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u16 coding_rate;
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u16 modulation;
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};
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/* MAC TX control */
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#define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
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#define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
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#define B43_TXH_MAC_KEYIDX_SHIFT 20
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#define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
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#define B43_TXH_MAC_KEYALG_SHIFT 16
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#define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
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#define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
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#define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
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#define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */
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#define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */
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#define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */
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#define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */
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#define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */
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#define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */
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#define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */
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#define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */
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#define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */
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#define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */
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#define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */
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#define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */
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#define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */
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#define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */
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#define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */
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#define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */
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/* Extra Frame Types */
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#define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */
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#define B43_TXH_EFT_FB_CCK 0x00 /* CCK */
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#define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */
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#define B43_TXH_EFT_FB_EWC 0x02 /* EWC */
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#define B43_TXH_EFT_FB_N 0x03 /* N */
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#define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */
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#define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */
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#define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */
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#define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */
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#define B43_TXH_EFT_RTS_N 0x0C /* N */
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#define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */
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#define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */
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#define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */
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#define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */
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#define B43_TXH_EFT_RTSFB_N 0x30 /* N */
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/* PHY TX control word */
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#define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */
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#define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */
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#define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */
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#define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */
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#define B43_TXH_PHY_ENC_N 0x0003 /* N */
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#define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
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#define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */
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#define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */
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#define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */
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#define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */
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#define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */
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#define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */
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#define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */
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#define B43_TXH_PHY_TXPWR_SHIFT 10
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/* PHY TX control word 1 */
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#define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */
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#define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */
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#define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */
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#define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */
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#define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */
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#define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */
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#define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */
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#define B43_TXH_PHY1_MODE 0x0038 /* Mode */
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#define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */
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#define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */
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#define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */
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#define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */
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#define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */
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#define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */
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#define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */
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#define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */
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#define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */
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#define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */
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#define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */
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#define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */
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#define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */
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#define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */
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#define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */
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#define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */
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#define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */
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static inline
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size_t b43_txhdr_size(struct b43_wldev *dev)
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{
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switch (dev->fw.hdr_format) {
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case B43_FW_HDR_598:
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return 112 + sizeof(struct b43_plcp_hdr6);
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case B43_FW_HDR_410:
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return 104 + sizeof(struct b43_plcp_hdr6);
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case B43_FW_HDR_351:
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return 100 + sizeof(struct b43_plcp_hdr6);
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}
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return 0;
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}
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int b43_generate_txhdr(struct b43_wldev *dev,
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u8 * txhdr,
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struct sk_buff *skb_frag,
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struct ieee80211_tx_info *txctl, u16 cookie);
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/* Transmit Status */
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struct b43_txstatus {
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u16 cookie; /* The cookie from the txhdr */
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u16 seq; /* Sequence number */
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u8 phy_stat; /* PHY TX status */
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u8 frame_count; /* Frame transmit count */
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u8 rts_count; /* RTS transmit count */
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u8 supp_reason; /* Suppression reason */
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/* flags */
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u8 pm_indicated; /* PM mode indicated to AP */
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u8 intermediate; /* Intermediate status notification (not final) */
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u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
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u8 acked; /* Wireless ACK received */
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};
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/* txstatus supp_reason values */
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enum {
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B43_TXST_SUPP_NONE, /* Not suppressed */
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B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
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B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
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B43_TXST_SUPP_PREV, /* Previous fragment failed */
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B43_TXST_SUPP_CHAN, /* Channel mismatch */
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B43_TXST_SUPP_LIFE, /* Lifetime expired */
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B43_TXST_SUPP_UNDER, /* Buffer underflow */
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B43_TXST_SUPP_ABNACK, /* Afterburner NACK */
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};
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/* Receive header for v4 firmware. */
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struct b43_rxhdr_fw4 {
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__le16 frame_len; /* Frame length */
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PAD_BYTES(2);
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__le16 phy_status0; /* PHY RX Status 0 */
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union {
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/* RSSI for A/B/G-PHYs */
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struct {
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__u8 jssi; /* PHY RX Status 1: JSSI */
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__u8 sig_qual; /* PHY RX Status 1: Signal Quality */
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} __packed;
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/* RSSI for N-PHYs */
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struct {
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__s8 power0; /* PHY RX Status 1: Power 0 */
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__s8 power1; /* PHY RX Status 1: Power 1 */
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} __packed;
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} __packed;
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union {
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/* HT-PHY */
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struct {
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PAD_BYTES(1);
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__s8 phy_ht_power0;
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} __packed;
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/* RSSI for N-PHYs */
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struct {
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__s8 power2;
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PAD_BYTES(1);
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} __packed;
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__le16 phy_status2; /* PHY RX Status 2 */
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} __packed;
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union {
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/* HT-PHY */
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struct {
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__s8 phy_ht_power1;
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__s8 phy_ht_power2;
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} __packed;
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__le16 phy_status3; /* PHY RX Status 3 */
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} __packed;
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union {
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/* Tested with 598.314, 644.1001 and 666.2 */
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struct {
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__le16 phy_status4; /* PHY RX Status 4 */
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__le16 phy_status5; /* PHY RX Status 5 */
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__le32 mac_status; /* MAC RX status */
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__le16 mac_time;
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__le16 channel;
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} format_598 __packed;
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/* Tested with 351.126, 410.2160, 478.104 and 508.* */
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struct {
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__le32 mac_status; /* MAC RX status */
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__le16 mac_time;
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__le16 channel;
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} format_351 __packed;
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} __packed;
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} __packed;
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/* PHY RX Status 0 */
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#define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
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#define B43_RX_PHYST0_PLCPHCF 0x0200
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#define B43_RX_PHYST0_PLCPFV 0x0100
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#define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */
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#define B43_RX_PHYST0_LCRS 0x0040
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#define B43_RX_PHYST0_ANT 0x0020 /* Antenna */
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#define B43_RX_PHYST0_UNSRATE 0x0010
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#define B43_RX_PHYST0_CLIP 0x000C
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#define B43_RX_PHYST0_CLIP_SHIFT 2
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#define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */
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#define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
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#define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
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#define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
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#define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
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/* PHY RX Status 2 */
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#define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
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#define B43_RX_PHYST2_LNAG_SHIFT 14
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#define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
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#define B43_RX_PHYST2_PNAG_SHIFT 10
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#define B43_RX_PHYST2_FOFF 0x03FF /* F offset */
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/* PHY RX Status 3 */
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#define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
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#define B43_RX_PHYST3_DIGG_SHIFT 11
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#define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */
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/* MAC RX Status */
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#define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */
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#define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */
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#define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */
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#define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */
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#define B43_RX_MAC_AGGTYPE_SHIFT 17
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#define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */
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#define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */
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#define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */
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#define B43_RX_MAC_KEYIDX_SHIFT 5
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#define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */
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#define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */
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#define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
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#define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */
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#define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */
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/* RX channel */
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#define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */
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#define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */
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#define B43_RX_CHAN_ID 0x07F8 /* Channel ID */
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#define B43_RX_CHAN_ID_SHIFT 3
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#define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */
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u8 b43_plcp_get_ratecode_cck(const u8 bitrate);
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u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate);
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void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp,
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const u16 octets, const u8 bitrate);
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void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr);
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void b43_handle_txstatus(struct b43_wldev *dev,
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const struct b43_txstatus *status);
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bool b43_fill_txstatus_report(struct b43_wldev *dev,
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struct ieee80211_tx_info *report,
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const struct b43_txstatus *status);
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void b43_tx_suspend(struct b43_wldev *dev);
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void b43_tx_resume(struct b43_wldev *dev);
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/* Helper functions for converting the key-table index from "firmware-format"
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* to "raw-format" and back. The firmware API changed for this at some revision.
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* We need to account for that here. */
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static inline int b43_new_kidx_api(struct b43_wldev *dev)
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{
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/* FIXME: Not sure the change was at rev 351 */
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return (dev->fw.rev >= 351);
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}
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static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx)
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{
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u8 firmware_kidx;
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if (b43_new_kidx_api(dev)) {
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firmware_kidx = raw_kidx;
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} else {
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if (raw_kidx >= 4) /* Is per STA key? */
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firmware_kidx = raw_kidx - 4;
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else
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firmware_kidx = raw_kidx; /* TX default key */
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}
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return firmware_kidx;
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}
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static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx)
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{
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u8 raw_kidx;
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if (b43_new_kidx_api(dev))
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raw_kidx = firmware_kidx;
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else
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raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */
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|
return raw_kidx;
|
|
}
|
|
|
|
/* struct b43_private_tx_info - TX info private to b43.
|
|
* The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data
|
|
*
|
|
* @bouncebuffer: DMA Bouncebuffer (if used)
|
|
*/
|
|
struct b43_private_tx_info {
|
|
void *bouncebuffer;
|
|
};
|
|
|
|
static inline struct b43_private_tx_info *
|
|
b43_get_priv_tx_info(struct ieee80211_tx_info *info)
|
|
{
|
|
BUILD_BUG_ON(sizeof(struct b43_private_tx_info) >
|
|
sizeof(info->rate_driver_data));
|
|
return (struct b43_private_tx_info *)info->rate_driver_data;
|
|
}
|
|
|
|
#endif /* B43_XMIT_H_ */
|