382 lines
9.9 KiB
C
382 lines
9.9 KiB
C
/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#undef pr_fmt
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/printk.h>
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#include <linux/nl80211.h>
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#include <linux/pci.h>
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#include <linux/pci-aspm.h>
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#include <linux/ath9k_platform.h>
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#include <linux/module.h>
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#include "ath9k.h"
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static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
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{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
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{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
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{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
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{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
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{ PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
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{ PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
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{ PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
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{ 0 }
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};
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/* return bus cachesize in 4B word units */
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static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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u8 u8tmp;
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pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
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*csz = (int)u8tmp;
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/*
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* This check was put in to avoid "unpleasant" consequences if
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* the bootrom has not fully initialized all PCI devices.
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* Sometimes the cache line size register is not set
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*/
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if (*csz == 0)
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*csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
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}
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static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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struct ath9k_platform_data *pdata = sc->dev->platform_data;
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if (pdata) {
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if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
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ath_err(common,
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"%s: eeprom read failed, offset %08x is out of range\n",
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__func__, off);
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}
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*data = pdata->eeprom_data[off];
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} else {
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struct ath_hw *ah = (struct ath_hw *) common->ah;
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common->ops->read(ah, AR5416_EEPROM_OFFSET +
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(off << AR5416_EEPROM_S));
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if (!ath9k_hw_wait(ah,
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AR_EEPROM_STATUS_DATA,
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AR_EEPROM_STATUS_DATA_BUSY |
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AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
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AH_WAIT_TIMEOUT)) {
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return false;
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}
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*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
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AR_EEPROM_STATUS_DATA_VAL);
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}
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return true;
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}
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static void ath_pci_extn_synch_enable(struct ath_common *common)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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struct pci_dev *pdev = to_pci_dev(sc->dev);
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u8 lnkctl;
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pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
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lnkctl |= PCI_EXP_LNKCTL_ES;
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pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
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}
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/* Need to be called after we discover btcoex capabilities */
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static void ath_pci_aspm_init(struct ath_common *common)
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{
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struct ath_softc *sc = (struct ath_softc *) common->priv;
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struct ath_hw *ah = sc->sc_ah;
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struct pci_dev *pdev = to_pci_dev(sc->dev);
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struct pci_dev *parent;
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int pos;
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u8 aspm;
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if (!ah->is_pciexpress)
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return;
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pos = pci_pcie_cap(pdev);
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if (!pos)
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return;
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parent = pdev->bus->self;
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if (!parent)
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return;
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if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
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/* Bluetooth coexistance requires disabling ASPM. */
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pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm);
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aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
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pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
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/*
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* Both upstream and downstream PCIe components should
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* have the same ASPM settings.
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*/
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pos = pci_pcie_cap(parent);
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pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
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aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
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pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
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ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
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return;
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}
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pos = pci_pcie_cap(parent);
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pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
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if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
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ah->aspm_enabled = true;
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/* Initialize PCIe PM and SERDES registers. */
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ath9k_hw_configpcipowersave(ah, false);
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ath_info(common, "ASPM enabled: 0x%x\n", aspm);
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}
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}
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static const struct ath_bus_ops ath_pci_bus_ops = {
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.ath_bus_type = ATH_PCI,
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.read_cachesize = ath_pci_read_cachesize,
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.eeprom_read = ath_pci_eeprom_read,
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.extn_synch_en = ath_pci_extn_synch_enable,
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.aspm_init = ath_pci_aspm_init,
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};
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static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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void __iomem *mem;
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struct ath_softc *sc;
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struct ieee80211_hw *hw;
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u8 csz;
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u32 val;
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int ret = 0;
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char hw_name[64];
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if (pci_enable_device(pdev))
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return -EIO;
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ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret) {
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pr_err("32-bit DMA not available\n");
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goto err_dma;
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}
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ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
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if (ret) {
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pr_err("32-bit DMA consistent DMA enable failed\n");
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goto err_dma;
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}
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/*
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* Cache line size is used to size and align various
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* structures used to communicate with the hardware.
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*/
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
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if (csz == 0) {
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/*
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* Linux 2.4.18 (at least) writes the cache line size
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* register as a 16-bit wide register which is wrong.
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* We must have this setup properly for rx buffer
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* DMA to work so force a reasonable value here if it
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* comes up zero.
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*/
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csz = L1_CACHE_BYTES / sizeof(u32);
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pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
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}
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/*
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* The default setting of latency timer yields poor results,
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* set it to the value used by other systems. It may be worth
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* tweaking this setting more.
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*/
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pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
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pci_set_master(pdev);
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/*
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* Disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state.
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*/
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pci_read_config_dword(pdev, 0x40, &val);
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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ret = pci_request_region(pdev, 0, "ath9k");
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if (ret) {
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dev_err(&pdev->dev, "PCI memory region reserve error\n");
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ret = -ENODEV;
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goto err_region;
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}
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mem = pci_iomap(pdev, 0, 0);
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if (!mem) {
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pr_err("PCI memory map error\n") ;
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ret = -EIO;
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goto err_iomap;
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}
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hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
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if (!hw) {
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dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
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ret = -ENOMEM;
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goto err_alloc_hw;
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}
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SET_IEEE80211_DEV(hw, &pdev->dev);
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pci_set_drvdata(pdev, hw);
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sc = hw->priv;
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sc->hw = hw;
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sc->dev = &pdev->dev;
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sc->mem = mem;
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/* Will be cleared in ath9k_start() */
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set_bit(SC_OP_INVALID, &sc->sc_flags);
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ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
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if (ret) {
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dev_err(&pdev->dev, "request_irq failed\n");
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goto err_irq;
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}
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sc->irq = pdev->irq;
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ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
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if (ret) {
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dev_err(&pdev->dev, "Failed to initialize device\n");
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goto err_init;
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}
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ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
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wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
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hw_name, (unsigned long)mem, pdev->irq);
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return 0;
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err_init:
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free_irq(sc->irq, sc);
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err_irq:
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ieee80211_free_hw(hw);
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err_alloc_hw:
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pci_iounmap(pdev, mem);
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err_iomap:
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pci_release_region(pdev, 0);
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err_region:
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/* Nothing */
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err_dma:
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pci_disable_device(pdev);
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return ret;
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}
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static void ath_pci_remove(struct pci_dev *pdev)
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{
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath_softc *sc = hw->priv;
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void __iomem *mem = sc->mem;
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if (!is_ath9k_unloaded)
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sc->sc_ah->ah_flags |= AH_UNPLUGGED;
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ath9k_deinit_device(sc);
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free_irq(sc->irq, sc);
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ieee80211_free_hw(sc->hw);
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pci_iounmap(pdev, mem);
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pci_disable_device(pdev);
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pci_release_region(pdev, 0);
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}
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#ifdef CONFIG_PM
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static int ath_pci_suspend(struct device *device)
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{
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struct pci_dev *pdev = to_pci_dev(device);
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struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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struct ath_softc *sc = hw->priv;
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/* The device has to be moved to FULLSLEEP forcibly.
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* Otherwise the chip never moved to full sleep,
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* when no interface is up.
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*/
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ath9k_hw_disable(sc->sc_ah);
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ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
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return 0;
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}
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static int ath_pci_resume(struct device *device)
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{
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struct pci_dev *pdev = to_pci_dev(device);
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u32 val;
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/*
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* Suspend/Resume resets the PCI configuration space, so we have to
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* re-disable the RETRY_TIMEOUT register (0x41) to keep
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* PCI Tx retries from interfering with C3 CPU state
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*/
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pci_read_config_dword(pdev, 0x40, &val);
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if ((val & 0x0000ff00) != 0)
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pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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return 0;
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}
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static const struct dev_pm_ops ath9k_pm_ops = {
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.suspend = ath_pci_suspend,
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.resume = ath_pci_resume,
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.freeze = ath_pci_suspend,
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.thaw = ath_pci_resume,
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.poweroff = ath_pci_suspend,
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.restore = ath_pci_resume,
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};
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#define ATH9K_PM_OPS (&ath9k_pm_ops)
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#else /* !CONFIG_PM */
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#define ATH9K_PM_OPS NULL
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#endif /* !CONFIG_PM */
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MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
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static struct pci_driver ath_pci_driver = {
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.name = "ath9k",
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.id_table = ath_pci_id_table,
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.probe = ath_pci_probe,
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.remove = ath_pci_remove,
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.driver.pm = ATH9K_PM_OPS,
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};
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int ath_pci_init(void)
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{
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return pci_register_driver(&ath_pci_driver);
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}
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void ath_pci_exit(void)
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{
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pci_unregister_driver(&ath_pci_driver);
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}
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