553 lines
14 KiB
C
553 lines
14 KiB
C
/*
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* Copyright (c) 2009, Google Inc.
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* All rights reserved.
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* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Google, Inc. nor the names of its contributors
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* may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <dev/keys.h>
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#include <dev/ssbi.h>
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#include <dev/gpio.h>
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#include <lib/ptable.h>
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#include <dev/flash.h>
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#include <smem.h>
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#include <mmc.h>
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#include <platform/timer.h>
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#include <platform/iomap.h>
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#include <platform/gpio.h>
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#include <baseband.h>
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#include <reg.h>
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#include <platform.h>
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#include <gsbi.h>
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#include <platform/scm-io.h>
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#include <platform/machtype.h>
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#include <crypto_hash.h>
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static const uint8_t uart_gsbi_id = GSBI_ID_12;
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/* Setting this variable to different values defines the
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* behavior of CE engine:
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* platform_ce_type = CRYPTO_ENGINE_TYPE_NONE : No CE engine
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* platform_ce_type = CRYPTO_ENGINE_TYPE_SW : Software CE engine
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* platform_ce_type = CRYPTO_ENGINE_TYPE_HW : Hardware CE engine
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* Behavior is determined in the target code.
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*/
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static crypto_engine_type platform_ce_type = CRYPTO_ENGINE_TYPE_SW;
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void keypad_init(void);
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extern void dmb(void);
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int target_is_emmc_boot(void);
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void debug_led_write(char);
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char debug_led_read();
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uint32_t platform_id_read(void);
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void setup_fpga(void);
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int pm8901_reset_pwr_off(int reset);
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int pm8058_reset_pwr_off(int reset);
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int pm8058_rtc0_alarm_irq_disable(void);
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static void target_shutdown_for_rtc_alarm(void);
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void target_init(void)
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{
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target_shutdown_for_rtc_alarm();
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dprintf(INFO, "target_init()\n");
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setup_fpga();
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/* Setting Debug LEDs ON */
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debug_led_write(0xFF);
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#if (!ENABLE_NANDWRITE)
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keys_init();
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keypad_init();
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#endif
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/* Display splash screen if enabled */
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#if DISPLAY_SPLASH_SCREEN
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display_init();
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dprintf(SPEW, "Diplay initialized\n");
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display_image_on_screen();
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#endif
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if (mmc_boot_main(MMC_SLOT, MSM_SDC1_BASE)) {
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dprintf(CRITICAL, "mmc init failed!");
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ASSERT(0);
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}
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}
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unsigned board_machtype(void)
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{
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struct smem_board_info_v5 board_info_v5;
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struct smem_board_info_v6 board_info_v6;
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unsigned int board_info_len = 0;
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unsigned smem_status = 0;
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unsigned format = 0;
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unsigned id = 0;
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unsigned hw_platform = 0;
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unsigned fused_chip = 0;
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unsigned platform_subtype = 0;
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static unsigned mach_id = 0xFFFFFFFF;
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if (mach_id != 0xFFFFFFFF)
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return mach_id;
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/* Detect external msm if this is a "fusion" */
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smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
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&format, sizeof(format), 0);
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if (!smem_status) {
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if (format == 5) {
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board_info_len = sizeof(board_info_v5);
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smem_status =
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smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
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&board_info_v5,
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board_info_len);
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if (!smem_status) {
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fused_chip = board_info_v5.fused_chip;
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id = board_info_v5.board_info_v3.hw_platform;
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}
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} else if (format == 6) {
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board_info_len = sizeof(board_info_v6);
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smem_status =
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smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
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&board_info_v6,
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board_info_len);
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if (!smem_status) {
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fused_chip = board_info_v6.fused_chip;
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id = board_info_v6.board_info_v3.hw_platform;
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platform_subtype =
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board_info_v6.platform_subtype;
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}
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}
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}
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/* Detect SURF v/s FFA v/s Fluid */
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switch (id) {
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case 0x1:
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hw_platform = HW_PLATFORM_SURF;
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break;
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case 0x2:
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hw_platform = HW_PLATFORM_FFA;
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break;
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case 0x3:
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hw_platform = HW_PLATFORM_FLUID;
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break;
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case 0x6:
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hw_platform = HW_PLATFORM_QT;
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break;
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case 0xA:
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hw_platform = HW_PLATFORM_DRAGON;
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break;
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default:
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/* Writing to Debug LED register and reading back to auto detect
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SURF and FFA. If we read back, it is SURF */
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debug_led_write(0xA5);
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if ((debug_led_read() & 0xFF) == 0xA5) {
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debug_led_write(0);
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hw_platform = HW_PLATFORM_SURF;
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} else
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hw_platform = HW_PLATFORM_FFA;
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};
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/* Use platform_subtype or fused_chip information to determine machine id */
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if (format >= 6) {
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switch (platform_subtype) {
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case HW_PLATFORM_SUBTYPE_CSFB:
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case HW_PLATFORM_SUBTYPE_SVLTE2A:
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if (hw_platform == HW_PLATFORM_SURF)
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mach_id = LINUX_MACHTYPE_8660_CHARM_SURF;
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else if (hw_platform == HW_PLATFORM_FFA)
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mach_id = LINUX_MACHTYPE_8660_CHARM_FFA;
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break;
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default:
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if (hw_platform == HW_PLATFORM_SURF)
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mach_id = LINUX_MACHTYPE_8660_SURF;
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else if (hw_platform == HW_PLATFORM_FFA)
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mach_id = LINUX_MACHTYPE_8660_FFA;
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else if (hw_platform == HW_PLATFORM_FLUID)
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mach_id = LINUX_MACHTYPE_8660_FLUID;
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else if (hw_platform == HW_PLATFORM_QT)
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mach_id = LINUX_MACHTYPE_8660_QT;
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else if (hw_platform == HW_PLATFORM_DRAGON)
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mach_id = LINUX_MACHTYPE_8x60_DRAGON;
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}
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} else if (format == 5) {
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switch (fused_chip) {
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case UNKNOWN:
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if (hw_platform == HW_PLATFORM_SURF)
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mach_id = LINUX_MACHTYPE_8660_SURF;
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else if (hw_platform == HW_PLATFORM_FFA)
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mach_id = LINUX_MACHTYPE_8660_FFA;
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else if (hw_platform == HW_PLATFORM_FLUID)
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mach_id = LINUX_MACHTYPE_8660_FLUID;
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else if (hw_platform == HW_PLATFORM_QT)
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mach_id = LINUX_MACHTYPE_8660_QT;
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else if (hw_platform == HW_PLATFORM_DRAGON)
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mach_id = LINUX_MACHTYPE_8x60_DRAGON;
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break;
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case MDM9200:
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case MDM9600:
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if (hw_platform == HW_PLATFORM_SURF)
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mach_id = LINUX_MACHTYPE_8660_CHARM_SURF;
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else if (hw_platform == HW_PLATFORM_FFA)
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mach_id = LINUX_MACHTYPE_8660_CHARM_FFA;
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break;
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default:
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mach_id = LINUX_MACHTYPE_8660_FFA;
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}
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}
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return mach_id;
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}
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void shutdown_device()
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{
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gpio_config_pshold();
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pm8058_reset_pwr_off(0);
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pm8901_reset_pwr_off(0);
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writel(0, MSM_PSHOLD_CTL_SU);
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mdelay(10000);
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dprintf(CRITICAL, "Shutdown failed\n");
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}
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void reboot_device(unsigned reboot_reason)
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{
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/* Reset WDG0 counter */
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writel(1, MSM_WDT0_RST);
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/* Disable WDG0 */
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writel(0, MSM_WDT0_EN);
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/* Set WDG0 bark time */
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writel(0x31F3, MSM_WDT0_BT);
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/* Enable WDG0 */
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writel(3, MSM_WDT0_EN);
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dmb();
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/* Enable WDG output */
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secure_writel(3, MSM_TCSR_BASE + TCSR_WDOG_CFG);
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mdelay(10000);
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dprintf(CRITICAL, "Rebooting failed\n");
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return;
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}
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unsigned check_reboot_mode(void)
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{
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unsigned restart_reason = 0;
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void *restart_reason_addr = (void *)0x2A05F65C;
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/* Read reboot reason and scrub it */
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restart_reason = readl(restart_reason_addr);
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writel(0x00, restart_reason_addr);
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return restart_reason;
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}
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void target_battery_charging_enable(unsigned enable, unsigned disconnect)
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{
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}
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void setup_fpga()
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{
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writel(0x147, GPIO_CFG133_ADDR);
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writel(0x144, GPIO_CFG135_ADDR);
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writel(0x144, GPIO_CFG136_ADDR);
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writel(0x144, GPIO_CFG137_ADDR);
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writel(0x144, GPIO_CFG138_ADDR);
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writel(0x144, GPIO_CFG139_ADDR);
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writel(0x144, GPIO_CFG140_ADDR);
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writel(0x144, GPIO_CFG141_ADDR);
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writel(0x144, GPIO_CFG142_ADDR);
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writel(0x144, GPIO_CFG143_ADDR);
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writel(0x144, GPIO_CFG144_ADDR);
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writel(0x144, GPIO_CFG145_ADDR);
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writel(0x144, GPIO_CFG146_ADDR);
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writel(0x144, GPIO_CFG147_ADDR);
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writel(0x144, GPIO_CFG148_ADDR);
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writel(0x144, GPIO_CFG149_ADDR);
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writel(0x144, GPIO_CFG150_ADDR);
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writel(0x147, GPIO_CFG151_ADDR);
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writel(0x147, GPIO_CFG152_ADDR);
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writel(0x147, GPIO_CFG153_ADDR);
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writel(0x3, GPIO_CFG154_ADDR);
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writel(0x147, GPIO_CFG155_ADDR);
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writel(0x147, GPIO_CFG156_ADDR);
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writel(0x147, GPIO_CFG157_ADDR);
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writel(0x3, GPIO_CFG158_ADDR);
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writel(0x00000B31, EBI2_CHIP_SELECT_CFG0);
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writel(0xA3030020, EBI2_XMEM_CS3_CFG1);
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}
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void debug_led_write(char val)
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{
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writeb(val, SURF_DEBUG_LED_ADDR);
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}
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char debug_led_read()
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{
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return readb(SURF_DEBUG_LED_ADDR);
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}
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unsigned target_baseband()
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{
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struct smem_board_info_v5 board_info_v5;
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struct smem_board_info_v6 board_info_v6;
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unsigned int board_info_len = 0;
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unsigned smem_status = 0;
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unsigned format = 0;
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unsigned baseband = BASEBAND_MSM;
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smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
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&format, sizeof(format), 0);
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if (!smem_status) {
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if (format == 5) {
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board_info_len = sizeof(board_info_v5);
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smem_status =
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smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
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&board_info_v5,
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board_info_len);
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if (!smem_status) {
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/* Check for LTE fused targets or APQ. Default to MSM */
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if (board_info_v5.fused_chip == MDM9200)
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baseband = BASEBAND_CSFB;
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else if (board_info_v5.fused_chip == MDM9600)
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baseband = BASEBAND_SVLTE2A;
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else if (board_info_v5.board_info_v3.msm_id ==
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APQ8060)
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baseband = BASEBAND_APQ;
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else
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baseband = BASEBAND_MSM;
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}
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} else if (format >= 6) {
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board_info_len = sizeof(board_info_v6);
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smem_status =
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smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
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&board_info_v6,
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board_info_len);
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if (!smem_status) {
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/* Check for LTE fused targets or APQ. Default to MSM */
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if (board_info_v6.platform_subtype ==
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HW_PLATFORM_SUBTYPE_CSFB)
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baseband = BASEBAND_CSFB;
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else if (board_info_v6.platform_subtype ==
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HW_PLATFORM_SUBTYPE_SVLTE2A)
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baseband = BASEBAND_SVLTE2A;
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else if (board_info_v6.board_info_v3.msm_id ==
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APQ8060)
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baseband = BASEBAND_APQ;
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else
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baseband = BASEBAND_MSM;
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}
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}
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}
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return baseband;
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}
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crypto_engine_type board_ce_type(void)
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{
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struct smem_board_info_v5 board_info_v5;
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struct smem_board_info_v6 board_info_v6;
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unsigned int board_info_len = 0;
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unsigned smem_status = 0;
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unsigned format = 0;
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smem_status = smem_read_alloc_entry_offset(SMEM_BOARD_INFO_LOCATION,
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&format, sizeof(format), 0);
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if (!smem_status) {
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if (format == 5) {
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board_info_len = sizeof(board_info_v5);
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smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
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&board_info_v5,
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board_info_len);
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if (!smem_status) {
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if ((board_info_v5.board_info_v3.msm_id == APQ8060) ||
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(board_info_v5.board_info_v3.msm_id == MSM8660) ||
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(board_info_v5.board_info_v3.msm_id == MSM8260))
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platform_ce_type = CRYPTO_ENGINE_TYPE_HW;
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}
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} else if (format >= 6) {
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board_info_len = sizeof(board_info_v6);
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smem_status = smem_read_alloc_entry(SMEM_BOARD_INFO_LOCATION,
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&board_info_v6,
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board_info_len);
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if(!smem_status) {
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if ((board_info_v6.board_info_v3.msm_id == APQ8060) ||
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(board_info_v6.board_info_v3.msm_id == MSM8660) ||
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(board_info_v6.board_info_v3.msm_id == MSM8260))
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platform_ce_type = CRYPTO_ENGINE_TYPE_HW;
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}
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}
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}
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return platform_ce_type;
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}
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static unsigned target_check_power_on_reason(void)
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{
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unsigned power_on_status = 0;
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unsigned int status_len = sizeof(power_on_status);
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unsigned smem_status;
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smem_status = smem_read_alloc_entry(SMEM_POWER_ON_STATUS_INFO,
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&power_on_status, status_len);
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if (smem_status) {
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dprintf(CRITICAL,
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"ERROR: unable to read shared memory for power on reason\n");
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}
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dprintf(INFO, "Power on reason %u\n", power_on_status);
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return power_on_status;
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}
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static void target_shutdown_for_rtc_alarm(void)
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{
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if (target_check_power_on_reason() == PWR_ON_EVENT_RTC_ALARM) {
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dprintf(CRITICAL,
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"Power on due to RTC alarm. Going to shutdown!!\n");
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pm8058_rtc0_alarm_irq_disable();
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shutdown_device();
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}
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}
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unsigned target_pause_for_battery_charge(void)
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{
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if (target_check_power_on_reason() == PWR_ON_EVENT_WALL_CHG)
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return 1;
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return 0;
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}
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void target_serialno(unsigned char *buf)
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{
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unsigned int serialno;
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if (target_is_emmc_boot()) {
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serialno = mmc_get_psn();
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snprintf((char *)buf, 13, "%x", serialno);
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}
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}
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void hsusb_gpio_init(void)
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{
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uint32_t func;
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uint32_t pull;
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uint32_t dir;
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uint32_t enable;
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uint32_t drv;
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/* GPIO 131 and 132 need to be configured for connecting to USB HS PHY */
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func = 0;
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enable = 1;
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pull = GPIO_NO_PULL;
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dir = 2;
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drv = GPIO_2MA;
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gpio_tlmm_config(131, func, dir, pull, drv, enable);
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gpio_set(131, dir);
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func = 0;
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enable = 1;
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pull = GPIO_NO_PULL;
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dir = 1;
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drv = GPIO_2MA;
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gpio_tlmm_config(132, func, dir, pull, drv, enable);
|
|
gpio_set(132, dir);
|
|
|
|
return;
|
|
}
|
|
|
|
#define USB_CLK 0x00902910
|
|
#define USB_PHY_CLK 0x00902E20
|
|
#define CLK_RESET_ASSERT 0x1
|
|
#define CLK_RESET_DEASSERT 0x0
|
|
#define CLK_RESET(x,y) writel((y), (x));
|
|
|
|
static int msm_otg_xceiv_reset()
|
|
{
|
|
CLK_RESET(USB_CLK, CLK_RESET_ASSERT);
|
|
CLK_RESET(USB_PHY_CLK, CLK_RESET_ASSERT);
|
|
mdelay(20);
|
|
CLK_RESET(USB_PHY_CLK, CLK_RESET_DEASSERT);
|
|
CLK_RESET(USB_CLK, CLK_RESET_DEASSERT);
|
|
mdelay(20);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void target_ulpi_init(void)
|
|
{
|
|
unsigned int reg;
|
|
|
|
reg = ulpi_read(0x32);
|
|
dprintf(INFO, " Value of ulpi read 0x32 is %08x\n", reg);
|
|
ulpi_write(0x30, 0x32);
|
|
reg = ulpi_read(0x32);
|
|
dprintf(INFO, " Value of ulpi read 0x32 after write is %08x\n", reg);
|
|
|
|
reg = ulpi_read(0x36);
|
|
dprintf(INFO, " Value of ulpi read 0x36 is %08x\n", reg);
|
|
ulpi_write(reg | 0x2, 0x36);
|
|
reg = ulpi_read(0x36);
|
|
dprintf(INFO, " Value of ulpi read 0x36 aafter write is %08x\n", reg);
|
|
}
|
|
|
|
/* Do target specific usb initialization */
|
|
void target_usb_init(void)
|
|
{
|
|
hsusb_gpio_init();
|
|
|
|
msm_otg_xceiv_reset();
|
|
|
|
target_ulpi_init();
|
|
}
|
|
|
|
void target_usb_stop(void)
|
|
{
|
|
int val;
|
|
/* Voting down PLL8 */
|
|
val = readl(0x009034C0);
|
|
val &= ~(1 << 8);
|
|
writel(val, 0x009034C0);
|
|
}
|
|
|
|
uint8_t target_uart_gsbi(void)
|
|
{
|
|
return uart_gsbi_id;
|
|
}
|
|
|
|
int emmc_recovery_init(void)
|
|
{
|
|
int rc;
|
|
rc = _emmc_recovery_init();
|
|
return rc;
|
|
}
|