919 lines
22 KiB
Raku
919 lines
22 KiB
Raku
#!/usr/bin/env perl
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# ====================================================================
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# Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
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# project. The module is, however, dual licensed under OpenSSL and
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# CRYPTOGAMS licenses depending on where you obtain it. For further
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# details see http://www.openssl.org/~appro/cryptogams/.
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# ====================================================================
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# December 2007
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# The reason for undertaken effort is basically following. Even though
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# Power 6 CPU operates at incredible 4.7GHz clock frequency, its PKI
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# performance was observed to be less than impressive, essentially as
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# fast as 1.8GHz PPC970, or 2.6 times(!) slower than one would hope.
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# Well, it's not surprising that IBM had to make some sacrifices to
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# boost the clock frequency that much, but no overall improvement?
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# Having observed how much difference did switching to FPU make on
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# UltraSPARC, playing same stunt on Power 6 appeared appropriate...
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# Unfortunately the resulting performance improvement is not as
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# impressive, ~30%, and in absolute terms is still very far from what
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# one would expect from 4.7GHz CPU. There is a chance that I'm doing
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# something wrong, but in the lack of assembler level micro-profiling
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# data or at least decent platform guide I can't tell... Or better
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# results might be achieved with VMX... Anyway, this module provides
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# *worse* performance on other PowerPC implementations, ~40-15% slower
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# on PPC970 depending on key length and ~40% slower on Power 5 for all
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# key lengths. As it's obviously inappropriate as "best all-round"
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# alternative, it has to be complemented with run-time CPU family
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# detection. Oh! It should also be noted that unlike other PowerPC
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# implementation IALU ppc-mont.pl module performs *suboptimaly* on
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# >=1024-bit key lengths on Power 6. It should also be noted that
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# *everything* said so far applies to 64-bit builds! As far as 32-bit
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# application executed on 64-bit CPU goes, this module is likely to
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# become preferred choice, because it's easy to adapt it for such
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# case and *is* faster than 32-bit ppc-mont.pl on *all* processors.
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# February 2008
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# Micro-profiling assisted optimization results in ~15% improvement
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# over original ppc64-mont.pl version, or overall ~50% improvement
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# over ppc.pl module on Power 6. If compared to ppc-mont.pl on same
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# Power 6 CPU, this module is 5-150% faster depending on key length,
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# [hereafter] more for longer keys. But if compared to ppc-mont.pl
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# on 1.8GHz PPC970, it's only 5-55% faster. Still far from impressive
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# in absolute terms, but it's apparently the way Power 6 is...
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$flavour = shift;
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if ($flavour =~ /32/) {
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$SIZE_T=4;
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$RZONE= 224;
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$FRAME= $SIZE_T*12+8*12;
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$fname= "bn_mul_mont_ppc64";
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$STUX= "stwux"; # store indexed and update
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$PUSH= "stw";
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$POP= "lwz";
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die "not implemented yet";
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} elsif ($flavour =~ /64/) {
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$SIZE_T=8;
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$RZONE= 288;
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$FRAME= $SIZE_T*12+8*12;
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$fname= "bn_mul_mont";
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# same as above, but 64-bit mnemonics...
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$STUX= "stdux"; # store indexed and update
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$PUSH= "std";
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$POP= "ld";
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} else { die "nonsense $flavour"; }
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
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( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
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( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
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die "can't locate ppc-xlate.pl";
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open STDOUT,"| $^X $xlate $flavour ".shift || die "can't call $xlate: $!";
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$FRAME=($FRAME+63)&~63;
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$TRANSFER=16*8;
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$carry="r0";
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$sp="r1";
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$toc="r2";
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$rp="r3"; $ovf="r3";
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$ap="r4";
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$bp="r5";
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$np="r6";
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$n0="r7";
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$num="r8";
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$rp="r9"; # $rp is reassigned
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$tp="r10";
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$j="r11";
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$i="r12";
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# non-volatile registers
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$nap_d="r14"; # interleaved ap and np in double format
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$a0="r15"; # ap[0]
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$t0="r16"; # temporary registers
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$t1="r17";
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$t2="r18";
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$t3="r19";
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$t4="r20";
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$t5="r21";
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$t6="r22";
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$t7="r23";
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# PPC offers enough register bank capacity to unroll inner loops twice
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#
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# ..A3A2A1A0
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# dcba
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# -----------
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# A0a
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# A0b
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# A0c
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# A0d
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# A1a
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# A1b
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# A1c
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# A1d
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# A2a
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# A2b
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# A2c
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# A2d
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# A3a
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# A3b
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# A3c
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# A3d
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# ..a
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# ..b
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#
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$ba="f0"; $bb="f1"; $bc="f2"; $bd="f3";
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$na="f4"; $nb="f5"; $nc="f6"; $nd="f7";
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$dota="f8"; $dotb="f9";
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$A0="f10"; $A1="f11"; $A2="f12"; $A3="f13";
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$N0="f14"; $N1="f15"; $N2="f16"; $N3="f17";
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$T0a="f18"; $T0b="f19";
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$T1a="f20"; $T1b="f21";
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$T2a="f22"; $T2b="f23";
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$T3a="f24"; $T3b="f25";
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# sp----------->+-------------------------------+
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# | saved sp |
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# +-------------------------------+
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# | |
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# +-------------------------------+
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# | 10 saved gpr, r14-r23 |
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# . .
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# . .
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# +12*size_t +-------------------------------+
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# | 12 saved fpr, f14-f25 |
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# . .
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# . .
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# +12*8 +-------------------------------+
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# | padding to 64 byte boundary |
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# . .
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# +X +-------------------------------+
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# | 16 gpr<->fpr transfer zone |
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# . .
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# . .
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# +16*8 +-------------------------------+
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# | __int64 tmp[-1] |
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# +-------------------------------+
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# | __int64 tmp[num] |
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# . .
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# . .
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# . .
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# +(num+1)*8 +-------------------------------+
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# | padding to 64 byte boundary |
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# . .
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# +X +-------------------------------+
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# | double nap_d[4*num] |
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# . .
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# . .
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# . .
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# +-------------------------------+
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$code=<<___;
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.machine "any"
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.text
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.globl .$fname
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.align 5
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.$fname:
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cmpwi $num,4
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mr $rp,r3 ; $rp is reassigned
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li r3,0 ; possible "not handled" return code
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bltlr-
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andi. r0,$num,1 ; $num has to be even
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bnelr-
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slwi $num,$num,3 ; num*=8
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li $i,-4096
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slwi $tp,$num,2 ; place for {an}p_{lh}[num], i.e. 4*num
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add $tp,$tp,$num ; place for tp[num+1]
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addi $tp,$tp,`$FRAME+$TRANSFER+8+64+$RZONE`
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subf $tp,$tp,$sp ; $sp-$tp
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and $tp,$tp,$i ; minimize TLB usage
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subf $tp,$sp,$tp ; $tp-$sp
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$STUX $sp,$sp,$tp ; alloca
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$PUSH r14,`2*$SIZE_T`($sp)
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$PUSH r15,`3*$SIZE_T`($sp)
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$PUSH r16,`4*$SIZE_T`($sp)
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$PUSH r17,`5*$SIZE_T`($sp)
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$PUSH r18,`6*$SIZE_T`($sp)
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$PUSH r19,`7*$SIZE_T`($sp)
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$PUSH r20,`8*$SIZE_T`($sp)
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$PUSH r21,`9*$SIZE_T`($sp)
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$PUSH r22,`10*$SIZE_T`($sp)
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$PUSH r23,`11*$SIZE_T`($sp)
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stfd f14,`12*$SIZE_T+0`($sp)
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stfd f15,`12*$SIZE_T+8`($sp)
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stfd f16,`12*$SIZE_T+16`($sp)
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stfd f17,`12*$SIZE_T+24`($sp)
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stfd f18,`12*$SIZE_T+32`($sp)
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stfd f19,`12*$SIZE_T+40`($sp)
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stfd f20,`12*$SIZE_T+48`($sp)
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stfd f21,`12*$SIZE_T+56`($sp)
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stfd f22,`12*$SIZE_T+64`($sp)
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stfd f23,`12*$SIZE_T+72`($sp)
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stfd f24,`12*$SIZE_T+80`($sp)
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stfd f25,`12*$SIZE_T+88`($sp)
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ld $a0,0($ap) ; pull ap[0] value
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ld $n0,0($n0) ; pull n0[0] value
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ld $t3,0($bp) ; bp[0]
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addi $tp,$sp,`$FRAME+$TRANSFER+8+64`
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li $i,-64
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add $nap_d,$tp,$num
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and $nap_d,$nap_d,$i ; align to 64 bytes
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mulld $t7,$a0,$t3 ; ap[0]*bp[0]
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; nap_d is off by 1, because it's used with stfdu/lfdu
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addi $nap_d,$nap_d,-8
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srwi $j,$num,`3+1` ; counter register, num/2
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mulld $t7,$t7,$n0 ; tp[0]*n0
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addi $j,$j,-1
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addi $tp,$sp,`$FRAME+$TRANSFER-8`
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li $carry,0
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mtctr $j
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; transfer bp[0] to FPU as 4x16-bit values
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extrdi $t0,$t3,16,48
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extrdi $t1,$t3,16,32
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extrdi $t2,$t3,16,16
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extrdi $t3,$t3,16,0
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std $t0,`$FRAME+0`($sp)
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std $t1,`$FRAME+8`($sp)
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std $t2,`$FRAME+16`($sp)
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std $t3,`$FRAME+24`($sp)
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; transfer (ap[0]*bp[0])*n0 to FPU as 4x16-bit values
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extrdi $t4,$t7,16,48
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extrdi $t5,$t7,16,32
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extrdi $t6,$t7,16,16
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extrdi $t7,$t7,16,0
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std $t4,`$FRAME+32`($sp)
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std $t5,`$FRAME+40`($sp)
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std $t6,`$FRAME+48`($sp)
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std $t7,`$FRAME+56`($sp)
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lwz $t0,4($ap) ; load a[j] as 32-bit word pair
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lwz $t1,0($ap)
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lwz $t2,12($ap) ; load a[j+1] as 32-bit word pair
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lwz $t3,8($ap)
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lwz $t4,4($np) ; load n[j] as 32-bit word pair
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lwz $t5,0($np)
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lwz $t6,12($np) ; load n[j+1] as 32-bit word pair
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lwz $t7,8($np)
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lfd $ba,`$FRAME+0`($sp)
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lfd $bb,`$FRAME+8`($sp)
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lfd $bc,`$FRAME+16`($sp)
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lfd $bd,`$FRAME+24`($sp)
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lfd $na,`$FRAME+32`($sp)
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lfd $nb,`$FRAME+40`($sp)
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lfd $nc,`$FRAME+48`($sp)
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lfd $nd,`$FRAME+56`($sp)
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std $t0,`$FRAME+64`($sp)
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std $t1,`$FRAME+72`($sp)
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std $t2,`$FRAME+80`($sp)
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std $t3,`$FRAME+88`($sp)
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std $t4,`$FRAME+96`($sp)
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std $t5,`$FRAME+104`($sp)
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std $t6,`$FRAME+112`($sp)
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std $t7,`$FRAME+120`($sp)
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fcfid $ba,$ba
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fcfid $bb,$bb
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fcfid $bc,$bc
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fcfid $bd,$bd
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fcfid $na,$na
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fcfid $nb,$nb
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fcfid $nc,$nc
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fcfid $nd,$nd
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lfd $A0,`$FRAME+64`($sp)
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lfd $A1,`$FRAME+72`($sp)
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lfd $A2,`$FRAME+80`($sp)
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lfd $A3,`$FRAME+88`($sp)
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lfd $N0,`$FRAME+96`($sp)
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lfd $N1,`$FRAME+104`($sp)
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lfd $N2,`$FRAME+112`($sp)
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lfd $N3,`$FRAME+120`($sp)
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fcfid $A0,$A0
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fcfid $A1,$A1
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fcfid $A2,$A2
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fcfid $A3,$A3
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fcfid $N0,$N0
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fcfid $N1,$N1
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fcfid $N2,$N2
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fcfid $N3,$N3
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addi $ap,$ap,16
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addi $np,$np,16
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fmul $T1a,$A1,$ba
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fmul $T1b,$A1,$bb
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stfd $A0,8($nap_d) ; save a[j] in double format
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stfd $A1,16($nap_d)
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fmul $T2a,$A2,$ba
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fmul $T2b,$A2,$bb
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stfd $A2,24($nap_d) ; save a[j+1] in double format
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stfd $A3,32($nap_d)
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fmul $T3a,$A3,$ba
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fmul $T3b,$A3,$bb
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stfd $N0,40($nap_d) ; save n[j] in double format
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stfd $N1,48($nap_d)
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fmul $T0a,$A0,$ba
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fmul $T0b,$A0,$bb
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stfd $N2,56($nap_d) ; save n[j+1] in double format
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stfdu $N3,64($nap_d)
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fmadd $T1a,$A0,$bc,$T1a
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fmadd $T1b,$A0,$bd,$T1b
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fmadd $T2a,$A1,$bc,$T2a
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fmadd $T2b,$A1,$bd,$T2b
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fmadd $T3a,$A2,$bc,$T3a
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fmadd $T3b,$A2,$bd,$T3b
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fmul $dota,$A3,$bc
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fmul $dotb,$A3,$bd
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fmadd $T1a,$N1,$na,$T1a
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fmadd $T1b,$N1,$nb,$T1b
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fmadd $T2a,$N2,$na,$T2a
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fmadd $T2b,$N2,$nb,$T2b
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fmadd $T3a,$N3,$na,$T3a
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fmadd $T3b,$N3,$nb,$T3b
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fmadd $T0a,$N0,$na,$T0a
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fmadd $T0b,$N0,$nb,$T0b
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fmadd $T1a,$N0,$nc,$T1a
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fmadd $T1b,$N0,$nd,$T1b
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fmadd $T2a,$N1,$nc,$T2a
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fmadd $T2b,$N1,$nd,$T2b
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fmadd $T3a,$N2,$nc,$T3a
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fmadd $T3b,$N2,$nd,$T3b
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fmadd $dota,$N3,$nc,$dota
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fmadd $dotb,$N3,$nd,$dotb
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|
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fctid $T0a,$T0a
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fctid $T0b,$T0b
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fctid $T1a,$T1a
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fctid $T1b,$T1b
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||
fctid $T2a,$T2a
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fctid $T2b,$T2b
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fctid $T3a,$T3a
|
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fctid $T3b,$T3b
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|
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stfd $T0a,`$FRAME+0`($sp)
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stfd $T0b,`$FRAME+8`($sp)
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stfd $T1a,`$FRAME+16`($sp)
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||
stfd $T1b,`$FRAME+24`($sp)
|
||
stfd $T2a,`$FRAME+32`($sp)
|
||
stfd $T2b,`$FRAME+40`($sp)
|
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stfd $T3a,`$FRAME+48`($sp)
|
||
stfd $T3b,`$FRAME+56`($sp)
|
||
|
||
.align 5
|
||
L1st:
|
||
lwz $t0,4($ap) ; load a[j] as 32-bit word pair
|
||
lwz $t1,0($ap)
|
||
lwz $t2,12($ap) ; load a[j+1] as 32-bit word pair
|
||
lwz $t3,8($ap)
|
||
lwz $t4,4($np) ; load n[j] as 32-bit word pair
|
||
lwz $t5,0($np)
|
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lwz $t6,12($np) ; load n[j+1] as 32-bit word pair
|
||
lwz $t7,8($np)
|
||
std $t0,`$FRAME+64`($sp)
|
||
std $t1,`$FRAME+72`($sp)
|
||
std $t2,`$FRAME+80`($sp)
|
||
std $t3,`$FRAME+88`($sp)
|
||
std $t4,`$FRAME+96`($sp)
|
||
std $t5,`$FRAME+104`($sp)
|
||
std $t6,`$FRAME+112`($sp)
|
||
std $t7,`$FRAME+120`($sp)
|
||
ld $t0,`$FRAME+0`($sp)
|
||
ld $t1,`$FRAME+8`($sp)
|
||
ld $t2,`$FRAME+16`($sp)
|
||
ld $t3,`$FRAME+24`($sp)
|
||
ld $t4,`$FRAME+32`($sp)
|
||
ld $t5,`$FRAME+40`($sp)
|
||
ld $t6,`$FRAME+48`($sp)
|
||
ld $t7,`$FRAME+56`($sp)
|
||
lfd $A0,`$FRAME+64`($sp)
|
||
lfd $A1,`$FRAME+72`($sp)
|
||
lfd $A2,`$FRAME+80`($sp)
|
||
lfd $A3,`$FRAME+88`($sp)
|
||
lfd $N0,`$FRAME+96`($sp)
|
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lfd $N1,`$FRAME+104`($sp)
|
||
lfd $N2,`$FRAME+112`($sp)
|
||
lfd $N3,`$FRAME+120`($sp)
|
||
fcfid $A0,$A0
|
||
fcfid $A1,$A1
|
||
fcfid $A2,$A2
|
||
fcfid $A3,$A3
|
||
fcfid $N0,$N0
|
||
fcfid $N1,$N1
|
||
fcfid $N2,$N2
|
||
fcfid $N3,$N3
|
||
addi $ap,$ap,16
|
||
addi $np,$np,16
|
||
|
||
fmul $T1a,$A1,$ba
|
||
fmul $T1b,$A1,$bb
|
||
fmul $T2a,$A2,$ba
|
||
fmul $T2b,$A2,$bb
|
||
stfd $A0,8($nap_d) ; save a[j] in double format
|
||
stfd $A1,16($nap_d)
|
||
fmul $T3a,$A3,$ba
|
||
fmul $T3b,$A3,$bb
|
||
fmadd $T0a,$A0,$ba,$dota
|
||
fmadd $T0b,$A0,$bb,$dotb
|
||
stfd $A2,24($nap_d) ; save a[j+1] in double format
|
||
stfd $A3,32($nap_d)
|
||
|
||
fmadd $T1a,$A0,$bc,$T1a
|
||
fmadd $T1b,$A0,$bd,$T1b
|
||
fmadd $T2a,$A1,$bc,$T2a
|
||
fmadd $T2b,$A1,$bd,$T2b
|
||
stfd $N0,40($nap_d) ; save n[j] in double format
|
||
stfd $N1,48($nap_d)
|
||
fmadd $T3a,$A2,$bc,$T3a
|
||
fmadd $T3b,$A2,$bd,$T3b
|
||
add $t0,$t0,$carry ; can not overflow
|
||
fmul $dota,$A3,$bc
|
||
fmul $dotb,$A3,$bd
|
||
stfd $N2,56($nap_d) ; save n[j+1] in double format
|
||
stfdu $N3,64($nap_d)
|
||
srdi $carry,$t0,16
|
||
add $t1,$t1,$carry
|
||
srdi $carry,$t1,16
|
||
|
||
fmadd $T1a,$N1,$na,$T1a
|
||
fmadd $T1b,$N1,$nb,$T1b
|
||
insrdi $t0,$t1,16,32
|
||
fmadd $T2a,$N2,$na,$T2a
|
||
fmadd $T2b,$N2,$nb,$T2b
|
||
add $t2,$t2,$carry
|
||
fmadd $T3a,$N3,$na,$T3a
|
||
fmadd $T3b,$N3,$nb,$T3b
|
||
srdi $carry,$t2,16
|
||
fmadd $T0a,$N0,$na,$T0a
|
||
fmadd $T0b,$N0,$nb,$T0b
|
||
insrdi $t0,$t2,16,16
|
||
add $t3,$t3,$carry
|
||
srdi $carry,$t3,16
|
||
|
||
fmadd $T1a,$N0,$nc,$T1a
|
||
fmadd $T1b,$N0,$nd,$T1b
|
||
insrdi $t0,$t3,16,0 ; 0..63 bits
|
||
fmadd $T2a,$N1,$nc,$T2a
|
||
fmadd $T2b,$N1,$nd,$T2b
|
||
add $t4,$t4,$carry
|
||
fmadd $T3a,$N2,$nc,$T3a
|
||
fmadd $T3b,$N2,$nd,$T3b
|
||
srdi $carry,$t4,16
|
||
fmadd $dota,$N3,$nc,$dota
|
||
fmadd $dotb,$N3,$nd,$dotb
|
||
add $t5,$t5,$carry
|
||
srdi $carry,$t5,16
|
||
insrdi $t4,$t5,16,32
|
||
|
||
fctid $T0a,$T0a
|
||
fctid $T0b,$T0b
|
||
add $t6,$t6,$carry
|
||
fctid $T1a,$T1a
|
||
fctid $T1b,$T1b
|
||
srdi $carry,$t6,16
|
||
fctid $T2a,$T2a
|
||
fctid $T2b,$T2b
|
||
insrdi $t4,$t6,16,16
|
||
fctid $T3a,$T3a
|
||
fctid $T3b,$T3b
|
||
add $t7,$t7,$carry
|
||
insrdi $t4,$t7,16,0 ; 64..127 bits
|
||
srdi $carry,$t7,16 ; upper 33 bits
|
||
|
||
stfd $T0a,`$FRAME+0`($sp)
|
||
stfd $T0b,`$FRAME+8`($sp)
|
||
stfd $T1a,`$FRAME+16`($sp)
|
||
stfd $T1b,`$FRAME+24`($sp)
|
||
stfd $T2a,`$FRAME+32`($sp)
|
||
stfd $T2b,`$FRAME+40`($sp)
|
||
stfd $T3a,`$FRAME+48`($sp)
|
||
stfd $T3b,`$FRAME+56`($sp)
|
||
std $t0,8($tp) ; tp[j-1]
|
||
stdu $t4,16($tp) ; tp[j]
|
||
bdnz- L1st
|
||
|
||
fctid $dota,$dota
|
||
fctid $dotb,$dotb
|
||
|
||
ld $t0,`$FRAME+0`($sp)
|
||
ld $t1,`$FRAME+8`($sp)
|
||
ld $t2,`$FRAME+16`($sp)
|
||
ld $t3,`$FRAME+24`($sp)
|
||
ld $t4,`$FRAME+32`($sp)
|
||
ld $t5,`$FRAME+40`($sp)
|
||
ld $t6,`$FRAME+48`($sp)
|
||
ld $t7,`$FRAME+56`($sp)
|
||
stfd $dota,`$FRAME+64`($sp)
|
||
stfd $dotb,`$FRAME+72`($sp)
|
||
|
||
add $t0,$t0,$carry ; can not overflow
|
||
srdi $carry,$t0,16
|
||
add $t1,$t1,$carry
|
||
srdi $carry,$t1,16
|
||
insrdi $t0,$t1,16,32
|
||
add $t2,$t2,$carry
|
||
srdi $carry,$t2,16
|
||
insrdi $t0,$t2,16,16
|
||
add $t3,$t3,$carry
|
||
srdi $carry,$t3,16
|
||
insrdi $t0,$t3,16,0 ; 0..63 bits
|
||
add $t4,$t4,$carry
|
||
srdi $carry,$t4,16
|
||
add $t5,$t5,$carry
|
||
srdi $carry,$t5,16
|
||
insrdi $t4,$t5,16,32
|
||
add $t6,$t6,$carry
|
||
srdi $carry,$t6,16
|
||
insrdi $t4,$t6,16,16
|
||
add $t7,$t7,$carry
|
||
insrdi $t4,$t7,16,0 ; 64..127 bits
|
||
srdi $carry,$t7,16 ; upper 33 bits
|
||
ld $t6,`$FRAME+64`($sp)
|
||
ld $t7,`$FRAME+72`($sp)
|
||
|
||
std $t0,8($tp) ; tp[j-1]
|
||
stdu $t4,16($tp) ; tp[j]
|
||
|
||
add $t6,$t6,$carry ; can not overflow
|
||
srdi $carry,$t6,16
|
||
add $t7,$t7,$carry
|
||
insrdi $t6,$t7,48,0
|
||
srdi $ovf,$t7,48
|
||
std $t6,8($tp) ; tp[num-1]
|
||
|
||
slwi $t7,$num,2
|
||
subf $nap_d,$t7,$nap_d ; rewind pointer
|
||
|
||
li $i,8 ; i=1
|
||
.align 5
|
||
Louter:
|
||
ldx $t3,$bp,$i ; bp[i]
|
||
ld $t6,`$FRAME+$TRANSFER+8`($sp) ; tp[0]
|
||
mulld $t7,$a0,$t3 ; ap[0]*bp[i]
|
||
|
||
addi $tp,$sp,`$FRAME+$TRANSFER`
|
||
add $t7,$t7,$t6 ; ap[0]*bp[i]+tp[0]
|
||
li $carry,0
|
||
mulld $t7,$t7,$n0 ; tp[0]*n0
|
||
mtctr $j
|
||
|
||
; transfer bp[i] to FPU as 4x16-bit values
|
||
extrdi $t0,$t3,16,48
|
||
extrdi $t1,$t3,16,32
|
||
extrdi $t2,$t3,16,16
|
||
extrdi $t3,$t3,16,0
|
||
std $t0,`$FRAME+0`($sp)
|
||
std $t1,`$FRAME+8`($sp)
|
||
std $t2,`$FRAME+16`($sp)
|
||
std $t3,`$FRAME+24`($sp)
|
||
; transfer (ap[0]*bp[i]+tp[0])*n0 to FPU as 4x16-bit values
|
||
extrdi $t4,$t7,16,48
|
||
extrdi $t5,$t7,16,32
|
||
extrdi $t6,$t7,16,16
|
||
extrdi $t7,$t7,16,0
|
||
std $t4,`$FRAME+32`($sp)
|
||
std $t5,`$FRAME+40`($sp)
|
||
std $t6,`$FRAME+48`($sp)
|
||
std $t7,`$FRAME+56`($sp)
|
||
|
||
lfd $A0,8($nap_d) ; load a[j] in double format
|
||
lfd $A1,16($nap_d)
|
||
lfd $A2,24($nap_d) ; load a[j+1] in double format
|
||
lfd $A3,32($nap_d)
|
||
lfd $N0,40($nap_d) ; load n[j] in double format
|
||
lfd $N1,48($nap_d)
|
||
lfd $N2,56($nap_d) ; load n[j+1] in double format
|
||
lfdu $N3,64($nap_d)
|
||
|
||
lfd $ba,`$FRAME+0`($sp)
|
||
lfd $bb,`$FRAME+8`($sp)
|
||
lfd $bc,`$FRAME+16`($sp)
|
||
lfd $bd,`$FRAME+24`($sp)
|
||
lfd $na,`$FRAME+32`($sp)
|
||
lfd $nb,`$FRAME+40`($sp)
|
||
lfd $nc,`$FRAME+48`($sp)
|
||
lfd $nd,`$FRAME+56`($sp)
|
||
|
||
fcfid $ba,$ba
|
||
fcfid $bb,$bb
|
||
fcfid $bc,$bc
|
||
fcfid $bd,$bd
|
||
fcfid $na,$na
|
||
fcfid $nb,$nb
|
||
fcfid $nc,$nc
|
||
fcfid $nd,$nd
|
||
|
||
fmul $T1a,$A1,$ba
|
||
fmul $T1b,$A1,$bb
|
||
fmul $T2a,$A2,$ba
|
||
fmul $T2b,$A2,$bb
|
||
fmul $T3a,$A3,$ba
|
||
fmul $T3b,$A3,$bb
|
||
fmul $T0a,$A0,$ba
|
||
fmul $T0b,$A0,$bb
|
||
|
||
fmadd $T1a,$A0,$bc,$T1a
|
||
fmadd $T1b,$A0,$bd,$T1b
|
||
fmadd $T2a,$A1,$bc,$T2a
|
||
fmadd $T2b,$A1,$bd,$T2b
|
||
fmadd $T3a,$A2,$bc,$T3a
|
||
fmadd $T3b,$A2,$bd,$T3b
|
||
fmul $dota,$A3,$bc
|
||
fmul $dotb,$A3,$bd
|
||
|
||
fmadd $T1a,$N1,$na,$T1a
|
||
fmadd $T1b,$N1,$nb,$T1b
|
||
lfd $A0,8($nap_d) ; load a[j] in double format
|
||
lfd $A1,16($nap_d)
|
||
fmadd $T2a,$N2,$na,$T2a
|
||
fmadd $T2b,$N2,$nb,$T2b
|
||
lfd $A2,24($nap_d) ; load a[j+1] in double format
|
||
lfd $A3,32($nap_d)
|
||
fmadd $T3a,$N3,$na,$T3a
|
||
fmadd $T3b,$N3,$nb,$T3b
|
||
fmadd $T0a,$N0,$na,$T0a
|
||
fmadd $T0b,$N0,$nb,$T0b
|
||
|
||
fmadd $T1a,$N0,$nc,$T1a
|
||
fmadd $T1b,$N0,$nd,$T1b
|
||
fmadd $T2a,$N1,$nc,$T2a
|
||
fmadd $T2b,$N1,$nd,$T2b
|
||
fmadd $T3a,$N2,$nc,$T3a
|
||
fmadd $T3b,$N2,$nd,$T3b
|
||
fmadd $dota,$N3,$nc,$dota
|
||
fmadd $dotb,$N3,$nd,$dotb
|
||
|
||
fctid $T0a,$T0a
|
||
fctid $T0b,$T0b
|
||
fctid $T1a,$T1a
|
||
fctid $T1b,$T1b
|
||
fctid $T2a,$T2a
|
||
fctid $T2b,$T2b
|
||
fctid $T3a,$T3a
|
||
fctid $T3b,$T3b
|
||
|
||
stfd $T0a,`$FRAME+0`($sp)
|
||
stfd $T0b,`$FRAME+8`($sp)
|
||
stfd $T1a,`$FRAME+16`($sp)
|
||
stfd $T1b,`$FRAME+24`($sp)
|
||
stfd $T2a,`$FRAME+32`($sp)
|
||
stfd $T2b,`$FRAME+40`($sp)
|
||
stfd $T3a,`$FRAME+48`($sp)
|
||
stfd $T3b,`$FRAME+56`($sp)
|
||
|
||
.align 5
|
||
Linner:
|
||
fmul $T1a,$A1,$ba
|
||
fmul $T1b,$A1,$bb
|
||
fmul $T2a,$A2,$ba
|
||
fmul $T2b,$A2,$bb
|
||
lfd $N0,40($nap_d) ; load n[j] in double format
|
||
lfd $N1,48($nap_d)
|
||
fmul $T3a,$A3,$ba
|
||
fmul $T3b,$A3,$bb
|
||
fmadd $T0a,$A0,$ba,$dota
|
||
fmadd $T0b,$A0,$bb,$dotb
|
||
lfd $N2,56($nap_d) ; load n[j+1] in double format
|
||
lfdu $N3,64($nap_d)
|
||
|
||
fmadd $T1a,$A0,$bc,$T1a
|
||
fmadd $T1b,$A0,$bd,$T1b
|
||
fmadd $T2a,$A1,$bc,$T2a
|
||
fmadd $T2b,$A1,$bd,$T2b
|
||
lfd $A0,8($nap_d) ; load a[j] in double format
|
||
lfd $A1,16($nap_d)
|
||
fmadd $T3a,$A2,$bc,$T3a
|
||
fmadd $T3b,$A2,$bd,$T3b
|
||
fmul $dota,$A3,$bc
|
||
fmul $dotb,$A3,$bd
|
||
lfd $A2,24($nap_d) ; load a[j+1] in double format
|
||
lfd $A3,32($nap_d)
|
||
|
||
fmadd $T1a,$N1,$na,$T1a
|
||
fmadd $T1b,$N1,$nb,$T1b
|
||
ld $t0,`$FRAME+0`($sp)
|
||
ld $t1,`$FRAME+8`($sp)
|
||
fmadd $T2a,$N2,$na,$T2a
|
||
fmadd $T2b,$N2,$nb,$T2b
|
||
ld $t2,`$FRAME+16`($sp)
|
||
ld $t3,`$FRAME+24`($sp)
|
||
fmadd $T3a,$N3,$na,$T3a
|
||
fmadd $T3b,$N3,$nb,$T3b
|
||
add $t0,$t0,$carry ; can not overflow
|
||
ld $t4,`$FRAME+32`($sp)
|
||
ld $t5,`$FRAME+40`($sp)
|
||
fmadd $T0a,$N0,$na,$T0a
|
||
fmadd $T0b,$N0,$nb,$T0b
|
||
srdi $carry,$t0,16
|
||
add $t1,$t1,$carry
|
||
srdi $carry,$t1,16
|
||
ld $t6,`$FRAME+48`($sp)
|
||
ld $t7,`$FRAME+56`($sp)
|
||
|
||
fmadd $T1a,$N0,$nc,$T1a
|
||
fmadd $T1b,$N0,$nd,$T1b
|
||
insrdi $t0,$t1,16,32
|
||
ld $t1,8($tp) ; tp[j]
|
||
fmadd $T2a,$N1,$nc,$T2a
|
||
fmadd $T2b,$N1,$nd,$T2b
|
||
add $t2,$t2,$carry
|
||
fmadd $T3a,$N2,$nc,$T3a
|
||
fmadd $T3b,$N2,$nd,$T3b
|
||
srdi $carry,$t2,16
|
||
insrdi $t0,$t2,16,16
|
||
fmadd $dota,$N3,$nc,$dota
|
||
fmadd $dotb,$N3,$nd,$dotb
|
||
add $t3,$t3,$carry
|
||
ldu $t2,16($tp) ; tp[j+1]
|
||
srdi $carry,$t3,16
|
||
insrdi $t0,$t3,16,0 ; 0..63 bits
|
||
add $t4,$t4,$carry
|
||
|
||
fctid $T0a,$T0a
|
||
fctid $T0b,$T0b
|
||
srdi $carry,$t4,16
|
||
fctid $T1a,$T1a
|
||
fctid $T1b,$T1b
|
||
add $t5,$t5,$carry
|
||
fctid $T2a,$T2a
|
||
fctid $T2b,$T2b
|
||
srdi $carry,$t5,16
|
||
insrdi $t4,$t5,16,32
|
||
fctid $T3a,$T3a
|
||
fctid $T3b,$T3b
|
||
add $t6,$t6,$carry
|
||
srdi $carry,$t6,16
|
||
insrdi $t4,$t6,16,16
|
||
|
||
stfd $T0a,`$FRAME+0`($sp)
|
||
stfd $T0b,`$FRAME+8`($sp)
|
||
add $t7,$t7,$carry
|
||
addc $t3,$t0,$t1
|
||
stfd $T1a,`$FRAME+16`($sp)
|
||
stfd $T1b,`$FRAME+24`($sp)
|
||
insrdi $t4,$t7,16,0 ; 64..127 bits
|
||
srdi $carry,$t7,16 ; upper 33 bits
|
||
stfd $T2a,`$FRAME+32`($sp)
|
||
stfd $T2b,`$FRAME+40`($sp)
|
||
adde $t5,$t4,$t2
|
||
stfd $T3a,`$FRAME+48`($sp)
|
||
stfd $T3b,`$FRAME+56`($sp)
|
||
addze $carry,$carry
|
||
std $t3,-16($tp) ; tp[j-1]
|
||
std $t5,-8($tp) ; tp[j]
|
||
bdnz- Linner
|
||
|
||
fctid $dota,$dota
|
||
fctid $dotb,$dotb
|
||
ld $t0,`$FRAME+0`($sp)
|
||
ld $t1,`$FRAME+8`($sp)
|
||
ld $t2,`$FRAME+16`($sp)
|
||
ld $t3,`$FRAME+24`($sp)
|
||
ld $t4,`$FRAME+32`($sp)
|
||
ld $t5,`$FRAME+40`($sp)
|
||
ld $t6,`$FRAME+48`($sp)
|
||
ld $t7,`$FRAME+56`($sp)
|
||
stfd $dota,`$FRAME+64`($sp)
|
||
stfd $dotb,`$FRAME+72`($sp)
|
||
|
||
add $t0,$t0,$carry ; can not overflow
|
||
srdi $carry,$t0,16
|
||
add $t1,$t1,$carry
|
||
srdi $carry,$t1,16
|
||
insrdi $t0,$t1,16,32
|
||
add $t2,$t2,$carry
|
||
ld $t1,8($tp) ; tp[j]
|
||
srdi $carry,$t2,16
|
||
insrdi $t0,$t2,16,16
|
||
add $t3,$t3,$carry
|
||
ldu $t2,16($tp) ; tp[j+1]
|
||
srdi $carry,$t3,16
|
||
insrdi $t0,$t3,16,0 ; 0..63 bits
|
||
add $t4,$t4,$carry
|
||
srdi $carry,$t4,16
|
||
add $t5,$t5,$carry
|
||
srdi $carry,$t5,16
|
||
insrdi $t4,$t5,16,32
|
||
add $t6,$t6,$carry
|
||
srdi $carry,$t6,16
|
||
insrdi $t4,$t6,16,16
|
||
add $t7,$t7,$carry
|
||
insrdi $t4,$t7,16,0 ; 64..127 bits
|
||
srdi $carry,$t7,16 ; upper 33 bits
|
||
ld $t6,`$FRAME+64`($sp)
|
||
ld $t7,`$FRAME+72`($sp)
|
||
|
||
addc $t3,$t0,$t1
|
||
adde $t5,$t4,$t2
|
||
addze $carry,$carry
|
||
|
||
std $t3,-16($tp) ; tp[j-1]
|
||
std $t5,-8($tp) ; tp[j]
|
||
|
||
add $carry,$carry,$ovf ; comsume upmost overflow
|
||
add $t6,$t6,$carry ; can not overflow
|
||
srdi $carry,$t6,16
|
||
add $t7,$t7,$carry
|
||
insrdi $t6,$t7,48,0
|
||
srdi $ovf,$t7,48
|
||
std $t6,0($tp) ; tp[num-1]
|
||
|
||
slwi $t7,$num,2
|
||
addi $i,$i,8
|
||
subf $nap_d,$t7,$nap_d ; rewind pointer
|
||
cmpw $i,$num
|
||
blt- Louter
|
||
|
||
subf $np,$num,$np ; rewind np
|
||
addi $j,$j,1 ; restore counter
|
||
subfc $i,$i,$i ; j=0 and "clear" XER[CA]
|
||
addi $tp,$sp,`$FRAME+$TRANSFER+8`
|
||
addi $t4,$sp,`$FRAME+$TRANSFER+16`
|
||
addi $t5,$np,8
|
||
addi $t6,$rp,8
|
||
mtctr $j
|
||
|
||
.align 4
|
||
Lsub: ldx $t0,$tp,$i
|
||
ldx $t1,$np,$i
|
||
ldx $t2,$t4,$i
|
||
ldx $t3,$t5,$i
|
||
subfe $t0,$t1,$t0 ; tp[j]-np[j]
|
||
subfe $t2,$t3,$t2 ; tp[j+1]-np[j+1]
|
||
stdx $t0,$rp,$i
|
||
stdx $t2,$t6,$i
|
||
addi $i,$i,16
|
||
bdnz- Lsub
|
||
|
||
li $i,0
|
||
subfe $ovf,$i,$ovf ; handle upmost overflow bit
|
||
and $ap,$tp,$ovf
|
||
andc $np,$rp,$ovf
|
||
or $ap,$ap,$np ; ap=borrow?tp:rp
|
||
addi $t7,$ap,8
|
||
mtctr $j
|
||
|
||
.align 4
|
||
Lcopy: ; copy or in-place refresh
|
||
ldx $t0,$ap,$i
|
||
ldx $t1,$t7,$i
|
||
std $i,8($nap_d) ; zap nap_d
|
||
std $i,16($nap_d)
|
||
std $i,24($nap_d)
|
||
std $i,32($nap_d)
|
||
std $i,40($nap_d)
|
||
std $i,48($nap_d)
|
||
std $i,56($nap_d)
|
||
stdu $i,64($nap_d)
|
||
stdx $t0,$rp,$i
|
||
stdx $t1,$t6,$i
|
||
stdx $i,$tp,$i ; zap tp at once
|
||
stdx $i,$t4,$i
|
||
addi $i,$i,16
|
||
bdnz- Lcopy
|
||
|
||
$POP r14,`2*$SIZE_T`($sp)
|
||
$POP r15,`3*$SIZE_T`($sp)
|
||
$POP r16,`4*$SIZE_T`($sp)
|
||
$POP r17,`5*$SIZE_T`($sp)
|
||
$POP r18,`6*$SIZE_T`($sp)
|
||
$POP r19,`7*$SIZE_T`($sp)
|
||
$POP r20,`8*$SIZE_T`($sp)
|
||
$POP r21,`9*$SIZE_T`($sp)
|
||
$POP r22,`10*$SIZE_T`($sp)
|
||
$POP r23,`11*$SIZE_T`($sp)
|
||
lfd f14,`12*$SIZE_T+0`($sp)
|
||
lfd f15,`12*$SIZE_T+8`($sp)
|
||
lfd f16,`12*$SIZE_T+16`($sp)
|
||
lfd f17,`12*$SIZE_T+24`($sp)
|
||
lfd f18,`12*$SIZE_T+32`($sp)
|
||
lfd f19,`12*$SIZE_T+40`($sp)
|
||
lfd f20,`12*$SIZE_T+48`($sp)
|
||
lfd f21,`12*$SIZE_T+56`($sp)
|
||
lfd f22,`12*$SIZE_T+64`($sp)
|
||
lfd f23,`12*$SIZE_T+72`($sp)
|
||
lfd f24,`12*$SIZE_T+80`($sp)
|
||
lfd f25,`12*$SIZE_T+88`($sp)
|
||
$POP $sp,0($sp)
|
||
li r3,1 ; signal "handled"
|
||
blr
|
||
.long 0
|
||
.asciz "Montgomery Multiplication for PPC64, CRYPTOGAMS by <appro\@fy.chalmers.se>"
|
||
___
|
||
|
||
$code =~ s/\`([^\`]*)\`/eval $1/gem;
|
||
print $code;
|
||
close STDOUT;
|