287 lines
7.5 KiB
C
287 lines
7.5 KiB
C
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef WCD9XXX_CODEC_COMMON
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#define WCD9XXX_CODEC_COMMON
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#include "wcd9xxx-resmgr.h"
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#define WCD9XXX_CLSH_REQ_ENABLE true
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#define WCD9XXX_CLSH_REQ_DISABLE false
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#define WCD9XXX_CLSH_EVENT_PRE_DAC 0x01
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#define WCD9XXX_CLSH_EVENT_POST_PA 0x02
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/* Basic states for Class H state machine.
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* represented as a bit mask within a u8 data type
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* bit 0: EAR mode
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* bit 1: HPH Left mode
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* bit 2: HPH Right mode
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* bit 3: Lineout mode
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* bit 4: Ultrasound mode
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*/
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#define WCD9XXX_CLSH_STATE_IDLE 0x00
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#define WCD9XXX_CLSH_STATE_EAR (0x01 << 0)
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#define WCD9XXX_CLSH_STATE_HPHL (0x01 << 1)
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#define WCD9XXX_CLSH_STATE_HPHR (0x01 << 2)
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#define WCD9XXX_CLSH_STATE_LO (0x01 << 3)
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#define NUM_CLSH_STATES (0x01 << 4)
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#define WCD9XXX_CLSAB_STATE_IDLE 0x00
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#define WCD9XXX_CLSAB_STATE_HPHL (0x01 << 1)
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#define WCD9XXX_CLSAB_STATE_HPHR (0x01 << 2)
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#define WCD9XXX_CLSAB_REQ_ENABLE true
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#define WCD9XXX_CLSAB_REQ_DISABLE false
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#define WCD9XXX_NON_UHQA_MODE 0
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#define WCD9XXX_DMIC_SAMPLE_RATE_DIV_2 0x0
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#define WCD9XXX_DMIC_SAMPLE_RATE_DIV_3 0x1
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#define WCD9XXX_DMIC_SAMPLE_RATE_DIV_4 0x2
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#define WCD9XXX_DMIC_B1_CTL_DIV_2 0x00
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#define WCD9XXX_DMIC_B1_CTL_DIV_3 0x22
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#define WCD9XXX_DMIC_B1_CTL_DIV_4 0x44
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#define WCD9XXX_DMIC_B2_CTL_DIV_2 0x00
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#define WCD9XXX_DMIC_B2_CTL_DIV_3 0x02
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#define WCD9XXX_DMIC_B2_CTL_DIV_4 0x04
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#define WCD9XXX_ANC_DMIC_X2_ON 0x1
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#define WCD9XXX_ANC_DMIC_X2_OFF 0x0
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/* Derived State: Bits 1 and 2 should be set for Headphone stereo */
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#define WCD9XXX_CLSH_STATE_HPH_ST (WCD9XXX_CLSH_STATE_HPHL | \
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WCD9XXX_CLSH_STATE_HPHR)
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#define WCD9XXX_CLSH_STATE_HPHL_EAR (WCD9XXX_CLSH_STATE_HPHL | \
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WCD9XXX_CLSH_STATE_EAR)
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#define WCD9XXX_CLSH_STATE_HPHR_EAR (WCD9XXX_CLSH_STATE_HPHR | \
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WCD9XXX_CLSH_STATE_EAR)
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#define WCD9XXX_CLSH_STATE_HPH_ST_EAR (WCD9XXX_CLSH_STATE_HPH_ST | \
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WCD9XXX_CLSH_STATE_EAR)
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#define WCD9XXX_CLSH_STATE_HPHL_LO (WCD9XXX_CLSH_STATE_HPHL | \
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WCD9XXX_CLSH_STATE_LO)
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#define WCD9XXX_CLSH_STATE_HPHR_LO (WCD9XXX_CLSH_STATE_HPHR | \
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WCD9XXX_CLSH_STATE_LO)
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#define WCD9XXX_CLSH_STATE_HPH_ST_LO (WCD9XXX_CLSH_STATE_HPH_ST | \
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WCD9XXX_CLSH_STATE_LO)
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#define WCD9XXX_CLSH_STATE_EAR_LO (WCD9XXX_CLSH_STATE_EAR | \
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WCD9XXX_CLSH_STATE_LO)
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#define WCD9XXX_CLSH_STATE_HPHL_EAR_LO (WCD9XXX_CLSH_STATE_HPHL | \
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WCD9XXX_CLSH_STATE_EAR | \
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WCD9XXX_CLSH_STATE_LO)
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#define WCD9XXX_CLSH_STATE_HPHR_EAR_LO (WCD9XXX_CLSH_STATE_HPHR | \
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WCD9XXX_CLSH_STATE_EAR | \
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WCD9XXX_CLSH_STATE_LO)
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#define WCD9XXX_CLSH_STATE_HPH_ST_EAR_LO (WCD9XXX_CLSH_STATE_HPH_ST | \
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WCD9XXX_CLSH_STATE_EAR | \
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WCD9XXX_CLSH_STATE_LO)
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struct wcd9xxx_reg_mask_val {
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u16 reg;
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u8 mask;
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u8 val;
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};
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enum ncp_fclk_level {
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NCP_FCLK_LEVEL_8,
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NCP_FCLK_LEVEL_5,
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NCP_FCLK_LEVEL_MAX,
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};
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/* Class H data that the codec driver will maintain */
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struct wcd9xxx_clsh_cdc_data {
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u8 state;
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int buck_mv;
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bool is_dynamic_vdd_cp;
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int clsh_users;
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int buck_users;
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int ncp_users[NCP_FCLK_LEVEL_MAX];
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struct wcd9xxx_resmgr *resmgr;
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};
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struct wcd9xxx_anc_header {
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u32 reserved[3];
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u32 num_anc_slots;
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};
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enum wcd9xxx_buck_volt {
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WCD9XXX_CDC_BUCK_UNSUPPORTED = 0,
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WCD9XXX_CDC_BUCK_MV_1P8 = 1800000,
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WCD9XXX_CDC_BUCK_MV_2P15 = 2150000,
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};
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struct mad_audio_header {
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u32 reserved[3];
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u32 num_reg_cfg;
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};
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struct mad_microphone_info {
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uint8_t input_microphone;
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uint8_t cycle_time;
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uint8_t settle_time;
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uint8_t padding;
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} __packed;
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struct mad_micbias_info {
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uint8_t micbias;
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uint8_t k_factor;
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uint8_t external_bypass_capacitor;
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uint8_t internal_biasing;
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uint8_t cfilter;
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uint8_t padding[3];
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} __packed;
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struct mad_rms_audio_beacon_info {
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uint8_t rms_omit_samples;
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uint8_t rms_comp_time;
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uint8_t detection_mechanism;
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uint8_t rms_diff_threshold;
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uint8_t rms_threshold_lsb;
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uint8_t rms_threshold_msb;
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uint8_t padding[2];
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uint8_t iir_coefficients[36];
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} __packed;
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struct mad_rms_ultrasound_info {
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uint8_t rms_comp_time;
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uint8_t detection_mechanism;
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uint8_t rms_diff_threshold;
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uint8_t rms_threshold_lsb;
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uint8_t rms_threshold_msb;
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uint8_t padding[3];
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uint8_t iir_coefficients[36];
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} __packed;
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struct mad_audio_cal {
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uint32_t version;
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struct mad_microphone_info microphone_info;
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struct mad_micbias_info micbias_info;
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struct mad_rms_audio_beacon_info audio_info;
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struct mad_rms_audio_beacon_info beacon_info;
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struct mad_rms_ultrasound_info ultrasound_info;
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} __packed;
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extern void wcd9xxx_clsh_fsm(struct snd_soc_codec *codec,
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struct wcd9xxx_clsh_cdc_data *cdc_clsh_d,
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u8 req_state, bool req_type, u8 clsh_event);
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extern void wcd9xxx_enable_high_perf_mode(struct snd_soc_codec *codec,
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struct wcd9xxx_clsh_cdc_data *clsh_d,
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u8 uhqa_mode, u8 req_state, bool req_type);
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extern void wcd9xxx_clsh_init(struct wcd9xxx_clsh_cdc_data *clsh,
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struct wcd9xxx_resmgr *resmgr);
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extern void wcd9xxx_clsh_imped_config(struct snd_soc_codec *codec,
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int imped);
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enum wcd9xxx_codec_event {
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WCD9XXX_CODEC_EVENT_CODEC_UP = 0,
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};
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struct wcd9xxx_register_save_node {
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struct list_head lh;
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u16 reg;
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u16 value;
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};
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extern int wcd9xxx_soc_update_bits_push(struct snd_soc_codec *codec,
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struct list_head *lh,
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uint16_t reg, uint8_t mask,
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uint8_t value, int delay);
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extern void wcd9xxx_restore_registers(struct snd_soc_codec *codec,
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struct list_head *lh);
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enum {
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RESERVED = 0,
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AANC_LPF_FF_FB = 1,
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AANC_LPF_COEFF_MSB,
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AANC_LPF_COEFF_LSB,
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HW_MAD_AUDIO_ENABLE,
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HW_MAD_ULTR_ENABLE,
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HW_MAD_BEACON_ENABLE,
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HW_MAD_AUDIO_SLEEP_TIME,
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HW_MAD_ULTR_SLEEP_TIME,
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HW_MAD_BEACON_SLEEP_TIME,
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HW_MAD_TX_AUDIO_SWITCH_OFF,
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HW_MAD_TX_ULTR_SWITCH_OFF,
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HW_MAD_TX_BEACON_SWITCH_OFF,
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MAD_AUDIO_INT_DEST_SELECT_REG,
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MAD_ULT_INT_DEST_SELECT_REG,
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MAD_BEACON_INT_DEST_SELECT_REG,
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MAD_CLIP_INT_DEST_SELECT_REG,
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MAD_VBAT_INT_DEST_SELECT_REG,
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MAD_AUDIO_INT_MASK_REG,
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MAD_ULT_INT_MASK_REG,
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MAD_BEACON_INT_MASK_REG,
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MAD_CLIP_INT_MASK_REG,
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MAD_VBAT_INT_MASK_REG,
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MAD_AUDIO_INT_STATUS_REG,
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MAD_ULT_INT_STATUS_REG,
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MAD_BEACON_INT_STATUS_REG,
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MAD_CLIP_INT_STATUS_REG,
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MAD_VBAT_INT_STATUS_REG,
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MAD_AUDIO_INT_CLEAR_REG,
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MAD_ULT_INT_CLEAR_REG,
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MAD_BEACON_INT_CLEAR_REG,
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MAD_CLIP_INT_CLEAR_REG,
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MAD_VBAT_INT_CLEAR_REG,
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SB_PGD_PORT_TX_WATERMARK_N,
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SB_PGD_PORT_TX_ENABLE_N,
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SB_PGD_PORT_RX_WATERMARK_N,
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SB_PGD_PORT_RX_ENABLE_N,
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SB_PGD_TX_PORTn_MULTI_CHNL_0,
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SB_PGD_TX_PORTn_MULTI_CHNL_1,
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SB_PGD_RX_PORTn_MULTI_CHNL_0,
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SB_PGD_RX_PORTn_MULTI_CHNL_1,
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AANC_FF_GAIN_ADAPTIVE,
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AANC_FFGAIN_ADAPTIVE_EN,
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AANC_GAIN_CONTROL,
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SPKR_CLIP_PIPE_BANK_SEL,
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SPKR_CLIPDET_VAL0,
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SPKR_CLIPDET_VAL1,
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SPKR_CLIPDET_VAL2,
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SPKR_CLIPDET_VAL3,
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SPKR_CLIPDET_VAL4,
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SPKR_CLIPDET_VAL5,
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SPKR_CLIPDET_VAL6,
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SPKR_CLIPDET_VAL7,
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VBAT_RELEASE_INT_DEST_SELECT_REG,
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VBAT_RELEASE_INT_MASK_REG,
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VBAT_RELEASE_INT_STATUS_REG,
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VBAT_RELEASE_INT_CLEAR_REG,
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MAD2_CLIP_INT_DEST_SELECT_REG,
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MAD2_CLIP_INT_MASK_REG,
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MAD2_CLIP_INT_STATUS_REG,
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MAD2_CLIP_INT_CLEAR_REG,
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SPKR2_CLIP_PIPE_BANK_SEL,
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SPKR2_CLIPDET_VAL0,
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SPKR2_CLIPDET_VAL1,
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SPKR2_CLIPDET_VAL2,
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SPKR2_CLIPDET_VAL3,
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SPKR2_CLIPDET_VAL4,
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SPKR2_CLIPDET_VAL5,
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SPKR2_CLIPDET_VAL6,
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SPKR2_CLIPDET_VAL7,
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MAX_CFG_REGISTERS,
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};
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#endif
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