755 lines
30 KiB
C
755 lines
30 KiB
C
/******************************************************************************
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* xen.h
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*
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* Guest OS interface to Xen.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Copyright (c) 2004, K A Fraser
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*/
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#ifndef __XEN_PUBLIC_XEN_H__
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#define __XEN_PUBLIC_XEN_H__
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#include <asm/xen/interface.h>
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/*
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* XEN "SYSTEM CALLS" (a.k.a. HYPERCALLS).
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*/
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/*
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* x86_32: EAX = vector; EBX, ECX, EDX, ESI, EDI = args 1, 2, 3, 4, 5.
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* EAX = return value
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* (argument registers may be clobbered on return)
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* x86_64: RAX = vector; RDI, RSI, RDX, R10, R8, R9 = args 1, 2, 3, 4, 5, 6.
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* RAX = return value
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* (argument registers not clobbered on return; RCX, R11 are)
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*/
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#define __HYPERVISOR_set_trap_table 0
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#define __HYPERVISOR_mmu_update 1
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#define __HYPERVISOR_set_gdt 2
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#define __HYPERVISOR_stack_switch 3
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#define __HYPERVISOR_set_callbacks 4
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#define __HYPERVISOR_fpu_taskswitch 5
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#define __HYPERVISOR_sched_op_compat 6
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#define __HYPERVISOR_dom0_op 7
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#define __HYPERVISOR_set_debugreg 8
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#define __HYPERVISOR_get_debugreg 9
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#define __HYPERVISOR_update_descriptor 10
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#define __HYPERVISOR_memory_op 12
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#define __HYPERVISOR_multicall 13
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#define __HYPERVISOR_update_va_mapping 14
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#define __HYPERVISOR_set_timer_op 15
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#define __HYPERVISOR_event_channel_op_compat 16
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#define __HYPERVISOR_xen_version 17
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#define __HYPERVISOR_console_io 18
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#define __HYPERVISOR_physdev_op_compat 19
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#define __HYPERVISOR_grant_table_op 20
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#define __HYPERVISOR_vm_assist 21
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#define __HYPERVISOR_update_va_mapping_otherdomain 22
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#define __HYPERVISOR_iret 23 /* x86 only */
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#define __HYPERVISOR_vcpu_op 24
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#define __HYPERVISOR_set_segment_base 25 /* x86/64 only */
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#define __HYPERVISOR_mmuext_op 26
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#define __HYPERVISOR_acm_op 27
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#define __HYPERVISOR_nmi_op 28
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#define __HYPERVISOR_sched_op 29
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#define __HYPERVISOR_callback_op 30
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#define __HYPERVISOR_xenoprof_op 31
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#define __HYPERVISOR_event_channel_op 32
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#define __HYPERVISOR_physdev_op 33
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#define __HYPERVISOR_hvm_op 34
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#define __HYPERVISOR_tmem_op 38
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/* Architecture-specific hypercall definitions. */
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#define __HYPERVISOR_arch_0 48
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#define __HYPERVISOR_arch_1 49
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#define __HYPERVISOR_arch_2 50
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#define __HYPERVISOR_arch_3 51
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#define __HYPERVISOR_arch_4 52
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#define __HYPERVISOR_arch_5 53
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#define __HYPERVISOR_arch_6 54
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#define __HYPERVISOR_arch_7 55
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/*
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* VIRTUAL INTERRUPTS
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*
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* Virtual interrupts that a guest OS may receive from Xen.
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* In the side comments, 'V.' denotes a per-VCPU VIRQ while 'G.' denotes a
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* global VIRQ. The former can be bound once per VCPU and cannot be re-bound.
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* The latter can be allocated only once per guest: they must initially be
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* allocated to VCPU0 but can subsequently be re-bound.
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*/
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#define VIRQ_TIMER 0 /* V. Timebase update, and/or requested timeout. */
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#define VIRQ_DEBUG 1 /* V. Request guest to dump debug info. */
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#define VIRQ_CONSOLE 2 /* G. (DOM0) Bytes received on emergency console. */
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#define VIRQ_DOM_EXC 3 /* G. (DOM0) Exceptional event for some domain. */
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#define VIRQ_TBUF 4 /* G. (DOM0) Trace buffer has records available. */
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#define VIRQ_DEBUGGER 6 /* G. (DOM0) A domain has paused for debugging. */
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#define VIRQ_XENOPROF 7 /* V. XenOprofile interrupt: new sample available */
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#define VIRQ_CON_RING 8 /* G. (DOM0) Bytes received on console */
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#define VIRQ_PCPU_STATE 9 /* G. (DOM0) PCPU state changed */
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#define VIRQ_MEM_EVENT 10 /* G. (DOM0) A memory event has occured */
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#define VIRQ_XC_RESERVED 11 /* G. Reserved for XenClient */
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#define VIRQ_ENOMEM 12 /* G. (DOM0) Low on heap memory */
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/* Architecture-specific VIRQ definitions. */
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#define VIRQ_ARCH_0 16
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#define VIRQ_ARCH_1 17
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#define VIRQ_ARCH_2 18
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#define VIRQ_ARCH_3 19
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#define VIRQ_ARCH_4 20
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#define VIRQ_ARCH_5 21
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#define VIRQ_ARCH_6 22
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#define VIRQ_ARCH_7 23
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#define NR_VIRQS 24
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/*
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* enum neg_errnoval HYPERVISOR_mmu_update(const struct mmu_update reqs[],
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* unsigned count, unsigned *done_out,
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* unsigned foreigndom)
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* @reqs is an array of mmu_update_t structures ((ptr, val) pairs).
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* @count is the length of the above array.
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* @pdone is an output parameter indicating number of completed operations
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* @foreigndom[15:0]: FD, the expected owner of data pages referenced in this
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* hypercall invocation. Can be DOMID_SELF.
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* @foreigndom[31:16]: PFD, the expected owner of pagetable pages referenced
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* in this hypercall invocation. The value of this field
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* (x) encodes the PFD as follows:
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* x == 0 => PFD == DOMID_SELF
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* x != 0 => PFD == x - 1
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*
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* Sub-commands: ptr[1:0] specifies the appropriate MMU_* command.
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* -------------
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* ptr[1:0] == MMU_NORMAL_PT_UPDATE:
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* Updates an entry in a page table belonging to PFD. If updating an L1 table,
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* and the new table entry is valid/present, the mapped frame must belong to
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* FD. If attempting to map an I/O page then the caller assumes the privilege
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* of the FD.
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* FD == DOMID_IO: Permit /only/ I/O mappings, at the priv level of the caller.
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* FD == DOMID_XEN: Map restricted areas of Xen's heap space.
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* ptr[:2] -- Machine address of the page-table entry to modify.
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* val -- Value to write.
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*
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* There also certain implicit requirements when using this hypercall. The
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* pages that make up a pagetable must be mapped read-only in the guest.
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* This prevents uncontrolled guest updates to the pagetable. Xen strictly
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* enforces this, and will disallow any pagetable update which will end up
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* mapping pagetable page RW, and will disallow using any writable page as a
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* pagetable. In practice it means that when constructing a page table for a
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* process, thread, etc, we MUST be very dilligient in following these rules:
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* 1). Start with top-level page (PGD or in Xen language: L4). Fill out
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* the entries.
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* 2). Keep on going, filling out the upper (PUD or L3), and middle (PMD
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* or L2).
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* 3). Start filling out the PTE table (L1) with the PTE entries. Once
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* done, make sure to set each of those entries to RO (so writeable bit
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* is unset). Once that has been completed, set the PMD (L2) for this
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* PTE table as RO.
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* 4). When completed with all of the PMD (L2) entries, and all of them have
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* been set to RO, make sure to set RO the PUD (L3). Do the same
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* operation on PGD (L4) pagetable entries that have a PUD (L3) entry.
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* 5). Now before you can use those pages (so setting the cr3), you MUST also
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* pin them so that the hypervisor can verify the entries. This is done
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* via the HYPERVISOR_mmuext_op(MMUEXT_PIN_L4_TABLE, guest physical frame
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* number of the PGD (L4)). And this point the HYPERVISOR_mmuext_op(
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* MMUEXT_NEW_BASEPTR, guest physical frame number of the PGD (L4)) can be
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* issued.
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* For 32-bit guests, the L4 is not used (as there is less pagetables), so
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* instead use L3.
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* At this point the pagetables can be modified using the MMU_NORMAL_PT_UPDATE
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* hypercall. Also if so desired the OS can also try to write to the PTE
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* and be trapped by the hypervisor (as the PTE entry is RO).
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*
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* To deallocate the pages, the operations are the reverse of the steps
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* mentioned above. The argument is MMUEXT_UNPIN_TABLE for all levels and the
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* pagetable MUST not be in use (meaning that the cr3 is not set to it).
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*
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* ptr[1:0] == MMU_MACHPHYS_UPDATE:
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* Updates an entry in the machine->pseudo-physical mapping table.
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* ptr[:2] -- Machine address within the frame whose mapping to modify.
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* The frame must belong to the FD, if one is specified.
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* val -- Value to write into the mapping entry.
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*
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* ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD:
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* As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed
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* with those in @val.
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*
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* @val is usually the machine frame number along with some attributes.
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* The attributes by default follow the architecture defined bits. Meaning that
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* if this is a X86_64 machine and four page table layout is used, the layout
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* of val is:
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* - 63 if set means No execute (NX)
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* - 46-13 the machine frame number
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* - 12 available for guest
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* - 11 available for guest
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* - 10 available for guest
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* - 9 available for guest
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* - 8 global
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* - 7 PAT (PSE is disabled, must use hypercall to make 4MB or 2MB pages)
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* - 6 dirty
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* - 5 accessed
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* - 4 page cached disabled
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* - 3 page write through
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* - 2 userspace accessible
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* - 1 writeable
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* - 0 present
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*
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* The one bits that does not fit with the default layout is the PAGE_PSE
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* also called PAGE_PAT). The MMUEXT_[UN]MARK_SUPER arguments to the
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* HYPERVISOR_mmuext_op serve as mechanism to set a pagetable to be 4MB
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* (or 2MB) instead of using the PAGE_PSE bit.
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*
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* The reason that the PAGE_PSE (bit 7) is not being utilized is due to Xen
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* using it as the Page Attribute Table (PAT) bit - for details on it please
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* refer to Intel SDM 10.12. The PAT allows to set the caching attributes of
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* pages instead of using MTRRs.
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*
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* The PAT MSR is as follows (it is a 64-bit value, each entry is 8 bits):
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* PAT4 PAT0
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* +-----+-----+----+----+----+-----+----+----+
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* | UC | UC- | WC | WB | UC | UC- | WC | WB | <= Linux
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* +-----+-----+----+----+----+-----+----+----+
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* | UC | UC- | WT | WB | UC | UC- | WT | WB | <= BIOS (default when machine boots)
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* +-----+-----+----+----+----+-----+----+----+
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* | rsv | rsv | WP | WC | UC | UC- | WT | WB | <= Xen
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* +-----+-----+----+----+----+-----+----+----+
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*
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* The lookup of this index table translates to looking up
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* Bit 7, Bit 4, and Bit 3 of val entry:
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*
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* PAT/PSE (bit 7) ... PCD (bit 4) .. PWT (bit 3).
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*
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* If all bits are off, then we are using PAT0. If bit 3 turned on,
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* then we are using PAT1, if bit 3 and bit 4, then PAT2..
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*
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* As you can see, the Linux PAT1 translates to PAT4 under Xen. Which means
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* that if a guest that follows Linux's PAT setup and would like to set Write
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* Combined on pages it MUST use PAT4 entry. Meaning that Bit 7 (PAGE_PAT) is
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* set. For example, under Linux it only uses PAT0, PAT1, and PAT2 for the
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* caching as:
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*
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* WB = none (so PAT0)
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* WC = PWT (bit 3 on)
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* UC = PWT | PCD (bit 3 and 4 are on).
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*
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* To make it work with Xen, it needs to translate the WC bit as so:
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*
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* PWT (so bit 3 on) --> PAT (so bit 7 is on) and clear bit 3
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*
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* And to translate back it would:
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*
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* PAT (bit 7 on) --> PWT (bit 3 on) and clear bit 7.
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*/
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#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */
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#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */
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#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */
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/*
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* MMU EXTENDED OPERATIONS
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*
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* enum neg_errnoval HYPERVISOR_mmuext_op(mmuext_op_t uops[],
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* unsigned int count,
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* unsigned int *pdone,
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* unsigned int foreigndom)
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*/
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/* HYPERVISOR_mmuext_op() accepts a list of mmuext_op structures.
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* A foreigndom (FD) can be specified (or DOMID_SELF for none).
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* Where the FD has some effect, it is described below.
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*
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* cmd: MMUEXT_(UN)PIN_*_TABLE
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* mfn: Machine frame number to be (un)pinned as a p.t. page.
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* The frame must belong to the FD, if one is specified.
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*
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* cmd: MMUEXT_NEW_BASEPTR
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* mfn: Machine frame number of new page-table base to install in MMU.
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*
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* cmd: MMUEXT_NEW_USER_BASEPTR [x86/64 only]
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* mfn: Machine frame number of new page-table base to install in MMU
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* when in user space.
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*
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* cmd: MMUEXT_TLB_FLUSH_LOCAL
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* No additional arguments. Flushes local TLB.
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*
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* cmd: MMUEXT_INVLPG_LOCAL
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* linear_addr: Linear address to be flushed from the local TLB.
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*
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* cmd: MMUEXT_TLB_FLUSH_MULTI
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* vcpumask: Pointer to bitmap of VCPUs to be flushed.
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*
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* cmd: MMUEXT_INVLPG_MULTI
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* linear_addr: Linear address to be flushed.
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* vcpumask: Pointer to bitmap of VCPUs to be flushed.
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*
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* cmd: MMUEXT_TLB_FLUSH_ALL
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* No additional arguments. Flushes all VCPUs' TLBs.
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*
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* cmd: MMUEXT_INVLPG_ALL
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* linear_addr: Linear address to be flushed from all VCPUs' TLBs.
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*
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* cmd: MMUEXT_FLUSH_CACHE
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* No additional arguments. Writes back and flushes cache contents.
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*
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* cmd: MMUEXT_FLUSH_CACHE_GLOBAL
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* No additional arguments. Writes back and flushes cache contents
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* on all CPUs in the system.
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*
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* cmd: MMUEXT_SET_LDT
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* linear_addr: Linear address of LDT base (NB. must be page-aligned).
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* nr_ents: Number of entries in LDT.
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*
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* cmd: MMUEXT_CLEAR_PAGE
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* mfn: Machine frame number to be cleared.
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*
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* cmd: MMUEXT_COPY_PAGE
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* mfn: Machine frame number of the destination page.
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* src_mfn: Machine frame number of the source page.
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*
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* cmd: MMUEXT_[UN]MARK_SUPER
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* mfn: Machine frame number of head of superpage to be [un]marked.
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*/
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#define MMUEXT_PIN_L1_TABLE 0
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#define MMUEXT_PIN_L2_TABLE 1
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#define MMUEXT_PIN_L3_TABLE 2
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#define MMUEXT_PIN_L4_TABLE 3
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#define MMUEXT_UNPIN_TABLE 4
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#define MMUEXT_NEW_BASEPTR 5
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#define MMUEXT_TLB_FLUSH_LOCAL 6
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#define MMUEXT_INVLPG_LOCAL 7
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#define MMUEXT_TLB_FLUSH_MULTI 8
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#define MMUEXT_INVLPG_MULTI 9
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#define MMUEXT_TLB_FLUSH_ALL 10
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#define MMUEXT_INVLPG_ALL 11
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#define MMUEXT_FLUSH_CACHE 12
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#define MMUEXT_SET_LDT 13
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#define MMUEXT_NEW_USER_BASEPTR 15
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#define MMUEXT_CLEAR_PAGE 16
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#define MMUEXT_COPY_PAGE 17
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#define MMUEXT_FLUSH_CACHE_GLOBAL 18
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#define MMUEXT_MARK_SUPER 19
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#define MMUEXT_UNMARK_SUPER 20
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#ifndef __ASSEMBLY__
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struct mmuext_op {
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unsigned int cmd;
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union {
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/* [UN]PIN_TABLE, NEW_BASEPTR, NEW_USER_BASEPTR
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* CLEAR_PAGE, COPY_PAGE, [UN]MARK_SUPER */
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xen_pfn_t mfn;
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/* INVLPG_LOCAL, INVLPG_ALL, SET_LDT */
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unsigned long linear_addr;
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} arg1;
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union {
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/* SET_LDT */
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unsigned int nr_ents;
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/* TLB_FLUSH_MULTI, INVLPG_MULTI */
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void *vcpumask;
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/* COPY_PAGE */
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xen_pfn_t src_mfn;
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} arg2;
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};
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DEFINE_GUEST_HANDLE_STRUCT(mmuext_op);
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#endif
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/* These are passed as 'flags' to update_va_mapping. They can be ORed. */
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/* When specifying UVMF_MULTI, also OR in a pointer to a CPU bitmap. */
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/* UVMF_LOCAL is merely UVMF_MULTI with a NULL bitmap pointer. */
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#define UVMF_NONE (0UL<<0) /* No flushing at all. */
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#define UVMF_TLB_FLUSH (1UL<<0) /* Flush entire TLB(s). */
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#define UVMF_INVLPG (2UL<<0) /* Flush only one entry. */
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#define UVMF_FLUSHTYPE_MASK (3UL<<0)
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#define UVMF_MULTI (0UL<<2) /* Flush subset of TLBs. */
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#define UVMF_LOCAL (0UL<<2) /* Flush local TLB. */
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#define UVMF_ALL (1UL<<2) /* Flush all TLBs. */
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/*
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* Commands to HYPERVISOR_console_io().
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*/
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#define CONSOLEIO_write 0
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#define CONSOLEIO_read 1
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/*
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* Commands to HYPERVISOR_vm_assist().
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*/
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#define VMASST_CMD_enable 0
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#define VMASST_CMD_disable 1
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/* x86/32 guests: simulate full 4GB segment limits. */
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#define VMASST_TYPE_4gb_segments 0
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/* x86/32 guests: trap (vector 15) whenever above vmassist is used. */
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#define VMASST_TYPE_4gb_segments_notify 1
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/*
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* x86 guests: support writes to bottom-level PTEs.
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* NB1. Page-directory entries cannot be written.
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* NB2. Guest must continue to remove all writable mappings of PTEs.
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*/
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#define VMASST_TYPE_writable_pagetables 2
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/* x86/PAE guests: support PDPTs above 4GB. */
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#define VMASST_TYPE_pae_extended_cr3 3
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#define MAX_VMASST_TYPE 3
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#ifndef __ASSEMBLY__
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typedef uint16_t domid_t;
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/* Domain ids >= DOMID_FIRST_RESERVED cannot be used for ordinary domains. */
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#define DOMID_FIRST_RESERVED (0x7FF0U)
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/* DOMID_SELF is used in certain contexts to refer to oneself. */
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#define DOMID_SELF (0x7FF0U)
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/*
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* DOMID_IO is used to restrict page-table updates to mapping I/O memory.
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* Although no Foreign Domain need be specified to map I/O pages, DOMID_IO
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* is useful to ensure that no mappings to the OS's own heap are accidentally
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* installed. (e.g., in Linux this could cause havoc as reference counts
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* aren't adjusted on the I/O-mapping code path).
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* This only makes sense in MMUEXT_SET_FOREIGNDOM, but in that context can
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* be specified by any calling domain.
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*/
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#define DOMID_IO (0x7FF1U)
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/*
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* DOMID_XEN is used to allow privileged domains to map restricted parts of
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* Xen's heap space (e.g., the machine_to_phys table).
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* This only makes sense in MMUEXT_SET_FOREIGNDOM, and is only permitted if
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* the caller is privileged.
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*/
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#define DOMID_XEN (0x7FF2U)
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/* DOMID_COW is used as the owner of sharable pages */
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#define DOMID_COW (0x7FF3U)
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/* DOMID_INVALID is used to identify pages with unknown owner. */
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#define DOMID_INVALID (0x7FF4U)
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/* Idle domain. */
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#define DOMID_IDLE (0x7FFFU)
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/*
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* Send an array of these to HYPERVISOR_mmu_update().
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* NB. The fields are natural pointer/address size for this architecture.
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*/
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struct mmu_update {
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uint64_t ptr; /* Machine address of PTE. */
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uint64_t val; /* New contents of PTE. */
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};
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DEFINE_GUEST_HANDLE_STRUCT(mmu_update);
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/*
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* Send an array of these to HYPERVISOR_multicall().
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* NB. The fields are logically the natural register size for this
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* architecture. In cases where xen_ulong_t is larger than this then
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* any unused bits in the upper portion must be zero.
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*/
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struct multicall_entry {
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xen_ulong_t op;
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xen_long_t result;
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xen_ulong_t args[6];
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};
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DEFINE_GUEST_HANDLE_STRUCT(multicall_entry);
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struct vcpu_time_info {
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/*
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* Updates to the following values are preceded and followed
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* by an increment of 'version'. The guest can therefore
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* detect updates by looking for changes to 'version'. If the
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* least-significant bit of the version number is set then an
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* update is in progress and the guest must wait to read a
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* consistent set of values. The correct way to interact with
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* the version number is similar to Linux's seqlock: see the
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* implementations of read_seqbegin/read_seqretry.
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*/
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uint32_t version;
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uint32_t pad0;
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uint64_t tsc_timestamp; /* TSC at last update of time vals. */
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uint64_t system_time; /* Time, in nanosecs, since boot. */
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/*
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* Current system time:
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* system_time + ((tsc - tsc_timestamp) << tsc_shift) * tsc_to_system_mul
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* CPU frequency (Hz):
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* ((10^9 << 32) / tsc_to_system_mul) >> tsc_shift
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*/
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uint32_t tsc_to_system_mul;
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int8_t tsc_shift;
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int8_t pad1[3];
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}; /* 32 bytes */
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struct vcpu_info {
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/*
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* 'evtchn_upcall_pending' is written non-zero by Xen to indicate
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* a pending notification for a particular VCPU. It is then cleared
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* by the guest OS /before/ checking for pending work, thus avoiding
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* a set-and-check race. Note that the mask is only accessed by Xen
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* on the CPU that is currently hosting the VCPU. This means that the
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* pending and mask flags can be updated by the guest without special
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* synchronisation (i.e., no need for the x86 LOCK prefix).
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* This may seem suboptimal because if the pending flag is set by
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* a different CPU then an IPI may be scheduled even when the mask
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* is set. However, note:
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* 1. The task of 'interrupt holdoff' is covered by the per-event-
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* channel mask bits. A 'noisy' event that is continually being
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* triggered can be masked at source at this very precise
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* granularity.
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* 2. The main purpose of the per-VCPU mask is therefore to restrict
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* reentrant execution: whether for concurrency control, or to
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* prevent unbounded stack usage. Whatever the purpose, we expect
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* that the mask will be asserted only for short periods at a time,
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* and so the likelihood of a 'spurious' IPI is suitably small.
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* The mask is read before making an event upcall to the guest: a
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* non-zero mask therefore guarantees that the VCPU will not receive
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* an upcall activation. The mask is cleared when the VCPU requests
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* to block: this avoids wakeup-waiting races.
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*/
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uint8_t evtchn_upcall_pending;
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uint8_t evtchn_upcall_mask;
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xen_ulong_t evtchn_pending_sel;
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struct arch_vcpu_info arch;
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struct pvclock_vcpu_time_info time;
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}; /* 64 bytes (x86) */
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/*
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* Xen/kernel shared data -- pointer provided in start_info.
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* NB. We expect that this struct is smaller than a page.
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*/
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struct shared_info {
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struct vcpu_info vcpu_info[MAX_VIRT_CPUS];
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/*
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* A domain can create "event channels" on which it can send and receive
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* asynchronous event notifications. There are three classes of event that
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* are delivered by this mechanism:
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* 1. Bi-directional inter- and intra-domain connections. Domains must
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* arrange out-of-band to set up a connection (usually by allocating
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* an unbound 'listener' port and avertising that via a storage service
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* such as xenstore).
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* 2. Physical interrupts. A domain with suitable hardware-access
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* privileges can bind an event-channel port to a physical interrupt
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* source.
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* 3. Virtual interrupts ('events'). A domain can bind an event-channel
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* port to a virtual interrupt source, such as the virtual-timer
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* device or the emergency console.
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*
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* Event channels are addressed by a "port index". Each channel is
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* associated with two bits of information:
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* 1. PENDING -- notifies the domain that there is a pending notification
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* to be processed. This bit is cleared by the guest.
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* 2. MASK -- if this bit is clear then a 0->1 transition of PENDING
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* will cause an asynchronous upcall to be scheduled. This bit is only
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* updated by the guest. It is read-only within Xen. If a channel
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* becomes pending while the channel is masked then the 'edge' is lost
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* (i.e., when the channel is unmasked, the guest must manually handle
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* pending notifications as no upcall will be scheduled by Xen).
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*
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* To expedite scanning of pending notifications, any 0->1 pending
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* transition on an unmasked channel causes a corresponding bit in a
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* per-vcpu selector word to be set. Each bit in the selector covers a
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* 'C long' in the PENDING bitfield array.
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*/
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xen_ulong_t evtchn_pending[sizeof(xen_ulong_t) * 8];
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xen_ulong_t evtchn_mask[sizeof(xen_ulong_t) * 8];
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/*
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* Wallclock time: updated only by control software. Guests should base
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* their gettimeofday() syscall on this wallclock-base value.
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*/
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struct pvclock_wall_clock wc;
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struct arch_shared_info arch;
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};
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/*
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* Start-of-day memory layout for the initial domain (DOM0):
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* 1. The domain is started within contiguous virtual-memory region.
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* 2. The contiguous region begins and ends on an aligned 4MB boundary.
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* 3. The region start corresponds to the load address of the OS image.
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* If the load address is not 4MB aligned then the address is rounded down.
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* 4. This the order of bootstrap elements in the initial virtual region:
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* a. relocated kernel image
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* b. initial ram disk [mod_start, mod_len]
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* c. list of allocated page frames [mfn_list, nr_pages]
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* d. start_info_t structure [register ESI (x86)]
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* e. bootstrap page tables [pt_base, CR3 (x86)]
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* f. bootstrap stack [register ESP (x86)]
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* 5. Bootstrap elements are packed together, but each is 4kB-aligned.
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* 6. The initial ram disk may be omitted.
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* 7. The list of page frames forms a contiguous 'pseudo-physical' memory
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* layout for the domain. In particular, the bootstrap virtual-memory
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* region is a 1:1 mapping to the first section of the pseudo-physical map.
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* 8. All bootstrap elements are mapped read-writable for the guest OS. The
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* only exception is the bootstrap page table, which is mapped read-only.
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* 9. There is guaranteed to be at least 512kB padding after the final
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* bootstrap element. If necessary, the bootstrap virtual region is
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* extended by an extra 4MB to ensure this.
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*/
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#define MAX_GUEST_CMDLINE 1024
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struct start_info {
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/* THE FOLLOWING ARE FILLED IN BOTH ON INITIAL BOOT AND ON RESUME. */
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char magic[32]; /* "xen-<version>-<platform>". */
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unsigned long nr_pages; /* Total pages allocated to this domain. */
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unsigned long shared_info; /* MACHINE address of shared info struct. */
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uint32_t flags; /* SIF_xxx flags. */
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xen_pfn_t store_mfn; /* MACHINE page number of shared page. */
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uint32_t store_evtchn; /* Event channel for store communication. */
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union {
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struct {
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xen_pfn_t mfn; /* MACHINE page number of console page. */
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uint32_t evtchn; /* Event channel for console page. */
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} domU;
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struct {
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uint32_t info_off; /* Offset of console_info struct. */
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uint32_t info_size; /* Size of console_info struct from start.*/
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} dom0;
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} console;
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/* THE FOLLOWING ARE ONLY FILLED IN ON INITIAL BOOT (NOT RESUME). */
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unsigned long pt_base; /* VIRTUAL address of page directory. */
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unsigned long nr_pt_frames; /* Number of bootstrap p.t. frames. */
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unsigned long mfn_list; /* VIRTUAL address of page-frame list. */
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unsigned long mod_start; /* VIRTUAL address of pre-loaded module. */
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unsigned long mod_len; /* Size (bytes) of pre-loaded module. */
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int8_t cmd_line[MAX_GUEST_CMDLINE];
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/* The pfn range here covers both page table and p->m table frames. */
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unsigned long first_p2m_pfn;/* 1st pfn forming initial P->M table. */
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unsigned long nr_p2m_frames;/* # of pfns forming initial P->M table. */
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};
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/* These flags are passed in the 'flags' field of start_info_t. */
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#define SIF_PRIVILEGED (1<<0) /* Is the domain privileged? */
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#define SIF_INITDOMAIN (1<<1) /* Is this the initial control domain? */
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#define SIF_MULTIBOOT_MOD (1<<2) /* Is mod_start a multiboot module? */
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#define SIF_MOD_START_PFN (1<<3) /* Is mod_start a PFN? */
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#define SIF_PM_MASK (0xFF<<8) /* reserve 1 byte for xen-pm options */
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/*
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* A multiboot module is a package containing modules very similar to a
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* multiboot module array. The only differences are:
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* - the array of module descriptors is by convention simply at the beginning
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* of the multiboot module,
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* - addresses in the module descriptors are based on the beginning of the
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* multiboot module,
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* - the number of modules is determined by a termination descriptor that has
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* mod_start == 0.
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*
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* This permits to both build it statically and reference it in a configuration
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* file, and let the PV guest easily rebase the addresses to virtual addresses
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* and at the same time count the number of modules.
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*/
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struct xen_multiboot_mod_list {
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/* Address of first byte of the module */
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uint32_t mod_start;
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/* Address of last byte of the module (inclusive) */
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uint32_t mod_end;
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/* Address of zero-terminated command line */
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uint32_t cmdline;
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/* Unused, must be zero */
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uint32_t pad;
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};
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/*
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* The console structure in start_info.console.dom0
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*
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* This structure includes a variety of information required to
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* have a working VGA/VESA console.
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*/
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struct dom0_vga_console_info {
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uint8_t video_type;
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#define XEN_VGATYPE_TEXT_MODE_3 0x03
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#define XEN_VGATYPE_VESA_LFB 0x23
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#define XEN_VGATYPE_EFI_LFB 0x70
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union {
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struct {
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/* Font height, in pixels. */
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uint16_t font_height;
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/* Cursor location (column, row). */
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uint16_t cursor_x, cursor_y;
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/* Number of rows and columns (dimensions in characters). */
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uint16_t rows, columns;
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} text_mode_3;
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struct {
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/* Width and height, in pixels. */
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uint16_t width, height;
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/* Bytes per scan line. */
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uint16_t bytes_per_line;
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/* Bits per pixel. */
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uint16_t bits_per_pixel;
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/* LFB physical address, and size (in units of 64kB). */
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uint32_t lfb_base;
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uint32_t lfb_size;
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/* RGB mask offsets and sizes, as defined by VBE 1.2+ */
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uint8_t red_pos, red_size;
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uint8_t green_pos, green_size;
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uint8_t blue_pos, blue_size;
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uint8_t rsvd_pos, rsvd_size;
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/* VESA capabilities (offset 0xa, VESA command 0x4f00). */
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uint32_t gbl_caps;
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/* Mode attributes (offset 0x0, VESA command 0x4f01). */
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uint16_t mode_attrs;
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} vesa_lfb;
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} u;
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};
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typedef uint64_t cpumap_t;
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typedef uint8_t xen_domain_handle_t[16];
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/* Turn a plain number into a C unsigned long constant. */
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#define __mk_unsigned_long(x) x ## UL
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#define mk_unsigned_long(x) __mk_unsigned_long(x)
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#define TMEM_SPEC_VERSION 1
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struct tmem_op {
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uint32_t cmd;
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int32_t pool_id;
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union {
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struct { /* for cmd == TMEM_NEW_POOL */
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uint64_t uuid[2];
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uint32_t flags;
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} new;
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struct {
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uint64_t oid[3];
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uint32_t index;
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uint32_t tmem_offset;
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uint32_t pfn_offset;
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uint32_t len;
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GUEST_HANDLE(void) gmfn; /* guest machine page frame */
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} gen;
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} u;
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};
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DEFINE_GUEST_HANDLE(u64);
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#else /* __ASSEMBLY__ */
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/* In assembly code we cannot use C numeric constant suffixes. */
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#define mk_unsigned_long(x) x
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#endif /* !__ASSEMBLY__ */
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#endif /* __XEN_PUBLIC_XEN_H__ */
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