258 lines
6.6 KiB
C
258 lines
6.6 KiB
C
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_2_H
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#define __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_2_H
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#include <linux/spinlock.h>
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#include <linux/clk/msm-clk-provider.h>
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#include <linux/clk/msm-clk.h>
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/*
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* Generic frequency-definition structs and macros
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*/
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/**
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* @freq_hz: output rate
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* @src_freq: source freq for dynamic pll. For fixed plls, set to 0.
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* @src_clk: source clock for freq_hz
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* @m_val: M value corresponding to freq_hz
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* @n_val: N value corresponding to freq_hz
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* @d_val: D value corresponding to freq_hz
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* @div_src_val: Pre divider value and source selection mux index for freq_hz
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* @sys_vdd: Voltage level required for freq_hz
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*/
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struct clk_freq_tbl {
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unsigned long freq_hz;
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unsigned long src_freq;
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struct clk *src_clk;
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u32 m_val;
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u32 n_val;
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u32 d_val;
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u32 div_src_val;
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const unsigned sys_vdd;
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};
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#define FREQ_END (ULONG_MAX-1)
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#define F_END { .freq_hz = FREQ_END }
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#define FIXED_CLK_SRC 0
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/*
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* Generic clock-definition struct and macros
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*/
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/**
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* struct rcg_clk - root clock generator
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* @cmd_rcgr_reg: command register
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* @set_rate: function to set frequency
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* @freq_tbl: frequency table for this RCG
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* @current_freq: current RCG frequency
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* @c: generic clock data
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* @non_local_children: set if RCG has at least one branch owned by a diff EE
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* @force_enable_rcgr: set if RCG needs to be force enabled/disabled during
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* power sequence
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* @base: pointer to base address of ioremapped registers.
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*/
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struct rcg_clk {
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u32 cmd_rcgr_reg;
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void (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
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struct clk_freq_tbl *freq_tbl;
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struct clk_freq_tbl *current_freq;
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struct clk c;
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bool non_local_children;
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bool force_enable_rcgr;
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void *const __iomem *base;
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};
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static inline struct rcg_clk *to_rcg_clk(struct clk *clk)
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{
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return container_of(clk, struct rcg_clk, c);
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}
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extern struct clk_freq_tbl rcg_dummy_freq;
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/**
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* struct branch_clk - branch clock
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* @set_rate: Set the frequency of this branch clock.
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* @c: clk
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* @cbcr_reg: branch control register
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* @bcr_reg: block reset register
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* @has_sibling: true if other branches are derived from this branch's source
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* @cur_div: current branch divider value
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* @max_div: maximum branch divider value (if zero, no divider exists)
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* @halt_check: halt checking type
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* @toggle_memory: toggle memory during enable/disable if true
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* @no_halt_check_on_disable: When set, do not check status bit during
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* clk_disable().
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* @check_enable_bit: Check the enable bit to determine clock status
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during handoff.
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* @base: pointer to base address of ioremapped registers.
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*/
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struct branch_clk {
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void (*set_rate)(struct branch_clk *, struct clk_freq_tbl *);
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struct clk c;
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u32 cbcr_reg;
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u32 bcr_reg;
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int has_sibling;
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u32 cur_div;
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u32 max_div;
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const u32 halt_check;
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bool toggle_memory;
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bool no_halt_check_on_disable;
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bool check_enable_bit;
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void *const __iomem *base;
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};
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static inline struct branch_clk *to_branch_clk(struct clk *clk)
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{
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return container_of(clk, struct branch_clk, c);
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}
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/**
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* struct local_vote_clk - Voteable branch clock
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* @c: clk
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* @cbcr_reg: branch control register
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* @vote_reg: voting register
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* @en_mask: enable mask
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* @halt_check: halt checking type
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* @base: pointer to base address of ioremapped registers.
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* An on/off switch with a rate derived from the parent.
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*/
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struct local_vote_clk {
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struct clk c;
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u32 cbcr_reg;
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u32 vote_reg;
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u32 bcr_reg;
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u32 en_mask;
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const u32 halt_check;
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void * __iomem *base;
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};
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static inline struct local_vote_clk *to_local_vote_clk(struct clk *clk)
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{
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return container_of(clk, struct local_vote_clk, c);
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}
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/**
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* struct reset_clk - Reset clock
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* @c: clk
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* @reset_reg: block reset register
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* @base: pointer to base address of ioremapped registers.
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*/
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struct reset_clk {
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struct clk c;
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u32 reset_reg;
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void *__iomem *base;
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};
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static inline struct reset_clk *to_reset_clk(struct clk *clk)
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{
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return container_of(clk, struct reset_clk, c);
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}
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/**
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* struct measure_clk - for rate measurement debug use
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* @sample_ticks: sample period in reference clock ticks
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* @multiplier: measurement scale-up factor
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* @divider: measurement scale-down factor
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* @c: clk
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*/
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struct measure_clk {
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u64 sample_ticks;
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u32 multiplier;
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u32 divider;
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struct clk c;
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};
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struct measure_clk_data {
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struct clk *cxo;
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u32 plltest_reg;
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u32 plltest_val;
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u32 xo_div4_cbcr;
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u32 ctl_reg;
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u32 status_reg;
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void *const __iomem *base;
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};
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static inline struct measure_clk *to_measure_clk(struct clk *clk)
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{
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return container_of(clk, struct measure_clk, c);
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}
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/**
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* struct gate_clk
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* @c: clk
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* @en_mask: ORed with @en_reg to enable gate clk
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* @en_reg: register used to enable/disable gate clk
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* @base: pointer to base address of ioremapped registers
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*/
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struct gate_clk {
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struct clk c;
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u32 en_mask;
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u32 en_reg;
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unsigned int delay_us;
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void *const __iomem *base;
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};
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static inline struct gate_clk *to_gate_clk(struct clk *clk)
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{
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return container_of(clk, struct gate_clk, c);
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}
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/*
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* Generic set-rate implementations
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*/
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void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
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void set_rate_hid(struct rcg_clk *clk, struct clk_freq_tbl *nf);
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/*
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* Variables from the clock-local driver
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*/
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extern spinlock_t local_clock_reg_lock;
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extern struct clk_ops clk_ops_empty;
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extern struct clk_ops clk_ops_rcg;
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extern struct clk_ops clk_ops_rcg_mnd;
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extern struct clk_ops clk_ops_branch;
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extern struct clk_ops clk_ops_vote;
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extern struct clk_ops clk_ops_rcg_hdmi;
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extern struct clk_ops clk_ops_rcg_edp;
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extern struct clk_ops clk_ops_byte;
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extern struct clk_ops clk_ops_pixel;
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extern struct clk_ops clk_ops_byte_multiparent;
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extern struct clk_ops clk_ops_pixel_multiparent;
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extern struct clk_ops clk_ops_edppixel;
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extern struct clk_ops clk_ops_gate;
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extern struct clk_ops clk_ops_rst;
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extern struct clk_mux_ops mux_reg_ops;
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extern struct mux_div_ops rcg_mux_div_ops;
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extern struct clk_div_ops postdiv_reg_ops;
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enum handoff pixel_rcg_handoff(struct clk *clk);
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enum handoff byte_rcg_handoff(struct clk *clk);
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unsigned long measure_get_rate(struct clk *c);
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/*
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* Clock definition macros
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*/
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#define DEFINE_CLK_MEASURE(name) \
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struct clk name = { \
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.ops = &clk_ops_empty, \
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.dbg_name = #name, \
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CLK_INIT(name), \
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}; \
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#endif /* __ARCH_ARM_MACH_MSM_CLOCK_LOCAL_2_H */
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