163 lines
3.9 KiB
C
163 lines
3.9 KiB
C
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/* Copyright (c) 2007-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/interrupt.h>
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#include "mdss_mdp.h"
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struct mdss_hw *mdss_irq_handlers[MDSS_MAX_HW_BLK];
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static DEFINE_SPINLOCK(mdss_lock);
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int mdss_register_irq(struct mdss_hw *hw)
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{
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unsigned long irq_flags;
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u32 ndx_bit;
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if (!hw || hw->hw_ndx >= MDSS_MAX_HW_BLK)
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return -EINVAL;
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ndx_bit = BIT(hw->hw_ndx);
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spin_lock_irqsave(&mdss_lock, irq_flags);
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if (!mdss_irq_handlers[hw->hw_ndx])
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mdss_irq_handlers[hw->hw_ndx] = hw;
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else
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pr_err("panel %d's irq at %p is already registered\n",
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hw->hw_ndx, hw->irq_handler);
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spin_unlock_irqrestore(&mdss_lock, irq_flags);
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return 0;
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}
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void mdss_enable_irq(struct mdss_hw *hw)
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{
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unsigned long irq_flags;
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u32 ndx_bit;
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if (hw->hw_ndx >= MDSS_MAX_HW_BLK)
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return;
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if (!mdss_irq_handlers[hw->hw_ndx]) {
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pr_err("failed. First register the irq then enable it.\n");
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return;
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}
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ndx_bit = BIT(hw->hw_ndx);
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pr_debug("Enable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx,
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hw->irq_info->irq_ena, hw->irq_info->irq_mask);
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spin_lock_irqsave(&mdss_lock, irq_flags);
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if (hw->irq_info->irq_mask & ndx_bit) {
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pr_debug("MDSS HW ndx=%d is already set, mask=%x\n",
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hw->hw_ndx, hw->irq_info->irq_mask);
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} else {
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hw->irq_info->irq_mask |= ndx_bit;
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if (!hw->irq_info->irq_ena) {
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hw->irq_info->irq_ena = true;
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enable_irq(hw->irq_info->irq);
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}
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}
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spin_unlock_irqrestore(&mdss_lock, irq_flags);
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}
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void mdss_disable_irq(struct mdss_hw *hw)
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{
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unsigned long irq_flags;
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u32 ndx_bit;
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if (hw->hw_ndx >= MDSS_MAX_HW_BLK)
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return;
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ndx_bit = BIT(hw->hw_ndx);
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pr_debug("Disable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx,
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hw->irq_info->irq_ena, hw->irq_info->irq_mask);
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spin_lock_irqsave(&mdss_lock, irq_flags);
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if (!(hw->irq_info->irq_mask & ndx_bit)) {
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pr_warn("MDSS HW ndx=%d is NOT set\n", hw->hw_ndx);
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} else {
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hw->irq_info->irq_mask &= ~ndx_bit;
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if (hw->irq_info->irq_mask == 0) {
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hw->irq_info->irq_ena = false;
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disable_irq_nosync(hw->irq_info->irq);
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}
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}
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spin_unlock_irqrestore(&mdss_lock, irq_flags);
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}
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/* called from interrupt context */
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void mdss_disable_irq_nosync(struct mdss_hw *hw)
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{
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u32 ndx_bit;
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if (hw->hw_ndx >= MDSS_MAX_HW_BLK)
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return;
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ndx_bit = BIT(hw->hw_ndx);
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pr_debug("Disable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx,
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hw->irq_info->irq_ena, hw->irq_info->irq_mask);
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spin_lock(&mdss_lock);
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if (!(hw->irq_info->irq_mask & ndx_bit)) {
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pr_warn("MDSS HW ndx=%d is NOT set\n", hw->hw_ndx);
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} else {
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hw->irq_info->irq_mask &= ~ndx_bit;
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if (hw->irq_info->irq_mask == 0) {
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hw->irq_info->irq_ena = false;
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disable_irq_nosync(hw->irq_info->irq);
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}
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}
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spin_unlock(&mdss_lock);
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}
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int mdss_irq_dispatch(u32 hw_ndx, int irq, void *ptr)
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{
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struct mdss_hw *hw;
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int rc = -ENODEV;
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spin_lock(&mdss_lock);
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hw = mdss_irq_handlers[hw_ndx];
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spin_unlock(&mdss_lock);
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if (hw)
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rc = hw->irq_handler(irq, hw->ptr);
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return rc;
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}
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struct mdss_util_intf mdss_util = {
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.register_irq = mdss_register_irq,
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.enable_irq = mdss_enable_irq,
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.disable_irq = mdss_disable_irq,
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.disable_irq_nosync = mdss_disable_irq_nosync,
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.irq_dispatch = mdss_irq_dispatch,
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.get_iommu_domain = NULL,
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.iommu_attached = NULL,
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.iommu_ctrl = NULL,
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.bus_bandwidth_ctrl = NULL,
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.bus_scale_set_quota = NULL,
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.panel_intf_type = NULL,
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.panel_intf_status = NULL,
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.mdp_probe_done = false
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};
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struct mdss_util_intf *mdss_get_util_intf()
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{
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return &mdss_util;
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}
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EXPORT_SYMBOL(mdss_get_util_intf);
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