209 lines
5.0 KiB
C
209 lines
5.0 KiB
C
/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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* Copyright (C) 2007 Google Incorporated
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDP3_H
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#define MDP3_H
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#include <linux/types.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/msm_iommu_domains.h>
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#include "mdp3_dma.h"
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#include "mdss_fb.h"
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#include "mdss.h"
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#define MDP_VSYNC_CLK_RATE 19200000
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#define MDP_CORE_CLK_RATE_SVS 150000000
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#define MDP_CORE_CLK_RATE_MAX 307200000
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/* PPP cant work at SVS for panel res above qHD */
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#define SVS_MAX_PIXEL (540 * 960)
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#define KOFF_TIMEOUT msecs_to_jiffies(84)
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enum {
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MDP3_CLK_AHB,
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MDP3_CLK_AXI,
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MDP3_CLK_MDP_SRC,
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MDP3_CLK_MDP_CORE,
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MDP3_CLK_VSYNC,
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MDP3_CLK_DSI,
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MDP3_MAX_CLK
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};
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enum {
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MDP3_BUS_HANDLE,
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MDP3_BUS_HANDLE_MAX,
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};
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enum {
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MDP3_IOMMU_DOMAIN_SECURE,
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MDP3_IOMMU_DOMAIN_UNSECURE,
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MDP3_IOMMU_DOMAIN_MAX,
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};
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enum {
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MDP3_IOMMU_CTX_MDP_0,
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MDP3_IOMMU_CTX_MDP_1,
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MDP3_IOMMU_CTX_MAX
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};
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/* Keep DSI entry in sync with mdss
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which is being used by DSI 6G */
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enum {
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MDP3_CLIENT_DMA_P,
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MDP3_CLIENT_DSI = 1,
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MDP3_CLIENT_PPP,
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MDP3_CLIENT_MAX,
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};
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struct mdp3_bus_handle_map {
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struct msm_bus_vectors *bus_vector;
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struct msm_bus_paths *usecases;
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struct msm_bus_scale_pdata *scale_pdata;
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int current_bus_idx;
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int ref_cnt;
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u64 restore_ab[MDP3_CLIENT_MAX];
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u64 restore_ib[MDP3_CLIENT_MAX];
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u64 ab[MDP3_CLIENT_MAX];
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u64 ib[MDP3_CLIENT_MAX];
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u32 handle;
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};
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struct mdp3_iommu_domain_map {
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u32 domain_type;
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char *client_name;
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struct msm_iova_partition partitions[1];
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int npartitions;
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int domain_idx;
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struct iommu_domain *domain;
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};
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struct mdp3_iommu_ctx_map {
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u32 ctx_type;
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struct mdp3_iommu_domain_map *domain;
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char *ctx_name;
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struct device *ctx;
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int attached;
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};
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#define MDP3_MAX_INTR 28
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struct mdp3_intr_cb {
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void (*cb)(int type, void *);
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void *data;
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};
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struct mdp3_hw_resource {
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struct platform_device *pdev;
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u32 mdp_rev;
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struct mutex res_mutex;
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struct clk *clocks[MDP3_MAX_CLK];
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int clock_ref_count[MDP3_MAX_CLK];
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unsigned long dma_core_clk_request;
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unsigned long ppp_core_clk_request;
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struct mdss_hw mdp3_hw;
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struct mdss_util_intf *mdss_util;
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char __iomem *mdp_base;
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size_t mdp_reg_size;
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struct mdp3_bus_handle_map *bus_handle;
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struct ion_client *ion_client;
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struct mdp3_iommu_domain_map *domains;
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struct mdp3_iommu_ctx_map *iommu_contexts;
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unsigned int iommu_ref_cnt;
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bool allow_iommu_update;
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struct ion_handle *ion_handle;
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struct mutex iommu_lock;
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struct mdp3_dma dma[MDP3_DMA_MAX];
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struct mdp3_intf intf[MDP3_DMA_OUTPUT_SEL_MAX];
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spinlock_t irq_lock;
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u32 irq_ref_count[MDP3_MAX_INTR];
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u32 irq_mask;
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int irq_ref_cnt;
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struct mdp3_intr_cb callbacks[MDP3_MAX_INTR];
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u32 underrun_cnt;
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int irq_registered;
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unsigned long splash_mem_addr;
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u32 splash_mem_size;
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struct mdss_panel_cfg pan_cfg;
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int clk_prepare_count;
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int cont_splash_en;
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bool batfet_required;
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struct regulator *batfet;
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struct regulator *vdd_cx;
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struct regulator *fs;
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bool fs_ena;
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};
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struct mdp3_img_data {
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dma_addr_t addr;
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u32 len;
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u32 flags;
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int p_need;
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struct file *srcp_file;
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struct ion_handle *srcp_ihdl;
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};
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extern struct mdp3_hw_resource *mdp3_res;
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struct mdp3_dma *mdp3_get_dma_pipe(int capability);
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struct mdp3_intf *mdp3_get_display_intf(int type);
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void mdp3_irq_enable(int type);
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void mdp3_irq_disable(int type);
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void mdp3_irq_disable_nosync(int type);
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int mdp3_set_intr_callback(u32 type, struct mdp3_intr_cb *cb);
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void mdp3_irq_register(void);
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void mdp3_irq_deregister(void);
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int mdp3_clk_set_rate(int clk_type, unsigned long clk_rate, int client);
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int mdp3_clk_enable(int enable, int dsi_clk);
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int mdp3_res_update(int enable, int dsi_clk, int client);
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int mdp3_bus_scale_set_quota(int client, u64 ab_quota, u64 ib_quota);
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int mdp3_put_img(struct mdp3_img_data *data);
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int mdp3_get_img(struct msmfb_data *img, struct mdp3_img_data *data);
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int mdp3_iommu_enable(void);
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int mdp3_iommu_disable(void);
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int mdp3_iommu_is_attached(void);
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void mdp3_free(struct msm_fb_data_type *mfd);
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int mdp3_parse_dt_splash(struct msm_fb_data_type *mfd);
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void mdp3_release_splash_memory(struct msm_fb_data_type *mfd);
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int mdp3_create_sysfs_link(struct device *dev);
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int mdp3_get_cont_spash_en(void);
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int mdp3_get_mdp_dsi_clk(void);
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int mdp3_put_mdp_dsi_clk(void);
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int mdp3_misr_set(struct mdp_misr *misr_req);
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int mdp3_misr_get(struct mdp_misr *misr_resp);
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void mdp3_enable_regulator(int enable);
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void mdp3_check_dsi_ctrl_status(struct work_struct *work,
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uint32_t interval);
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int mdp3_footswitch_ctrl(int enable);
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#define MDP3_REG_WRITE(addr, val) writel_relaxed(val, mdp3_res->mdp_base + addr)
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#define MDP3_REG_READ(addr) readl_relaxed(mdp3_res->mdp_base + addr)
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#endif /* MDP3_H */
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