284 lines
7.4 KiB
C
284 lines
7.4 KiB
C
/* drivers/serial/msm_serial_hs_hwreg.h
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*
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* Copyright (c) 2007-2009, 2012-2014,The Linux Foundation. All rights reserved.
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*
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* All source code in this file is licensed under the following license
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* except where indicated.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can find it at http://www.fsf.org
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*/
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#ifndef MSM_SERIAL_HS_HWREG_H
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#define MSM_SERIAL_HS_HWREG_H
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#define GSBI_CONTROL_ADDR 0x0
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#define GSBI_PROTOCOL_CODE_MASK 0x30
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#define GSBI_PROTOCOL_I2C_UART 0x60
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#define GSBI_PROTOCOL_UART 0x40
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#define GSBI_PROTOCOL_IDLE 0x0
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#define TCSR_ADM_1_A_CRCI_MUX_SEL 0x78
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#define TCSR_ADM_1_B_CRCI_MUX_SEL 0x7C
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#define ADM1_CRCI_GSBI6_RX_SEL 0x800
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#define ADM1_CRCI_GSBI6_TX_SEL 0x400
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#define MSM_ENABLE_UART_CLOCK TIOCPMGET
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#define MSM_DISABLE_UART_CLOCK TIOCPMPUT
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#define MSM_GET_UART_CLOCK_STATUS TIOCPMACT
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enum msm_hsl_regs {
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UARTDM_MR1,
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UARTDM_MR2,
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UARTDM_IMR,
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UARTDM_SR,
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UARTDM_CR,
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UARTDM_CSR,
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UARTDM_IPR,
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UARTDM_ISR,
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UARTDM_RX_TOTAL_SNAP,
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UARTDM_RFWR,
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UARTDM_TFWR,
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UARTDM_RF,
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UARTDM_TF,
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UARTDM_MISR,
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UARTDM_DMRX,
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UARTDM_NCF_TX,
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UARTDM_DMEN,
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UARTDM_BCR,
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UARTDM_TXFS,
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UARTDM_RXFS,
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UARTDM_LAST,
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};
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enum msm_hs_regs {
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UART_DM_MR1 = 0x0,
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UART_DM_MR2 = 0x4,
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UART_DM_IMR = 0xb0,
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UART_DM_SR = 0xa4,
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UART_DM_CR = 0xa8,
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UART_DM_CSR = 0xa0,
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UART_DM_IPR = 0x18,
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UART_DM_ISR = 0xb4,
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UART_DM_RX_TOTAL_SNAP = 0xbc,
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UART_DM_TFWR = 0x1c,
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UART_DM_RFWR = 0x20,
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UART_DM_RF = 0x140,
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UART_DM_TF = 0x100,
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UART_DM_MISR = 0xac,
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UART_DM_DMRX = 0x34,
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UART_DM_NCF_TX = 0x40,
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UART_DM_DMEN = 0x3c,
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UART_DM_TXFS = 0x4c,
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UART_DM_RXFS = 0x50,
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UART_DM_RX_TRANS_CTRL = 0xcc,
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UART_DM_BCR = 0xc8,
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};
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#define UARTDM_MR1_ADDR 0x0
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#define UARTDM_MR2_ADDR 0x4
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/* Backward Compatability Register for UARTDM Core v1.4 */
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#define UARTDM_BCR_ADDR 0xc8
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/*
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* UARTDM Core v1.4 STALE_IRQ_EMPTY bit defination
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* Stale interrupt will fire if bit is set when RX-FIFO is empty
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*/
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#define UARTDM_BCR_TX_BREAK_DISABLE 0x1
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#define UARTDM_BCR_STALE_IRQ_EMPTY 0x2
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#define UARTDM_BCR_RX_DMRX_LOW_EN 0x4
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#define UARTDM_BCR_RX_STAL_IRQ_DMRX_EQL 0x10
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#define UARTDM_BCR_RX_DMRX_1BYTE_RES_EN 0x20
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/* TRANSFER_CONTROL Register for UARTDM Core v1.4 */
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#define UARTDM_RX_TRANS_CTRL_ADDR 0xcc
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/* TRANSFER_CONTROL Register bits */
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#define RX_STALE_AUTO_RE_EN 0x1
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#define RX_TRANS_AUTO_RE_ACTIVATE 0x2
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#define RX_DMRX_CYCLIC_EN 0x4
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/* write only register */
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#define UARTDM_CSR_115200 0xFF
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#define UARTDM_CSR_57600 0xEE
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#define UARTDM_CSR_38400 0xDD
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#define UARTDM_CSR_28800 0xCC
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#define UARTDM_CSR_19200 0xBB
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#define UARTDM_CSR_14400 0xAA
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#define UARTDM_CSR_9600 0x99
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#define UARTDM_CSR_7200 0x88
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#define UARTDM_CSR_4800 0x77
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#define UARTDM_CSR_3600 0x66
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#define UARTDM_CSR_2400 0x55
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#define UARTDM_CSR_1200 0x44
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#define UARTDM_CSR_600 0x33
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#define UARTDM_CSR_300 0x22
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#define UARTDM_CSR_150 0x11
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#define UARTDM_CSR_75 0x00
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/* write only register */
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#define UARTDM_IPR_ADDR 0x18
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#define UARTDM_TFWR_ADDR 0x1c
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#define UARTDM_RFWR_ADDR 0x20
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#define UARTDM_HCR_ADDR 0x24
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#define UARTDM_DMRX_ADDR 0x34
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#define UARTDM_DMEN_ADDR 0x3c
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/* UART_DM_NO_CHARS_FOR_TX */
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#define UARTDM_NCF_TX_ADDR 0x40
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#define UARTDM_BADR_ADDR 0x44
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#define UARTDM_SIM_CFG_ADDR 0x80
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/* Read Only register */
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#define UARTDM_TXFS_ADDR 0x4C
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#define UARTDM_RXFS_ADDR 0x50
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/* Register field Mask Mapping */
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#define UARTDM_SR_RX_BREAK_BMSK BIT(6)
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#define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
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#define UARTDM_SR_OVERRUN_BMSK BIT(4)
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#define UARTDM_SR_TXEMT_BMSK BIT(3)
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#define UARTDM_SR_TXRDY_BMSK BIT(2)
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#define UARTDM_SR_RXRDY_BMSK BIT(0)
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#define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
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#define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
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#define UARTDM_CR_TX_EN_BMSK BIT(2)
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#define UARTDM_CR_RX_EN_BMSK BIT(0)
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/* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
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#define RESET_RX 0x10
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#define RESET_TX 0x20
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#define RESET_ERROR_STATUS 0x30
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#define RESET_BREAK_INT 0x40
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#define START_BREAK 0x50
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#define STOP_BREAK 0x60
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#define RESET_CTS 0x70
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#define RESET_STALE_INT 0x80
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#define RFR_LOW 0xD0
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#define RFR_HIGH 0xE0
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#define CR_PROTECTION_EN 0x100
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#define STALE_EVENT_ENABLE 0x500
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#define STALE_EVENT_DISABLE 0x600
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#define FORCE_STALE_EVENT 0x400
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#define CLEAR_TX_READY 0x300
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#define RESET_TX_ERROR 0x800
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#define RESET_TX_DONE 0x810
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/*
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* UARTDM_CR BAM IFC comman bit value
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* for UARTDM Core v1.4
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*/
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#define START_RX_BAM_IFC 0x850
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#define START_TX_BAM_IFC 0x860
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#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
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#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
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#define UARTDM_MR1_CTS_CTL_BMSK 0x40
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#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
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/*
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* UARTDM Core v1.4 MR2_RFR_CTS_LOOP bitmask
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* Enables internal loopback between RFR_N of
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* RX channel and CTS_N of TX channel.
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*/
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#define UARTDM_MR2_RFR_CTS_LOOP_MODE_BMSK 0x400
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#define UARTDM_MR2_LOOP_MODE_BMSK 0x80
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#define UARTDM_MR2_ERROR_MODE_BMSK 0x40
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#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
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#define UARTDM_MR2_RX_ZERO_CHAR_OFF 0x100
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#define UARTDM_MR2_RX_ERROR_CHAR_OFF 0x200
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#define UARTDM_MR2_RX_BREAK_ZERO_CHAR_OFF 0x100
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#define UARTDM_MR2_BITS_PER_CHAR_8 (0x3 << 4)
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/* bits per character configuration */
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#define FIVE_BPC (0 << 4)
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#define SIX_BPC (1 << 4)
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#define SEVEN_BPC (2 << 4)
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#define EIGHT_BPC (3 << 4)
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#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
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#define STOP_BIT_ONE (1 << 2)
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#define STOP_BIT_TWO (3 << 2)
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#define UARTDM_MR2_PARITY_MODE_BMSK 0x3
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/* Parity configuration */
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#define NO_PARITY 0x0
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#define EVEN_PARITY 0x2
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#define ODD_PARITY 0x1
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#define SPACE_PARITY 0x3
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#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
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#define UARTDM_IPR_STALE_LSB_BMSK 0x1f
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/* These can be used for both ISR and IMR register */
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#define UARTDM_ISR_TX_READY_BMSK BIT(7)
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#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
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#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
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#define UARTDM_ISR_RXLEV_BMSK BIT(4)
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#define UARTDM_ISR_RXSTALE_BMSK BIT(3)
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#define UARTDM_ISR_RXBREAK_BMSK BIT(2)
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#define UARTDM_ISR_RXHUNT_BMSK BIT(1)
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#define UARTDM_ISR_TXLEV_BMSK BIT(0)
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/* Field definitions for UART_DM_DMEN*/
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#define UARTDM_TX_DM_EN_BMSK 0x1
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#define UARTDM_RX_DM_EN_BMSK 0x2
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/*
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* UARTDM Core v1.4 bitmask
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* Bitmasks for enabling Rx and Tx BAM Interface
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*/
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#define UARTDM_TX_BAM_ENABLE_BMSK 0x4
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#define UARTDM_RX_BAM_ENABLE_BMSK 0x8
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/* Register offsets for UART Core v13 */
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/* write only register */
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#define UARTDM_CSR_ADDR 0x8
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/* write only register */
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#define UARTDM_TF_ADDR 0x70
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#define UARTDM_TF2_ADDR 0x74
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#define UARTDM_TF3_ADDR 0x78
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#define UARTDM_TF4_ADDR 0x7c
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/* write only register */
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#define UARTDM_CR_ADDR 0x10
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/* write only register */
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#define UARTDM_IMR_ADDR 0x14
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#define UARTDM_IRDA_ADDR 0x38
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/* Read Only register */
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#define UARTDM_SR_ADDR 0x8
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/* Read Only register */
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#define UARTDM_RF_ADDR 0x70
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#define UARTDM_RF2_ADDR 0x74
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#define UARTDM_RF3_ADDR 0x78
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#define UARTDM_RF4_ADDR 0x7c
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/* Read Only register */
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#define UARTDM_MISR_ADDR 0x10
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/* Read Only register */
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#define UARTDM_ISR_ADDR 0x14
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#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
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#endif /* MSM_SERIAL_HS_HWREG_H */
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