236 lines
6.3 KiB
C
236 lines
6.3 KiB
C
/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2014 QLogic Corporation
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*
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* See LICENSE.qla2xxx for copyright and licensing details.
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*/
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#ifndef __QLA_BSG_H
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#define __QLA_BSG_H
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/* BSG Vendor specific commands */
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#define QL_VND_LOOPBACK 0x01
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#define QL_VND_A84_RESET 0x02
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#define QL_VND_A84_UPDATE_FW 0x03
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#define QL_VND_A84_MGMT_CMD 0x04
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#define QL_VND_IIDMA 0x05
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#define QL_VND_FCP_PRIO_CFG_CMD 0x06
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#define QL_VND_READ_FLASH 0x07
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#define QL_VND_UPDATE_FLASH 0x08
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#define QL_VND_SET_FRU_VERSION 0x0B
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#define QL_VND_READ_FRU_STATUS 0x0C
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#define QL_VND_WRITE_FRU_STATUS 0x0D
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#define QL_VND_DIAG_IO_CMD 0x0A
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#define QL_VND_WRITE_I2C 0x10
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#define QL_VND_READ_I2C 0x11
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#define QL_VND_FX00_MGMT_CMD 0x12
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#define QL_VND_SERDES_OP 0x13
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#define QL_VND_SERDES_OP_EX 0x14
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/* BSG Vendor specific subcode returns */
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#define EXT_STATUS_OK 0
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#define EXT_STATUS_ERR 1
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#define EXT_STATUS_BUSY 2
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#define EXT_STATUS_INVALID_PARAM 6
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#define EXT_STATUS_DATA_OVERRUN 7
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#define EXT_STATUS_DATA_UNDERRUN 8
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#define EXT_STATUS_MAILBOX 11
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#define EXT_STATUS_NO_MEMORY 17
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#define EXT_STATUS_DEVICE_OFFLINE 22
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/*
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* To support bidirectional iocb
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* BSG Vendor specific returns
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*/
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#define EXT_STATUS_NOT_SUPPORTED 27
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#define EXT_STATUS_INVALID_CFG 28
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#define EXT_STATUS_DMA_ERR 29
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#define EXT_STATUS_TIMEOUT 30
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#define EXT_STATUS_THREAD_FAILED 31
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#define EXT_STATUS_DATA_CMP_FAILED 32
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/* BSG definations for interpreting CommandSent field */
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#define INT_DEF_LB_LOOPBACK_CMD 0
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#define INT_DEF_LB_ECHO_CMD 1
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/* Loopback related definations */
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#define INTERNAL_LOOPBACK 0xF1
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#define EXTERNAL_LOOPBACK 0xF2
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#define ENABLE_INTERNAL_LOOPBACK 0x02
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#define ENABLE_EXTERNAL_LOOPBACK 0x04
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#define INTERNAL_LOOPBACK_MASK 0x000E
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#define MAX_ELS_FRAME_PAYLOAD 252
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#define ELS_OPCODE_BYTE 0x10
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/* BSG Vendor specific definations */
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#define A84_ISSUE_WRITE_TYPE_CMD 0
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#define A84_ISSUE_READ_TYPE_CMD 1
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#define A84_CLEANUP_CMD 2
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#define A84_ISSUE_RESET_OP_FW 3
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#define A84_ISSUE_RESET_DIAG_FW 4
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#define A84_ISSUE_UPDATE_OPFW_CMD 5
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#define A84_ISSUE_UPDATE_DIAGFW_CMD 6
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struct qla84_mgmt_param {
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union {
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struct {
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uint32_t start_addr;
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} mem; /* for QLA84_MGMT_READ/WRITE_MEM */
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struct {
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uint32_t id;
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#define QLA84_MGMT_CONFIG_ID_UIF 1
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#define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
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#define QLA84_MGMT_CONFIG_ID_PAUSE 3
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#define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
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uint32_t param0;
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uint32_t param1;
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} config; /* for QLA84_MGMT_CHNG_CONFIG */
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struct {
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uint32_t type;
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#define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1 /* Get Config Log Data */
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#define QLA84_MGMT_INFO_LOG_DATA 2 /* Get Log Data */
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#define QLA84_MGMT_INFO_PORT_STAT 3 /* Get Port Statistics */
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#define QLA84_MGMT_INFO_LIF_STAT 4 /* Get LIF Statistics */
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#define QLA84_MGMT_INFO_ASIC_STAT 5 /* Get ASIC Statistics */
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#define QLA84_MGMT_INFO_CONFIG_PARAMS 6 /* Get Config Parameters */
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#define QLA84_MGMT_INFO_PANIC_LOG 7 /* Get Panic Log */
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uint32_t context;
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/*
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* context definitions for QLA84_MGMT_INFO_CONFIG_LOG_DATA
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*/
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#define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
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#define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
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#define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
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#define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
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#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
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#define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
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#define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
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#define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
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#define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
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#define IC_LOG_DATA_LOG_ID_DCX_LOG 9
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/*
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* context definitions for QLA84_MGMT_INFO_PORT_STAT
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*/
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#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
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#define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
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#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
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#define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
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#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
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#define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
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/*
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* context definitions for QLA84_MGMT_INFO_LIF_STAT
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*/
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#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
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#define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
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#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
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#define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
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#define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
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} info; /* for QLA84_MGMT_GET_INFO */
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} u;
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};
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struct qla84_msg_mgmt {
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uint16_t cmd;
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#define QLA84_MGMT_READ_MEM 0x00
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#define QLA84_MGMT_WRITE_MEM 0x01
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#define QLA84_MGMT_CHNG_CONFIG 0x02
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#define QLA84_MGMT_GET_INFO 0x03
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uint16_t rsrvd;
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struct qla84_mgmt_param mgmtp;/* parameters for cmd */
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uint32_t len; /* bytes in payload following this struct */
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uint8_t payload[0]; /* payload for cmd */
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};
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struct qla_bsg_a84_mgmt {
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struct qla84_msg_mgmt mgmt;
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} __attribute__ ((packed));
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struct qla_scsi_addr {
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uint16_t bus;
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uint16_t target;
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} __attribute__ ((packed));
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struct qla_ext_dest_addr {
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union {
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uint8_t wwnn[8];
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uint8_t wwpn[8];
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uint8_t id[4];
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struct qla_scsi_addr scsi_addr;
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} dest_addr;
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uint16_t dest_type;
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#define EXT_DEF_TYPE_WWPN 2
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uint16_t lun;
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uint16_t padding[2];
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} __attribute__ ((packed));
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struct qla_port_param {
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struct qla_ext_dest_addr fc_scsi_addr;
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uint16_t mode;
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uint16_t speed;
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} __attribute__ ((packed));
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/* FRU VPD */
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#define MAX_FRU_SIZE 36
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struct qla_field_address {
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uint16_t offset;
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uint16_t device;
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uint16_t option;
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} __packed;
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struct qla_field_info {
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uint8_t version[MAX_FRU_SIZE];
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} __packed;
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struct qla_image_version {
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struct qla_field_address field_address;
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struct qla_field_info field_info;
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} __packed;
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struct qla_image_version_list {
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uint32_t count;
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struct qla_image_version version[0];
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} __packed;
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struct qla_status_reg {
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struct qla_field_address field_address;
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uint8_t status_reg;
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uint8_t reserved[7];
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} __packed;
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struct qla_i2c_access {
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uint16_t device;
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uint16_t offset;
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uint16_t option;
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uint16_t length;
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uint8_t buffer[0x40];
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} __packed;
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/* 26xx serdes register interface */
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/* serdes reg commands */
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#define INT_SC_SERDES_READ_REG 1
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#define INT_SC_SERDES_WRITE_REG 2
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struct qla_serdes_reg {
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uint16_t cmd;
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uint16_t addr;
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uint16_t val;
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} __packed;
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struct qla_serdes_reg_ex {
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uint16_t cmd;
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uint32_t addr;
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uint32_t val;
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} __packed;
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#endif
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