202 lines
6.0 KiB
C
202 lines
6.0 KiB
C
/*******************************************************************************
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This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
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developing this code.
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This contains the functions to handle the dma.
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Copyright (C) 2007-2009 STMicroelectronics Ltd
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*******************************************************************************/
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#include <asm/io.h>
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#include "dwmac1000.h"
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#include "dwmac_dma.h"
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static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
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int burst_len, u32 dma_tx, u32 dma_rx, int atds)
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{
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u32 value = readl(ioaddr + DMA_BUS_MODE);
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int limit;
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/* DMA SW reset */
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value |= DMA_BUS_MODE_SFT_RESET;
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writel(value, ioaddr + DMA_BUS_MODE);
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limit = 10;
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while (limit--) {
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if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
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break;
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mdelay(10);
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}
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if (limit < 0)
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return -EBUSY;
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/*
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* Set the DMA PBL (Programmable Burst Length) mode
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* Before stmmac core 3.50 this mode bit was 4xPBL, and
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* post 3.5 mode bit acts as 8*PBL.
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* For core rev < 3.5, when the core is set for 4xPBL mode, the
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* DMA transfers the data in 4, 8, 16, 32, 64 & 128 beats
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* depending on pbl value.
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* For core rev > 3.5, when the core is set for 8xPBL mode, the
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* DMA transfers the data in 8, 16, 32, 64, 128 & 256 beats
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* depending on pbl value.
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*/
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value = DMA_BUS_MODE_PBL | ((pbl << DMA_BUS_MODE_PBL_SHIFT) |
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(pbl << DMA_BUS_MODE_RPBL_SHIFT));
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/* Set the Fixed burst mode */
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if (fb)
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value |= DMA_BUS_MODE_FB;
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/* Mixed Burst has no effect when fb is set */
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if (mb)
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value |= DMA_BUS_MODE_MB;
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#ifdef CONFIG_STMMAC_DA
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value |= DMA_BUS_MODE_DA; /* Rx has priority over tx */
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#endif
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if (atds)
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value |= DMA_BUS_MODE_ATDS;
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writel(value, ioaddr + DMA_BUS_MODE);
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/* In case of GMAC AXI configuration, program the DMA_AXI_BUS_MODE
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* for supported bursts.
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*
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* Note: This is applicable only for revision GMACv3.61a. For
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* older version this register is reserved and shall have no
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* effect.
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*
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* Note:
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* For Fixed Burst Mode: if we directly write 0xFF to this
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* register using the configurations pass from platform code,
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* this would ensure that all bursts supported by core are set
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* and those which are not supported would remain ineffective.
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*
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* For Non Fixed Burst Mode: provide the maximum value of the
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* burst length. Any burst equal or below the provided burst
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* length would be allowed to perform.
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*/
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writel(burst_len, ioaddr + DMA_AXI_BUS_MODE);
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/* Mask interrupts by writing to CSR7 */
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writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
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/* RX/TX descriptor base address lists must be written into
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* DMA CSR3 and CSR4, respectively
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*/
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writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
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writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
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return 0;
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}
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static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
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int rxmode)
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{
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u32 csr6 = readl(ioaddr + DMA_CONTROL);
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if (txmode == SF_DMA_MODE) {
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pr_debug("GMAC: enable TX store and forward mode\n");
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/* Transmit COE type 2 cannot be done in cut-through mode. */
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csr6 |= DMA_CONTROL_TSF;
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/* Operating on second frame increase the performance
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* especially when transmit store-and-forward is used.
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*/
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csr6 |= DMA_CONTROL_OSF;
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} else {
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pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode);
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csr6 &= ~DMA_CONTROL_TSF;
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csr6 &= DMA_CONTROL_TC_TX_MASK;
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/* Set the transmit threshold */
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if (txmode <= 32)
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csr6 |= DMA_CONTROL_TTC_32;
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else if (txmode <= 64)
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csr6 |= DMA_CONTROL_TTC_64;
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else if (txmode <= 128)
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csr6 |= DMA_CONTROL_TTC_128;
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else if (txmode <= 192)
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csr6 |= DMA_CONTROL_TTC_192;
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else
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csr6 |= DMA_CONTROL_TTC_256;
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}
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if (rxmode == SF_DMA_MODE) {
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pr_debug("GMAC: enable RX store and forward mode\n");
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csr6 |= DMA_CONTROL_RSF;
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} else {
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pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode);
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csr6 &= ~DMA_CONTROL_RSF;
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csr6 &= DMA_CONTROL_TC_RX_MASK;
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if (rxmode <= 32)
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csr6 |= DMA_CONTROL_RTC_32;
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else if (rxmode <= 64)
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csr6 |= DMA_CONTROL_RTC_64;
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else if (rxmode <= 96)
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csr6 |= DMA_CONTROL_RTC_96;
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else
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csr6 |= DMA_CONTROL_RTC_128;
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}
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writel(csr6, ioaddr + DMA_CONTROL);
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}
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static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)
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{
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int i;
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pr_info(" DMA registers\n");
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for (i = 0; i < 22; i++) {
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if ((i < 9) || (i > 17)) {
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int offset = i * 4;
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pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
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(DMA_BUS_MODE + offset),
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readl(ioaddr + DMA_BUS_MODE + offset));
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}
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}
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}
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static unsigned int dwmac1000_get_hw_feature(void __iomem *ioaddr)
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{
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return readl(ioaddr + DMA_HW_FEATURE);
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}
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static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt)
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{
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writel(riwt, ioaddr + DMA_RX_WATCHDOG);
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}
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const struct stmmac_dma_ops dwmac1000_dma_ops = {
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.init = dwmac1000_dma_init,
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.dump_regs = dwmac1000_dump_dma_regs,
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.dma_mode = dwmac1000_dma_operation_mode,
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.enable_dma_transmission = dwmac_enable_dma_transmission,
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.enable_dma_irq = dwmac_enable_dma_irq,
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.disable_dma_irq = dwmac_disable_dma_irq,
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.start_tx = dwmac_dma_start_tx,
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.stop_tx = dwmac_dma_stop_tx,
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.start_rx = dwmac_dma_start_rx,
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.stop_rx = dwmac_dma_stop_rx,
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.dma_interrupt = dwmac_dma_interrupt,
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.get_hw_feature = dwmac1000_get_hw_feature,
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.rx_watchdog = dwmac1000_rx_watchdog,
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};
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