592 lines
14 KiB
C
592 lines
14 KiB
C
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* MSM EMAC PHY Controller driver.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_net.h>
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#include <linux/pm_runtime.h>
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#include <linux/phy.h>
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#include "emac.h"
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#include "emac_hw.h"
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#include "emac_defines.h"
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#include "emac_regs.h"
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#include "emac_phy.h"
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#include "emac_rgmii.h"
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#include "emac_sgmii_v1.h"
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static int emac_disable_mdio_autopoll(struct emac_hw *hw)
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{
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u32 i, val;
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emac_reg_update32(hw, EMAC, EMAC_MDIO_CTRL, MDIO_AP_EN, 0);
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wmb(); /* ensure mdio autopoll disable is requested */
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/* wait for any mdio polling to complete */
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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val = emac_reg_r32(hw, EMAC, EMAC_MDIO_CTRL);
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if (!(val & MDIO_BUSY))
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return 0;
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udelay(10); /* atomic context */
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}
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/* failed to disable; ensure it is enabled before returning */
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emac_reg_update32(hw, EMAC, EMAC_MDIO_CTRL, 0, MDIO_AP_EN);
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wmb(); /* ensure mdio autopoll is enabled */
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return -EBUSY;
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}
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static void emac_enable_mdio_autopoll(struct emac_hw *hw)
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{
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emac_reg_update32(hw, EMAC, EMAC_MDIO_CTRL, 0, MDIO_AP_EN);
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wmb(); /* ensure mdio autopoll is enabled */
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}
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int emac_hw_read_phy_reg(struct emac_adapter *adpt, bool ext, u8 dev, bool fast,
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u16 reg_addr, u16 *phy_data)
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{
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struct emac_phy *phy = &adpt->phy;
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struct emac_hw *hw = &adpt->hw;
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u32 i, clk_sel, val = 0;
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int retval = 0;
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*phy_data = 0;
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clk_sel = fast ? MDIO_CLK_25_4 : MDIO_CLK_25_28;
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if (phy->external) {
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retval = emac_disable_mdio_autopoll(hw);
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if (retval)
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return retval;
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}
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emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK,
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(dev << PHY_ADDR_SHFT));
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wmb(); /* ensure PHY address is set before we proceed */
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if (ext) {
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val = ((dev << DEVAD_SHFT) & DEVAD_BMSK) |
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((reg_addr << EX_REG_ADDR_SHFT) & EX_REG_ADDR_BMSK);
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emac_reg_w32(hw, EMAC, EMAC_MDIO_EX_CTRL, val);
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wmb(); /* ensure proper address is set before proceeding */
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val = SUP_PREAMBLE |
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((clk_sel << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) |
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MDIO_START | MDIO_MODE | MDIO_RD_NWR;
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} else {
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val = val & ~(MDIO_REG_ADDR_BMSK | MDIO_CLK_SEL_BMSK |
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MDIO_MODE | MDIO_PR);
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val = SUP_PREAMBLE |
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((clk_sel << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) |
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((reg_addr << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) |
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MDIO_START | MDIO_RD_NWR;
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}
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emac_reg_w32(hw, EMAC, EMAC_MDIO_CTRL, val);
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mb(); /* ensure hw starts the operation before we check for result */
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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val = emac_reg_r32(hw, EMAC, EMAC_MDIO_CTRL);
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if (!(val & (MDIO_START | MDIO_BUSY))) {
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*phy_data = (u16)((val >> MDIO_DATA_SHFT) &
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MDIO_DATA_BMSK);
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break;
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}
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udelay(10); /* atomic context */
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}
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if (i == MDIO_WAIT_TIMES)
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retval = -EIO;
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if (phy->external)
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emac_enable_mdio_autopoll(hw);
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return retval;
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}
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int emac_hw_write_phy_reg(struct emac_adapter *adpt, bool ext, u8 dev,
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bool fast, u16 reg_addr, u16 phy_data)
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{
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struct emac_phy *phy = &adpt->phy;
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struct emac_hw *hw = &adpt->hw;
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u32 i, clk_sel, val = 0;
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int retval = 0;
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clk_sel = fast ? MDIO_CLK_25_4 : MDIO_CLK_25_28;
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if (phy->external) {
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retval = emac_disable_mdio_autopoll(hw);
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if (retval)
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return retval;
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}
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emac_reg_update32(hw, EMAC, EMAC_PHY_STS, PHY_ADDR_BMSK,
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(dev << PHY_ADDR_SHFT));
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wmb(); /* ensure PHY address is set before we proceed */
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if (ext) {
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val = ((dev << DEVAD_SHFT) & DEVAD_BMSK) |
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((reg_addr << EX_REG_ADDR_SHFT) & EX_REG_ADDR_BMSK);
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emac_reg_w32(hw, EMAC, EMAC_MDIO_EX_CTRL, val);
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wmb(); /* ensure proper address is set before proceeding */
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val = SUP_PREAMBLE |
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((clk_sel << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) |
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((phy_data << MDIO_DATA_SHFT) & MDIO_DATA_BMSK) |
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MDIO_START | MDIO_MODE;
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} else {
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val = val & ~(MDIO_REG_ADDR_BMSK | MDIO_CLK_SEL_BMSK |
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MDIO_DATA_BMSK | MDIO_MODE | MDIO_PR);
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val = SUP_PREAMBLE |
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((clk_sel << MDIO_CLK_SEL_SHFT) & MDIO_CLK_SEL_BMSK) |
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((reg_addr << MDIO_REG_ADDR_SHFT) & MDIO_REG_ADDR_BMSK) |
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((phy_data << MDIO_DATA_SHFT) & MDIO_DATA_BMSK) |
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MDIO_START;
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}
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emac_reg_w32(hw, EMAC, EMAC_MDIO_CTRL, val);
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mb(); /* ensure hw starts the operation before we check for result */
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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val = emac_reg_r32(hw, EMAC, EMAC_MDIO_CTRL);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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udelay(10); /* atomic context */
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}
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if (i == MDIO_WAIT_TIMES)
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retval = -EIO;
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if (phy->external)
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emac_enable_mdio_autopoll(hw);
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return retval;
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}
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int emac_phy_read(struct emac_adapter *adpt, u16 phy_addr, u16 reg_addr,
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u16 *phy_data)
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{
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struct emac_phy *phy = &adpt->phy;
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unsigned long flags;
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int retval;
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spin_lock_irqsave(&phy->lock, flags);
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retval = emac_hw_read_phy_reg(adpt, false, phy_addr, true, reg_addr,
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phy_data);
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spin_unlock_irqrestore(&phy->lock, flags);
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if (retval)
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emac_err(adpt, "error reading phy reg 0x%02x\n", reg_addr);
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else
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emac_dbg(adpt, hw, "EMAC PHY RD: 0x%02x -> 0x%04x\n", reg_addr,
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*phy_data);
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return retval;
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}
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int emac_phy_write(struct emac_adapter *adpt, u16 phy_addr, u16 reg_addr,
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u16 phy_data)
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{
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struct emac_phy *phy = &adpt->phy;
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unsigned long flags;
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int retval;
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spin_lock_irqsave(&phy->lock, flags);
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retval = emac_hw_write_phy_reg(adpt, false, phy_addr, true, reg_addr,
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phy_data);
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spin_unlock_irqrestore(&phy->lock, flags);
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if (retval)
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emac_err(adpt, "error writing phy reg 0x%02x\n", reg_addr);
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else
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emac_dbg(adpt, hw, "EMAC PHY WR: 0x%02x <- 0x%04x\n", reg_addr,
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phy_data);
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return retval;
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}
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/* reset external phy */
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void emac_phy_reset_external(struct emac_adapter *adpt)
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{
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/* Trigger ephy reset by pulling line low */
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adpt->gpio_off(adpt, false, true);
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/* need delay to complete ephy reset */
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usleep_range(10000, 20000);
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/* Complete ephy reset by pulling line back up */
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adpt->gpio_on(adpt, false, true);
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/* need delay to complete ephy reset */
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usleep_range(10000, 20000);
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}
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/* initialize external phy */
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int emac_phy_init_external(struct emac_adapter *adpt)
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{
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struct emac_phy *phy = &adpt->phy;
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struct emac_hw *hw = &adpt->hw;
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u16 phy_id[2];
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int retval = 0;
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if (phy->external) {
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emac_phy_reset_external(adpt);
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retval = emac_phy_read(adpt, phy->addr, MII_PHYSID1,
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&phy_id[0]);
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if (retval)
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return retval;
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retval = emac_phy_read(adpt, phy->addr, MII_PHYSID2,
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&phy_id[1]);
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if (retval)
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return retval;
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phy->id[0] = phy_id[0];
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phy->id[1] = phy_id[1];
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} else {
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emac_disable_mdio_autopoll(hw);
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}
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return phy->ops.init_ephy(adpt);
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}
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static int emac_hw_setup_phy_link(struct emac_adapter *adpt,
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enum emac_flow_ctrl req_fc_mode, u32 speed,
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bool autoneg, bool fc)
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{
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struct emac_phy *phy = &adpt->phy;
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u16 adv, bmcr, ctrl1000 = 0;
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int retval = 0;
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if (autoneg) {
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switch (req_fc_mode) {
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case EMAC_FC_FULL:
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case EMAC_FC_RX_PAUSE:
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adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
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break;
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case EMAC_FC_TX_PAUSE:
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adv = ADVERTISE_PAUSE_ASYM;
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break;
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default:
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adv = 0;
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break;
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}
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if (!fc)
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adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
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if (speed & EMAC_LINK_SPEED_10_HALF)
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adv |= ADVERTISE_10HALF;
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if (speed & EMAC_LINK_SPEED_10_FULL)
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adv |= ADVERTISE_10HALF | ADVERTISE_10FULL;
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if (speed & EMAC_LINK_SPEED_100_HALF)
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adv |= ADVERTISE_100HALF;
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if (speed & EMAC_LINK_SPEED_100_FULL)
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adv |= ADVERTISE_100HALF | ADVERTISE_100FULL;
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if (speed & EMAC_LINK_SPEED_1GB_FULL)
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ctrl1000 |= ADVERTISE_1000FULL;
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retval |= emac_phy_write(adpt, phy->addr, MII_ADVERTISE, adv);
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retval |= emac_phy_write(adpt, phy->addr, MII_CTRL1000,
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ctrl1000);
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bmcr = BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART;
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retval |= emac_phy_write(adpt, phy->addr, MII_BMCR, bmcr);
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} else {
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bmcr = BMCR_RESET;
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switch (speed) {
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case EMAC_LINK_SPEED_10_HALF:
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bmcr |= BMCR_SPEED10;
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break;
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case EMAC_LINK_SPEED_10_FULL:
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bmcr |= BMCR_SPEED10 | BMCR_FULLDPLX;
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break;
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case EMAC_LINK_SPEED_100_HALF:
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bmcr |= BMCR_SPEED100;
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break;
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case EMAC_LINK_SPEED_100_FULL:
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bmcr |= BMCR_SPEED100 | BMCR_FULLDPLX;
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break;
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case EMAC_LINK_SPEED_1GB_FULL:
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bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
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break;
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default:
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return -EINVAL;
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}
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retval |= emac_phy_write(adpt, phy->addr, MII_BMCR, bmcr);
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}
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return retval;
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}
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int emac_phy_setup_link(struct emac_adapter *adpt, u32 speed, bool autoneg,
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bool fc)
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{
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struct emac_phy *phy = &adpt->phy;
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int retval = 0;
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if (!phy->external)
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return phy->ops.link_setup_no_ephy(adpt, speed, autoneg);
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if (emac_hw_setup_phy_link(adpt, phy->req_fc_mode, speed, autoneg,
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fc)) {
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emac_err(adpt,
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"error on setup_phy(speed:%d autoneg:%d fc:%d)\n",
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speed, autoneg, fc);
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retval = -EINVAL;
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} else {
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phy->autoneg = autoneg;
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}
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return retval;
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}
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int emac_phy_setup_link_speed(struct emac_adapter *adpt, u32 speed,
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bool autoneg, bool fc)
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{
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struct emac_phy *phy = &adpt->phy;
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/* update speed based on input link speed */
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phy->autoneg_advertised = speed & EMAC_LINK_SPEED_DEFAULT;
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return emac_phy_setup_link(adpt, phy->autoneg_advertised, autoneg, fc);
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}
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int emac_phy_check_link(struct emac_adapter *adpt, u32 *speed, bool *link_up)
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{
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struct emac_phy *phy = &adpt->phy;
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u16 bmsr, pssr;
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int retval;
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if (!phy->external)
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return phy->ops.link_check_no_ephy(adpt, speed, link_up);
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retval = emac_phy_read(adpt, phy->addr, MII_BMSR, &bmsr);
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if (retval)
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return retval;
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if (!(bmsr & BMSR_LSTATUS)) {
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*link_up = false;
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*speed = EMAC_LINK_SPEED_UNKNOWN;
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return 0;
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}
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*link_up = true;
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retval = emac_phy_read(adpt, phy->addr, MII_PSSR, &pssr);
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if (retval)
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return retval;
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if (!(pssr & PSSR_SPD_DPLX_RESOLVED)) {
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emac_err(adpt, "error for speed duplex resolved\n");
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return -EINVAL;
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}
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switch (pssr & PSSR_SPEED) {
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case PSSR_1000MBS:
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if (pssr & PSSR_DPLX)
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*speed = EMAC_LINK_SPEED_1GB_FULL;
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else
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emac_err(adpt, "1000M half duplex is invalid");
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break;
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case PSSR_100MBS:
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if (pssr & PSSR_DPLX)
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*speed = EMAC_LINK_SPEED_100_FULL;
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else
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*speed = EMAC_LINK_SPEED_100_HALF;
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break;
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case PSSR_10MBS:
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if (pssr & PSSR_DPLX)
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*speed = EMAC_LINK_SPEED_10_FULL;
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else
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*speed = EMAC_LINK_SPEED_10_HALF;
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break;
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default:
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*speed = EMAC_LINK_SPEED_UNKNOWN;
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retval = -EINVAL;
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break;
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}
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return retval;
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}
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int emac_phy_get_lpa_speed(struct emac_adapter *adpt, u32 *speed)
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{
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struct emac_phy *phy = &adpt->phy;
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int retval;
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u16 lpa, stat1000;
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bool link;
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if (!phy->external)
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return phy->ops.link_check_no_ephy(adpt, speed, &link);
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retval = emac_phy_read(adpt, phy->addr, MII_LPA, &lpa);
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retval |= emac_phy_read(adpt, phy->addr, MII_STAT1000, &stat1000);
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if (retval)
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return retval;
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*speed = EMAC_LINK_SPEED_10_HALF;
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if (lpa & LPA_10FULL)
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*speed = EMAC_LINK_SPEED_10_FULL;
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else if (lpa & LPA_10HALF)
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*speed = EMAC_LINK_SPEED_10_HALF;
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else if (lpa & LPA_100FULL)
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*speed = EMAC_LINK_SPEED_100_FULL;
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else if (lpa & LPA_100HALF)
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*speed = EMAC_LINK_SPEED_100_HALF;
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else if (stat1000 & LPA_1000FULL)
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*speed = EMAC_LINK_SPEED_1GB_FULL;
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return 0;
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}
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/* read phy configuration and initialize it */
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int emac_phy_config(struct platform_device *pdev, struct emac_adapter *adpt)
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{
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struct emac_phy *phy = &adpt->phy;
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struct device_node *dt = pdev->dev.of_node;
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int ret;
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phy->external = !of_property_read_bool(dt, "qcom,no-external-phy");
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/* get phy address on MDIO bus */
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if (phy->external) {
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ret = of_property_read_u32(dt, "phy-addr", &phy->addr);
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if (ret)
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return ret;
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}
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/* get phy mode */
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ret = of_get_phy_mode(dt);
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if (ret < 0)
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return ret;
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phy->phy_mode = ret;
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/* sgmii v2 is always using ACPI */
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phy->ops = (phy->phy_mode == PHY_INTERFACE_MODE_RGMII) ?
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emac_rgmii_ops : emac_sgmii_v1_ops;
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if (!phy->external)
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phy->uses_gpios = false;
|
|
|
|
ret = phy->ops.config(pdev, adpt);
|
|
if (ret)
|
|
return ret;
|
|
|
|
spin_lock_init(&phy->lock);
|
|
|
|
phy->autoneg = true;
|
|
phy->autoneg_advertised = EMAC_LINK_SPEED_DEFAULT;
|
|
|
|
return phy->ops.init(adpt);
|
|
}
|
|
|
|
/* Flow Control (fc) */
|
|
static int emac_get_fc_mode(struct emac_adapter *adpt,
|
|
enum emac_flow_ctrl *mode)
|
|
{
|
|
struct emac_phy *phy = &adpt->phy;
|
|
u16 i, bmsr = 0, pssr = 0;
|
|
int retval = 0;
|
|
|
|
for (i = 0; i < EMAC_MAX_SETUP_LNK_CYCLE; i++) {
|
|
retval = emac_phy_read(adpt, phy->addr, MII_BMSR, &bmsr);
|
|
if (retval)
|
|
return retval;
|
|
|
|
if (bmsr & BMSR_LSTATUS) {
|
|
retval = emac_phy_read(adpt, phy->addr, MII_PSSR,
|
|
&pssr);
|
|
if (retval)
|
|
return retval;
|
|
|
|
if (!(pssr & PSSR_SPD_DPLX_RESOLVED)) {
|
|
emac_err(adpt,
|
|
"error for speed duplex resolved\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((pssr & PSSR_FC_TXEN) &&
|
|
(pssr & PSSR_FC_RXEN)) {
|
|
*mode = (phy->req_fc_mode == EMAC_FC_FULL) ?
|
|
EMAC_FC_FULL : EMAC_FC_RX_PAUSE;
|
|
} else if (pssr & PSSR_FC_TXEN) {
|
|
*mode = EMAC_FC_TX_PAUSE;
|
|
} else if (pssr & PSSR_FC_RXEN) {
|
|
*mode = EMAC_FC_RX_PAUSE;
|
|
} else {
|
|
*mode = EMAC_FC_NONE;
|
|
}
|
|
break;
|
|
}
|
|
msleep(100); /* link can take upto few seconds to come up */
|
|
}
|
|
|
|
if (i == EMAC_MAX_SETUP_LNK_CYCLE) {
|
|
emac_err(adpt, "error when get flow control mode\n");
|
|
retval = -EINVAL;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
int emac_phy_config_fc(struct emac_adapter *adpt)
|
|
{
|
|
struct emac_phy *phy = &adpt->phy;
|
|
struct emac_hw *hw = &adpt->hw;
|
|
u32 mac;
|
|
int retval;
|
|
|
|
if (phy->disable_fc_autoneg || !phy->external) {
|
|
phy->cur_fc_mode = phy->req_fc_mode;
|
|
} else {
|
|
retval = emac_get_fc_mode(adpt, &phy->cur_fc_mode);
|
|
if (retval)
|
|
return retval;
|
|
}
|
|
|
|
mac = emac_reg_r32(hw, EMAC, EMAC_MAC_CTRL);
|
|
|
|
switch (phy->cur_fc_mode) {
|
|
case EMAC_FC_NONE:
|
|
mac &= ~(RXFC | TXFC);
|
|
break;
|
|
case EMAC_FC_RX_PAUSE:
|
|
mac &= ~TXFC;
|
|
mac |= RXFC;
|
|
break;
|
|
case EMAC_FC_TX_PAUSE:
|
|
mac |= TXFC;
|
|
mac &= ~RXFC;
|
|
break;
|
|
case EMAC_FC_FULL:
|
|
case EMAC_FC_DEFAULT:
|
|
mac |= (TXFC | RXFC);
|
|
break;
|
|
default:
|
|
emac_err(adpt, "flow control param set incorrectly\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
emac_reg_w32(hw, EMAC, EMAC_MAC_CTRL, mac);
|
|
/* ensure flow control config is slushed to hw */
|
|
wmb();
|
|
return 0;
|
|
}
|
|
|
|
void emac_reg_write_all(void __iomem *base, const struct emac_reg_write *itr)
|
|
{
|
|
for (; itr->offset != END_MARKER; ++itr)
|
|
writel_relaxed(itr->val, base + itr->offset);
|
|
}
|