1264 lines
38 KiB
C
1264 lines
38 KiB
C
/*******************************************************************************
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Intel PRO/10GbE Linux driver
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Copyright(c) 1999 - 2008 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* ixgb_hw.c
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* Shared functions for accessing and configuring the adapter
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/pci_ids.h>
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#include "ixgb_hw.h"
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#include "ixgb_ids.h"
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#include <linux/etherdevice.h>
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/* Local function prototypes */
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static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
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static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
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static void ixgb_get_bus_info(struct ixgb_hw *hw);
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static bool ixgb_link_reset(struct ixgb_hw *hw);
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static void ixgb_optics_reset(struct ixgb_hw *hw);
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static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
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static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
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static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
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static void ixgb_clear_vfta(struct ixgb_hw *hw);
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static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
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static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
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u32 reg_address,
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u32 phy_address,
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u32 device_type);
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static bool ixgb_setup_fc(struct ixgb_hw *hw);
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static bool mac_addr_valid(u8 *mac_addr);
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static u32 ixgb_mac_reset(struct ixgb_hw *hw)
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{
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u32 ctrl_reg;
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ctrl_reg = IXGB_CTRL0_RST |
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IXGB_CTRL0_SDP3_DIR | /* All pins are Output=1 */
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IXGB_CTRL0_SDP2_DIR |
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IXGB_CTRL0_SDP1_DIR |
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IXGB_CTRL0_SDP0_DIR |
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IXGB_CTRL0_SDP3 | /* Initial value 1101 */
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IXGB_CTRL0_SDP2 |
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IXGB_CTRL0_SDP0;
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#ifdef HP_ZX1
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/* Workaround for 82597EX reset errata */
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IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
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#else
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IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
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#endif
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/* Delay a few ms just to allow the reset to complete */
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msleep(IXGB_DELAY_AFTER_RESET);
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ctrl_reg = IXGB_READ_REG(hw, CTRL0);
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#ifdef DBG
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/* Make sure the self-clearing global reset bit did self clear */
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ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
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#endif
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if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) {
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ctrl_reg = /* Enable interrupt from XFP and SerDes */
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IXGB_CTRL1_GPI0_EN |
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IXGB_CTRL1_SDP6_DIR |
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IXGB_CTRL1_SDP7_DIR |
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IXGB_CTRL1_SDP6 |
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IXGB_CTRL1_SDP7;
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IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
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ixgb_optics_reset_bcm(hw);
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}
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if (hw->phy_type == ixgb_phy_type_txn17401)
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ixgb_optics_reset(hw);
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return ctrl_reg;
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}
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/******************************************************************************
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* Reset the transmit and receive units; mask and clear all interrupts.
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*
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* hw - Struct containing variables accessed by shared code
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*****************************************************************************/
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bool
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ixgb_adapter_stop(struct ixgb_hw *hw)
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{
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u32 ctrl_reg;
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u32 icr_reg;
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ENTER();
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/* If we are stopped or resetting exit gracefully and wait to be
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* started again before accessing the hardware.
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*/
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if (hw->adapter_stopped) {
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pr_debug("Exiting because the adapter is already stopped!!!\n");
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return false;
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}
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/* Set the Adapter Stopped flag so other driver functions stop
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* touching the Hardware.
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*/
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hw->adapter_stopped = true;
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/* Clear interrupt mask to stop board from generating interrupts */
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pr_debug("Masking off all interrupts\n");
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IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
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/* Disable the Transmit and Receive units. Then delay to allow
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* any pending transactions to complete before we hit the MAC with
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* the global reset.
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*/
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IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
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IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
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IXGB_WRITE_FLUSH(hw);
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msleep(IXGB_DELAY_BEFORE_RESET);
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/* Issue a global reset to the MAC. This will reset the chip's
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* transmit, receive, DMA, and link units. It will not effect
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* the current PCI configuration. The global reset bit is self-
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* clearing, and should clear within a microsecond.
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*/
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pr_debug("Issuing a global reset to MAC\n");
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ctrl_reg = ixgb_mac_reset(hw);
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/* Clear interrupt mask to stop board from generating interrupts */
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pr_debug("Masking off all interrupts\n");
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IXGB_WRITE_REG(hw, IMC, 0xffffffff);
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/* Clear any pending interrupt events. */
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icr_reg = IXGB_READ_REG(hw, ICR);
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return ctrl_reg & IXGB_CTRL0_RST;
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}
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/******************************************************************************
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* Identifies the vendor of the optics module on the adapter. The SR adapters
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* support two different types of XPAK optics, so it is necessary to determine
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* which optics are present before applying any optics-specific workarounds.
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*
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* hw - Struct containing variables accessed by shared code.
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*
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* Returns: the vendor of the XPAK optics module.
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*****************************************************************************/
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static ixgb_xpak_vendor
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ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
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{
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u32 i;
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u16 vendor_name[5];
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ixgb_xpak_vendor xpak_vendor;
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ENTER();
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/* Read the first few bytes of the vendor string from the XPAK NVR
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* registers. These are standard XENPAK/XPAK registers, so all XPAK
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* devices should implement them. */
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for (i = 0; i < 5; i++) {
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vendor_name[i] = ixgb_read_phy_reg(hw,
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MDIO_PMA_PMD_XPAK_VENDOR_NAME
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+ i, IXGB_PHY_ADDRESS,
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MDIO_MMD_PMAPMD);
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}
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/* Determine the actual vendor */
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if (vendor_name[0] == 'I' &&
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vendor_name[1] == 'N' &&
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vendor_name[2] == 'T' &&
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vendor_name[3] == 'E' && vendor_name[4] == 'L') {
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xpak_vendor = ixgb_xpak_vendor_intel;
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} else {
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xpak_vendor = ixgb_xpak_vendor_infineon;
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}
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return xpak_vendor;
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}
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/******************************************************************************
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* Determine the physical layer module on the adapter.
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*
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* hw - Struct containing variables accessed by shared code. The device_id
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* field must be (correctly) populated before calling this routine.
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*
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* Returns: the phy type of the adapter.
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*****************************************************************************/
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static ixgb_phy_type
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ixgb_identify_phy(struct ixgb_hw *hw)
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{
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ixgb_phy_type phy_type;
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ixgb_xpak_vendor xpak_vendor;
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ENTER();
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/* Infer the transceiver/phy type from the device id */
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switch (hw->device_id) {
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case IXGB_DEVICE_ID_82597EX:
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pr_debug("Identified TXN17401 optics\n");
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phy_type = ixgb_phy_type_txn17401;
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break;
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case IXGB_DEVICE_ID_82597EX_SR:
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/* The SR adapters carry two different types of XPAK optics
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* modules; read the vendor identifier to determine the exact
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* type of optics. */
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xpak_vendor = ixgb_identify_xpak_vendor(hw);
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if (xpak_vendor == ixgb_xpak_vendor_intel) {
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pr_debug("Identified TXN17201 optics\n");
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phy_type = ixgb_phy_type_txn17201;
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} else {
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pr_debug("Identified G6005 optics\n");
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phy_type = ixgb_phy_type_g6005;
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}
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break;
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case IXGB_DEVICE_ID_82597EX_LR:
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pr_debug("Identified G6104 optics\n");
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phy_type = ixgb_phy_type_g6104;
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break;
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case IXGB_DEVICE_ID_82597EX_CX4:
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pr_debug("Identified CX4\n");
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xpak_vendor = ixgb_identify_xpak_vendor(hw);
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if (xpak_vendor == ixgb_xpak_vendor_intel) {
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pr_debug("Identified TXN17201 optics\n");
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phy_type = ixgb_phy_type_txn17201;
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} else {
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pr_debug("Identified G6005 optics\n");
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phy_type = ixgb_phy_type_g6005;
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}
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break;
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default:
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pr_debug("Unknown physical layer module\n");
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phy_type = ixgb_phy_type_unknown;
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break;
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}
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/* update phy type for sun specific board */
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if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN)
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phy_type = ixgb_phy_type_bcm;
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return phy_type;
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}
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/******************************************************************************
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* Performs basic configuration of the adapter.
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Resets the controller.
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* Reads and validates the EEPROM.
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* Initializes the receive address registers.
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* Initializes the multicast table.
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* Clears all on-chip counters.
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* Calls routine to setup flow control settings.
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* Leaves the transmit and receive units disabled and uninitialized.
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*
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* Returns:
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* true if successful,
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* false if unrecoverable problems were encountered.
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*****************************************************************************/
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bool
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ixgb_init_hw(struct ixgb_hw *hw)
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{
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u32 i;
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u32 ctrl_reg;
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bool status;
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ENTER();
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/* Issue a global reset to the MAC. This will reset the chip's
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* transmit, receive, DMA, and link units. It will not effect
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* the current PCI configuration. The global reset bit is self-
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* clearing, and should clear within a microsecond.
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*/
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pr_debug("Issuing a global reset to MAC\n");
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ctrl_reg = ixgb_mac_reset(hw);
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pr_debug("Issuing an EE reset to MAC\n");
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#ifdef HP_ZX1
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/* Workaround for 82597EX reset errata */
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IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
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#else
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IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
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#endif
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/* Delay a few ms just to allow the reset to complete */
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msleep(IXGB_DELAY_AFTER_EE_RESET);
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if (!ixgb_get_eeprom_data(hw))
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return false;
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/* Use the device id to determine the type of phy/transceiver. */
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hw->device_id = ixgb_get_ee_device_id(hw);
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hw->phy_type = ixgb_identify_phy(hw);
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/* Setup the receive addresses.
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* Receive Address Registers (RARs 0 - 15).
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*/
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ixgb_init_rx_addrs(hw);
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/*
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* Check that a valid MAC address has been set.
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* If it is not valid, we fail hardware init.
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*/
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if (!mac_addr_valid(hw->curr_mac_addr)) {
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pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
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return(false);
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}
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/* tell the routines in this file they can access hardware again */
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hw->adapter_stopped = false;
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/* Fill in the bus_info structure */
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ixgb_get_bus_info(hw);
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/* Zero out the Multicast HASH table */
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pr_debug("Zeroing the MTA\n");
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for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
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IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
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/* Zero out the VLAN Filter Table Array */
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ixgb_clear_vfta(hw);
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/* Zero all of the hardware counters */
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ixgb_clear_hw_cntrs(hw);
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/* Call a subroutine to setup flow control. */
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status = ixgb_setup_fc(hw);
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/* 82597EX errata: Call check-for-link in case lane deskew is locked */
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ixgb_check_for_link(hw);
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return status;
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}
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/******************************************************************************
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* Initializes receive address filters.
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*
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* hw - Struct containing variables accessed by shared code
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*
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* Places the MAC address in receive address register 0 and clears the rest
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* of the receive address registers. Clears the multicast table. Assumes
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* the receiver is in reset when the routine is called.
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*****************************************************************************/
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static void
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ixgb_init_rx_addrs(struct ixgb_hw *hw)
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{
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u32 i;
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ENTER();
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/*
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* If the current mac address is valid, assume it is a software override
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* to the permanent address.
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* Otherwise, use the permanent address from the eeprom.
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*/
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if (!mac_addr_valid(hw->curr_mac_addr)) {
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/* Get the MAC address from the eeprom for later reference */
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ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
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pr_debug("Keeping Permanent MAC Addr = %pM\n",
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hw->curr_mac_addr);
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} else {
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/* Setup the receive address. */
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pr_debug("Overriding MAC Address in RAR[0]\n");
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pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
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ixgb_rar_set(hw, hw->curr_mac_addr, 0);
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}
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/* Zero out the other 15 receive addresses. */
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pr_debug("Clearing RAR[1-15]\n");
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for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
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/* Write high reg first to disable the AV bit first */
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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}
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}
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/******************************************************************************
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* Updates the MAC's list of multicast addresses.
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*
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* hw - Struct containing variables accessed by shared code
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* mc_addr_list - the list of new multicast addresses
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* mc_addr_count - number of addresses
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* pad - number of bytes between addresses in the list
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*
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* The given list replaces any existing list. Clears the last 15 receive
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* address registers and the multicast table. Uses receive address registers
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* for the first 15 multicast addresses, and hashes the rest into the
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* multicast table.
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*****************************************************************************/
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void
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ixgb_mc_addr_list_update(struct ixgb_hw *hw,
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u8 *mc_addr_list,
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u32 mc_addr_count,
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u32 pad)
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{
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u32 hash_value;
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u32 i;
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u32 rar_used_count = 1; /* RAR[0] is used for our MAC address */
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u8 *mca;
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ENTER();
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/* Set the new number of MC addresses that we are being requested to use. */
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hw->num_mc_addrs = mc_addr_count;
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/* Clear RAR[1-15] */
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pr_debug("Clearing RAR[1-15]\n");
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for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
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IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
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IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
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}
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/* Clear the MTA */
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pr_debug("Clearing MTA\n");
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for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
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IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
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/* Add the new addresses */
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mca = mc_addr_list;
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for (i = 0; i < mc_addr_count; i++) {
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pr_debug("Adding the multicast addresses:\n");
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pr_debug("MC Addr #%d = %pM\n", i, mca);
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/* Place this multicast address in the RAR if there is room, *
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* else put it in the MTA
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*/
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if (rar_used_count < IXGB_RAR_ENTRIES) {
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ixgb_rar_set(hw, mca, rar_used_count);
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pr_debug("Added a multicast address to RAR[%d]\n", i);
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rar_used_count++;
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} else {
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hash_value = ixgb_hash_mc_addr(hw, mca);
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pr_debug("Hash value = 0x%03X\n", hash_value);
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ixgb_mta_set(hw, hash_value);
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}
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mca += ETH_ALEN + pad;
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}
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pr_debug("MC Update Complete\n");
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}
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/******************************************************************************
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* Hashes an address to determine its location in the multicast table
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*
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* hw - Struct containing variables accessed by shared code
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* mc_addr - the multicast address to hash
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*
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* Returns:
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* The hash value
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*****************************************************************************/
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static u32
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ixgb_hash_mc_addr(struct ixgb_hw *hw,
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u8 *mc_addr)
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{
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u32 hash_value = 0;
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ENTER();
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/* The portion of the address that is used for the hash table is
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* determined by the mc_filter_type setting.
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*/
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switch (hw->mc_filter_type) {
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/* [0] [1] [2] [3] [4] [5]
|
|
* 01 AA 00 12 34 56
|
|
* LSB MSB - According to H/W docs */
|
|
case 0:
|
|
/* [47:36] i.e. 0x563 for above example address */
|
|
hash_value =
|
|
((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
|
|
break;
|
|
case 1: /* [46:35] i.e. 0xAC6 for above example address */
|
|
hash_value =
|
|
((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
|
|
break;
|
|
case 2: /* [45:34] i.e. 0x5D8 for above example address */
|
|
hash_value =
|
|
((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
|
|
break;
|
|
case 3: /* [43:32] i.e. 0x634 for above example address */
|
|
hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
|
|
break;
|
|
default:
|
|
/* Invalid mc_filter_type, what should we do? */
|
|
pr_debug("MC filter type param set incorrectly\n");
|
|
ASSERT(0);
|
|
break;
|
|
}
|
|
|
|
hash_value &= 0xFFF;
|
|
return hash_value;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Sets the bit in the multicast table corresponding to the hash value.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
* hash_value - Multicast address hash value
|
|
*****************************************************************************/
|
|
static void
|
|
ixgb_mta_set(struct ixgb_hw *hw,
|
|
u32 hash_value)
|
|
{
|
|
u32 hash_bit, hash_reg;
|
|
u32 mta_reg;
|
|
|
|
/* The MTA is a register array of 128 32-bit registers.
|
|
* It is treated like an array of 4096 bits. We want to set
|
|
* bit BitArray[hash_value]. So we figure out what register
|
|
* the bit is in, read it, OR in the new bit, then write
|
|
* back the new value. The register is determined by the
|
|
* upper 7 bits of the hash value and the bit within that
|
|
* register are determined by the lower 5 bits of the value.
|
|
*/
|
|
hash_reg = (hash_value >> 5) & 0x7F;
|
|
hash_bit = hash_value & 0x1F;
|
|
|
|
mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
|
|
|
|
mta_reg |= (1 << hash_bit);
|
|
|
|
IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Puts an ethernet address into a receive address register.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
* addr - Address to put into receive address register
|
|
* index - Receive address register to write
|
|
*****************************************************************************/
|
|
void
|
|
ixgb_rar_set(struct ixgb_hw *hw,
|
|
u8 *addr,
|
|
u32 index)
|
|
{
|
|
u32 rar_low, rar_high;
|
|
|
|
ENTER();
|
|
|
|
/* HW expects these in little endian so we reverse the byte order
|
|
* from network order (big endian) to little endian
|
|
*/
|
|
rar_low = ((u32) addr[0] |
|
|
((u32)addr[1] << 8) |
|
|
((u32)addr[2] << 16) |
|
|
((u32)addr[3] << 24));
|
|
|
|
rar_high = ((u32) addr[4] |
|
|
((u32)addr[5] << 8) |
|
|
IXGB_RAH_AV);
|
|
|
|
IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
|
|
IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Writes a value to the specified offset in the VLAN filter table.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
* offset - Offset in VLAN filer table to write
|
|
* value - Value to write into VLAN filter table
|
|
*****************************************************************************/
|
|
void
|
|
ixgb_write_vfta(struct ixgb_hw *hw,
|
|
u32 offset,
|
|
u32 value)
|
|
{
|
|
IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Clears the VLAN filer table
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
static void
|
|
ixgb_clear_vfta(struct ixgb_hw *hw)
|
|
{
|
|
u32 offset;
|
|
|
|
for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
|
|
IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Configures the flow control settings based on SW configuration.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
|
|
static bool
|
|
ixgb_setup_fc(struct ixgb_hw *hw)
|
|
{
|
|
u32 ctrl_reg;
|
|
u32 pap_reg = 0; /* by default, assume no pause time */
|
|
bool status = true;
|
|
|
|
ENTER();
|
|
|
|
/* Get the current control reg 0 settings */
|
|
ctrl_reg = IXGB_READ_REG(hw, CTRL0);
|
|
|
|
/* Clear the Receive Pause Enable and Transmit Pause Enable bits */
|
|
ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
|
|
|
|
/* The possible values of the "flow_control" parameter are:
|
|
* 0: Flow control is completely disabled
|
|
* 1: Rx flow control is enabled (we can receive pause frames
|
|
* but not send pause frames).
|
|
* 2: Tx flow control is enabled (we can send pause frames
|
|
* but we do not support receiving pause frames).
|
|
* 3: Both Rx and TX flow control (symmetric) are enabled.
|
|
* other: Invalid.
|
|
*/
|
|
switch (hw->fc.type) {
|
|
case ixgb_fc_none: /* 0 */
|
|
/* Set CMDC bit to disable Rx Flow control */
|
|
ctrl_reg |= (IXGB_CTRL0_CMDC);
|
|
break;
|
|
case ixgb_fc_rx_pause: /* 1 */
|
|
/* RX Flow control is enabled, and TX Flow control is
|
|
* disabled.
|
|
*/
|
|
ctrl_reg |= (IXGB_CTRL0_RPE);
|
|
break;
|
|
case ixgb_fc_tx_pause: /* 2 */
|
|
/* TX Flow control is enabled, and RX Flow control is
|
|
* disabled, by a software over-ride.
|
|
*/
|
|
ctrl_reg |= (IXGB_CTRL0_TPE);
|
|
pap_reg = hw->fc.pause_time;
|
|
break;
|
|
case ixgb_fc_full: /* 3 */
|
|
/* Flow control (both RX and TX) is enabled by a software
|
|
* over-ride.
|
|
*/
|
|
ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
|
|
pap_reg = hw->fc.pause_time;
|
|
break;
|
|
default:
|
|
/* We should never get here. The value should be 0-3. */
|
|
pr_debug("Flow control param set incorrectly\n");
|
|
ASSERT(0);
|
|
break;
|
|
}
|
|
|
|
/* Write the new settings */
|
|
IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
|
|
|
|
if (pap_reg != 0)
|
|
IXGB_WRITE_REG(hw, PAP, pap_reg);
|
|
|
|
/* Set the flow control receive threshold registers. Normally,
|
|
* these registers will be set to a default threshold that may be
|
|
* adjusted later by the driver's runtime code. However, if the
|
|
* ability to transmit pause frames in not enabled, then these
|
|
* registers will be set to 0.
|
|
*/
|
|
if (!(hw->fc.type & ixgb_fc_tx_pause)) {
|
|
IXGB_WRITE_REG(hw, FCRTL, 0);
|
|
IXGB_WRITE_REG(hw, FCRTH, 0);
|
|
} else {
|
|
/* We need to set up the Receive Threshold high and low water
|
|
* marks as well as (optionally) enabling the transmission of XON
|
|
* frames. */
|
|
if (hw->fc.send_xon) {
|
|
IXGB_WRITE_REG(hw, FCRTL,
|
|
(hw->fc.low_water | IXGB_FCRTL_XONE));
|
|
} else {
|
|
IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
|
|
}
|
|
IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
|
|
}
|
|
return status;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Reads a word from a device over the Management Data Interface (MDI) bus.
|
|
* This interface is used to manage Physical layer devices.
|
|
*
|
|
* hw - Struct containing variables accessed by hw code
|
|
* reg_address - Offset of device register being read.
|
|
* phy_address - Address of device on MDI.
|
|
*
|
|
* Returns: Data word (16 bits) from MDI device.
|
|
*
|
|
* The 82597EX has support for several MDI access methods. This routine
|
|
* uses the new protocol MDI Single Command and Address Operation.
|
|
* This requires that first an address cycle command is sent, followed by a
|
|
* read command.
|
|
*****************************************************************************/
|
|
static u16
|
|
ixgb_read_phy_reg(struct ixgb_hw *hw,
|
|
u32 reg_address,
|
|
u32 phy_address,
|
|
u32 device_type)
|
|
{
|
|
u32 i;
|
|
u32 data;
|
|
u32 command = 0;
|
|
|
|
ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
|
|
ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
|
|
ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
|
|
|
|
/* Setup and write the address cycle command */
|
|
command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
|
|
(device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
|
|
(phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
|
|
(IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
|
|
|
|
IXGB_WRITE_REG(hw, MSCA, command);
|
|
|
|
/**************************************************************
|
|
** Check every 10 usec to see if the address cycle completed
|
|
** The COMMAND bit will clear when the operation is complete.
|
|
** This may take as long as 64 usecs (we'll wait 100 usecs max)
|
|
** from the CPU Write to the Ready bit assertion.
|
|
**************************************************************/
|
|
|
|
for (i = 0; i < 10; i++)
|
|
{
|
|
udelay(10);
|
|
|
|
command = IXGB_READ_REG(hw, MSCA);
|
|
|
|
if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
|
|
break;
|
|
}
|
|
|
|
ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
|
|
|
|
/* Address cycle complete, setup and write the read command */
|
|
command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
|
|
(device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
|
|
(phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
|
|
(IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
|
|
|
|
IXGB_WRITE_REG(hw, MSCA, command);
|
|
|
|
/**************************************************************
|
|
** Check every 10 usec to see if the read command completed
|
|
** The COMMAND bit will clear when the operation is complete.
|
|
** The read may take as long as 64 usecs (we'll wait 100 usecs max)
|
|
** from the CPU Write to the Ready bit assertion.
|
|
**************************************************************/
|
|
|
|
for (i = 0; i < 10; i++)
|
|
{
|
|
udelay(10);
|
|
|
|
command = IXGB_READ_REG(hw, MSCA);
|
|
|
|
if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
|
|
break;
|
|
}
|
|
|
|
ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
|
|
|
|
/* Operation is complete, get the data from the MDIO Read/Write Data
|
|
* register and return.
|
|
*/
|
|
data = IXGB_READ_REG(hw, MSRWD);
|
|
data >>= IXGB_MSRWD_READ_DATA_SHIFT;
|
|
return((u16) data);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Writes a word to a device over the Management Data Interface (MDI) bus.
|
|
* This interface is used to manage Physical layer devices.
|
|
*
|
|
* hw - Struct containing variables accessed by hw code
|
|
* reg_address - Offset of device register being read.
|
|
* phy_address - Address of device on MDI.
|
|
* device_type - Also known as the Device ID or DID.
|
|
* data - 16-bit value to be written
|
|
*
|
|
* Returns: void.
|
|
*
|
|
* The 82597EX has support for several MDI access methods. This routine
|
|
* uses the new protocol MDI Single Command and Address Operation.
|
|
* This requires that first an address cycle command is sent, followed by a
|
|
* write command.
|
|
*****************************************************************************/
|
|
static void
|
|
ixgb_write_phy_reg(struct ixgb_hw *hw,
|
|
u32 reg_address,
|
|
u32 phy_address,
|
|
u32 device_type,
|
|
u16 data)
|
|
{
|
|
u32 i;
|
|
u32 command = 0;
|
|
|
|
ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
|
|
ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
|
|
ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
|
|
|
|
/* Put the data in the MDIO Read/Write Data register */
|
|
IXGB_WRITE_REG(hw, MSRWD, (u32)data);
|
|
|
|
/* Setup and write the address cycle command */
|
|
command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
|
|
(device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
|
|
(phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
|
|
(IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
|
|
|
|
IXGB_WRITE_REG(hw, MSCA, command);
|
|
|
|
/**************************************************************
|
|
** Check every 10 usec to see if the address cycle completed
|
|
** The COMMAND bit will clear when the operation is complete.
|
|
** This may take as long as 64 usecs (we'll wait 100 usecs max)
|
|
** from the CPU Write to the Ready bit assertion.
|
|
**************************************************************/
|
|
|
|
for (i = 0; i < 10; i++)
|
|
{
|
|
udelay(10);
|
|
|
|
command = IXGB_READ_REG(hw, MSCA);
|
|
|
|
if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
|
|
break;
|
|
}
|
|
|
|
ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
|
|
|
|
/* Address cycle complete, setup and write the write command */
|
|
command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
|
|
(device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
|
|
(phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
|
|
(IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
|
|
|
|
IXGB_WRITE_REG(hw, MSCA, command);
|
|
|
|
/**************************************************************
|
|
** Check every 10 usec to see if the read command completed
|
|
** The COMMAND bit will clear when the operation is complete.
|
|
** The write may take as long as 64 usecs (we'll wait 100 usecs max)
|
|
** from the CPU Write to the Ready bit assertion.
|
|
**************************************************************/
|
|
|
|
for (i = 0; i < 10; i++)
|
|
{
|
|
udelay(10);
|
|
|
|
command = IXGB_READ_REG(hw, MSCA);
|
|
|
|
if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
|
|
break;
|
|
}
|
|
|
|
ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
|
|
|
|
/* Operation is complete, return. */
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Checks to see if the link status of the hardware has changed.
|
|
*
|
|
* hw - Struct containing variables accessed by hw code
|
|
*
|
|
* Called by any function that needs to check the link status of the adapter.
|
|
*****************************************************************************/
|
|
void
|
|
ixgb_check_for_link(struct ixgb_hw *hw)
|
|
{
|
|
u32 status_reg;
|
|
u32 xpcss_reg;
|
|
|
|
ENTER();
|
|
|
|
xpcss_reg = IXGB_READ_REG(hw, XPCSS);
|
|
status_reg = IXGB_READ_REG(hw, STATUS);
|
|
|
|
if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
|
|
(status_reg & IXGB_STATUS_LU)) {
|
|
hw->link_up = true;
|
|
} else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
|
|
(status_reg & IXGB_STATUS_LU)) {
|
|
pr_debug("XPCSS Not Aligned while Status:LU is set\n");
|
|
hw->link_up = ixgb_link_reset(hw);
|
|
} else {
|
|
/*
|
|
* 82597EX errata. Since the lane deskew problem may prevent
|
|
* link, reset the link before reporting link down.
|
|
*/
|
|
hw->link_up = ixgb_link_reset(hw);
|
|
}
|
|
/* Anything else for 10 Gig?? */
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Check for a bad link condition that may have occurred.
|
|
* The indication is that the RFC / LFC registers may be incrementing
|
|
* continually. A full adapter reset is required to recover.
|
|
*
|
|
* hw - Struct containing variables accessed by hw code
|
|
*
|
|
* Called by any function that needs to check the link status of the adapter.
|
|
*****************************************************************************/
|
|
bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
|
|
{
|
|
u32 newLFC, newRFC;
|
|
bool bad_link_returncode = false;
|
|
|
|
if (hw->phy_type == ixgb_phy_type_txn17401) {
|
|
newLFC = IXGB_READ_REG(hw, LFC);
|
|
newRFC = IXGB_READ_REG(hw, RFC);
|
|
if ((hw->lastLFC + 250 < newLFC)
|
|
|| (hw->lastRFC + 250 < newRFC)) {
|
|
pr_debug("BAD LINK! too many LFC/RFC since last check\n");
|
|
bad_link_returncode = true;
|
|
}
|
|
hw->lastLFC = newLFC;
|
|
hw->lastRFC = newRFC;
|
|
}
|
|
|
|
return bad_link_returncode;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Clears all hardware statistics counters.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
static void
|
|
ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
|
|
{
|
|
volatile u32 temp_reg;
|
|
|
|
ENTER();
|
|
|
|
/* if we are stopped or resetting exit gracefully */
|
|
if (hw->adapter_stopped) {
|
|
pr_debug("Exiting because the adapter is stopped!!!\n");
|
|
return;
|
|
}
|
|
|
|
temp_reg = IXGB_READ_REG(hw, TPRL);
|
|
temp_reg = IXGB_READ_REG(hw, TPRH);
|
|
temp_reg = IXGB_READ_REG(hw, GPRCL);
|
|
temp_reg = IXGB_READ_REG(hw, GPRCH);
|
|
temp_reg = IXGB_READ_REG(hw, BPRCL);
|
|
temp_reg = IXGB_READ_REG(hw, BPRCH);
|
|
temp_reg = IXGB_READ_REG(hw, MPRCL);
|
|
temp_reg = IXGB_READ_REG(hw, MPRCH);
|
|
temp_reg = IXGB_READ_REG(hw, UPRCL);
|
|
temp_reg = IXGB_READ_REG(hw, UPRCH);
|
|
temp_reg = IXGB_READ_REG(hw, VPRCL);
|
|
temp_reg = IXGB_READ_REG(hw, VPRCH);
|
|
temp_reg = IXGB_READ_REG(hw, JPRCL);
|
|
temp_reg = IXGB_READ_REG(hw, JPRCH);
|
|
temp_reg = IXGB_READ_REG(hw, GORCL);
|
|
temp_reg = IXGB_READ_REG(hw, GORCH);
|
|
temp_reg = IXGB_READ_REG(hw, TORL);
|
|
temp_reg = IXGB_READ_REG(hw, TORH);
|
|
temp_reg = IXGB_READ_REG(hw, RNBC);
|
|
temp_reg = IXGB_READ_REG(hw, RUC);
|
|
temp_reg = IXGB_READ_REG(hw, ROC);
|
|
temp_reg = IXGB_READ_REG(hw, RLEC);
|
|
temp_reg = IXGB_READ_REG(hw, CRCERRS);
|
|
temp_reg = IXGB_READ_REG(hw, ICBC);
|
|
temp_reg = IXGB_READ_REG(hw, ECBC);
|
|
temp_reg = IXGB_READ_REG(hw, MPC);
|
|
temp_reg = IXGB_READ_REG(hw, TPTL);
|
|
temp_reg = IXGB_READ_REG(hw, TPTH);
|
|
temp_reg = IXGB_READ_REG(hw, GPTCL);
|
|
temp_reg = IXGB_READ_REG(hw, GPTCH);
|
|
temp_reg = IXGB_READ_REG(hw, BPTCL);
|
|
temp_reg = IXGB_READ_REG(hw, BPTCH);
|
|
temp_reg = IXGB_READ_REG(hw, MPTCL);
|
|
temp_reg = IXGB_READ_REG(hw, MPTCH);
|
|
temp_reg = IXGB_READ_REG(hw, UPTCL);
|
|
temp_reg = IXGB_READ_REG(hw, UPTCH);
|
|
temp_reg = IXGB_READ_REG(hw, VPTCL);
|
|
temp_reg = IXGB_READ_REG(hw, VPTCH);
|
|
temp_reg = IXGB_READ_REG(hw, JPTCL);
|
|
temp_reg = IXGB_READ_REG(hw, JPTCH);
|
|
temp_reg = IXGB_READ_REG(hw, GOTCL);
|
|
temp_reg = IXGB_READ_REG(hw, GOTCH);
|
|
temp_reg = IXGB_READ_REG(hw, TOTL);
|
|
temp_reg = IXGB_READ_REG(hw, TOTH);
|
|
temp_reg = IXGB_READ_REG(hw, DC);
|
|
temp_reg = IXGB_READ_REG(hw, PLT64C);
|
|
temp_reg = IXGB_READ_REG(hw, TSCTC);
|
|
temp_reg = IXGB_READ_REG(hw, TSCTFC);
|
|
temp_reg = IXGB_READ_REG(hw, IBIC);
|
|
temp_reg = IXGB_READ_REG(hw, RFC);
|
|
temp_reg = IXGB_READ_REG(hw, LFC);
|
|
temp_reg = IXGB_READ_REG(hw, PFRC);
|
|
temp_reg = IXGB_READ_REG(hw, PFTC);
|
|
temp_reg = IXGB_READ_REG(hw, MCFRC);
|
|
temp_reg = IXGB_READ_REG(hw, MCFTC);
|
|
temp_reg = IXGB_READ_REG(hw, XONRXC);
|
|
temp_reg = IXGB_READ_REG(hw, XONTXC);
|
|
temp_reg = IXGB_READ_REG(hw, XOFFRXC);
|
|
temp_reg = IXGB_READ_REG(hw, XOFFTXC);
|
|
temp_reg = IXGB_READ_REG(hw, RJC);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Turns on the software controllable LED
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
void
|
|
ixgb_led_on(struct ixgb_hw *hw)
|
|
{
|
|
u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
|
|
|
|
/* To turn on the LED, clear software-definable pin 0 (SDP0). */
|
|
ctrl0_reg &= ~IXGB_CTRL0_SDP0;
|
|
IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Turns off the software controllable LED
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
void
|
|
ixgb_led_off(struct ixgb_hw *hw)
|
|
{
|
|
u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
|
|
|
|
/* To turn off the LED, set software-definable pin 0 (SDP0). */
|
|
ctrl0_reg |= IXGB_CTRL0_SDP0;
|
|
IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Gets the current PCI bus type, speed, and width of the hardware
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
static void
|
|
ixgb_get_bus_info(struct ixgb_hw *hw)
|
|
{
|
|
u32 status_reg;
|
|
|
|
status_reg = IXGB_READ_REG(hw, STATUS);
|
|
|
|
hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
|
|
ixgb_bus_type_pcix : ixgb_bus_type_pci;
|
|
|
|
if (hw->bus.type == ixgb_bus_type_pci) {
|
|
hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
|
|
ixgb_bus_speed_66 : ixgb_bus_speed_33;
|
|
} else {
|
|
switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
|
|
case IXGB_STATUS_PCIX_SPD_66:
|
|
hw->bus.speed = ixgb_bus_speed_66;
|
|
break;
|
|
case IXGB_STATUS_PCIX_SPD_100:
|
|
hw->bus.speed = ixgb_bus_speed_100;
|
|
break;
|
|
case IXGB_STATUS_PCIX_SPD_133:
|
|
hw->bus.speed = ixgb_bus_speed_133;
|
|
break;
|
|
default:
|
|
hw->bus.speed = ixgb_bus_speed_reserved;
|
|
break;
|
|
}
|
|
}
|
|
|
|
hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
|
|
ixgb_bus_width_64 : ixgb_bus_width_32;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Tests a MAC address to ensure it is a valid Individual Address
|
|
*
|
|
* mac_addr - pointer to MAC address.
|
|
*
|
|
*****************************************************************************/
|
|
static bool
|
|
mac_addr_valid(u8 *mac_addr)
|
|
{
|
|
bool is_valid = true;
|
|
ENTER();
|
|
|
|
/* Make sure it is not a multicast address */
|
|
if (is_multicast_ether_addr(mac_addr)) {
|
|
pr_debug("MAC address is multicast\n");
|
|
is_valid = false;
|
|
}
|
|
/* Not a broadcast address */
|
|
else if (is_broadcast_ether_addr(mac_addr)) {
|
|
pr_debug("MAC address is broadcast\n");
|
|
is_valid = false;
|
|
}
|
|
/* Reject the zero address */
|
|
else if (is_zero_ether_addr(mac_addr)) {
|
|
pr_debug("MAC address is all zeros\n");
|
|
is_valid = false;
|
|
}
|
|
return is_valid;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Resets the 10GbE link. Waits the settle time and returns the state of
|
|
* the link.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
static bool
|
|
ixgb_link_reset(struct ixgb_hw *hw)
|
|
{
|
|
bool link_status = false;
|
|
u8 wait_retries = MAX_RESET_ITERATIONS;
|
|
u8 lrst_retries = MAX_RESET_ITERATIONS;
|
|
|
|
do {
|
|
/* Reset the link */
|
|
IXGB_WRITE_REG(hw, CTRL0,
|
|
IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
|
|
|
|
/* Wait for link-up and lane re-alignment */
|
|
do {
|
|
udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
|
|
link_status =
|
|
((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
|
|
&& (IXGB_READ_REG(hw, XPCSS) &
|
|
IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
|
|
} while (!link_status && --wait_retries);
|
|
|
|
} while (!link_status && --lrst_retries);
|
|
|
|
return link_status;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Resets the 10GbE optics module.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
static void
|
|
ixgb_optics_reset(struct ixgb_hw *hw)
|
|
{
|
|
if (hw->phy_type == ixgb_phy_type_txn17401) {
|
|
u16 mdio_reg;
|
|
|
|
ixgb_write_phy_reg(hw,
|
|
MDIO_CTRL1,
|
|
IXGB_PHY_ADDRESS,
|
|
MDIO_MMD_PMAPMD,
|
|
MDIO_CTRL1_RESET);
|
|
|
|
mdio_reg = ixgb_read_phy_reg(hw,
|
|
MDIO_CTRL1,
|
|
IXGB_PHY_ADDRESS,
|
|
MDIO_MMD_PMAPMD);
|
|
}
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Resets the 10GbE optics module for Sun variant NIC.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
*****************************************************************************/
|
|
|
|
#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG 0xC803
|
|
#define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL 0x0164
|
|
#define IXGB_BCM8704_USER_CTRL_REG 0xC800
|
|
#define IXGB_BCM8704_USER_CTRL_REG_VAL 0x7FBF
|
|
#define IXGB_BCM8704_USER_DEV3_ADDR 0x0003
|
|
#define IXGB_SUN_PHY_ADDRESS 0x0000
|
|
#define IXGB_SUN_PHY_RESET_DELAY 305
|
|
|
|
static void
|
|
ixgb_optics_reset_bcm(struct ixgb_hw *hw)
|
|
{
|
|
u32 ctrl = IXGB_READ_REG(hw, CTRL0);
|
|
ctrl &= ~IXGB_CTRL0_SDP2;
|
|
ctrl |= IXGB_CTRL0_SDP3;
|
|
IXGB_WRITE_REG(hw, CTRL0, ctrl);
|
|
IXGB_WRITE_FLUSH(hw);
|
|
|
|
/* SerDes needs extra delay */
|
|
msleep(IXGB_SUN_PHY_RESET_DELAY);
|
|
|
|
/* Broadcom 7408L configuration */
|
|
/* Reference clock config */
|
|
ixgb_write_phy_reg(hw,
|
|
IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
|
|
IXGB_SUN_PHY_ADDRESS,
|
|
IXGB_BCM8704_USER_DEV3_ADDR,
|
|
IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
|
|
/* we must read the registers twice */
|
|
ixgb_read_phy_reg(hw,
|
|
IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
|
|
IXGB_SUN_PHY_ADDRESS,
|
|
IXGB_BCM8704_USER_DEV3_ADDR);
|
|
ixgb_read_phy_reg(hw,
|
|
IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
|
|
IXGB_SUN_PHY_ADDRESS,
|
|
IXGB_BCM8704_USER_DEV3_ADDR);
|
|
|
|
ixgb_write_phy_reg(hw,
|
|
IXGB_BCM8704_USER_CTRL_REG,
|
|
IXGB_SUN_PHY_ADDRESS,
|
|
IXGB_BCM8704_USER_DEV3_ADDR,
|
|
IXGB_BCM8704_USER_CTRL_REG_VAL);
|
|
ixgb_read_phy_reg(hw,
|
|
IXGB_BCM8704_USER_CTRL_REG,
|
|
IXGB_SUN_PHY_ADDRESS,
|
|
IXGB_BCM8704_USER_DEV3_ADDR);
|
|
ixgb_read_phy_reg(hw,
|
|
IXGB_BCM8704_USER_CTRL_REG,
|
|
IXGB_SUN_PHY_ADDRESS,
|
|
IXGB_BCM8704_USER_DEV3_ADDR);
|
|
|
|
/* SerDes needs extra delay */
|
|
msleep(IXGB_SUN_PHY_RESET_DELAY);
|
|
}
|