760 lines
20 KiB
C
760 lines
20 KiB
C
/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Authors: Iyappan Subramanian <isubramanian@apm.com>
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* Ravi Patel <rapatel@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "xgene_enet_main.h"
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#include "xgene_enet_hw.h"
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static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
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{
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u32 *ring_cfg = ring->state;
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u64 addr = ring->dma;
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enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;
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ring_cfg[4] |= (1 << SELTHRSH_POS) &
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CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN);
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ring_cfg[3] |= ACCEPTLERR;
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ring_cfg[2] |= QCOHERENT;
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addr >>= 8;
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ring_cfg[2] |= (addr << RINGADDRL_POS) &
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CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN);
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addr >>= RINGADDRL_LEN;
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ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN);
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ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) &
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CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN);
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}
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static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
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{
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u32 *ring_cfg = ring->state;
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bool is_bufpool;
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u32 val;
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is_bufpool = xgene_enet_is_bufpool(ring->id);
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val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR;
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ring_cfg[4] |= (val << RINGTYPE_POS) &
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CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN);
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if (is_bufpool) {
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ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) &
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CREATE_MASK(RINGMODE_POS, RINGMODE_LEN);
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}
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}
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static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
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{
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u32 *ring_cfg = ring->state;
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ring_cfg[3] |= RECOMBBUF;
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ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) &
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CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN);
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ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN);
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}
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static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
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u32 offset, u32 data)
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
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iowrite32(data, pdata->ring_csr_addr + offset);
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}
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static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,
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u32 offset, u32 *data)
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
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*data = ioread32(pdata->ring_csr_addr + offset);
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}
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static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
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{
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int i;
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xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
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for (i = 0; i < NUM_RING_CONFIG; i++) {
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xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
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ring->state[i]);
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}
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}
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static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
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{
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memset(ring->state, 0, sizeof(u32) * NUM_RING_CONFIG);
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xgene_enet_write_ring_state(ring);
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}
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static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
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{
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xgene_enet_ring_set_type(ring);
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if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0)
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xgene_enet_ring_set_recombbuf(ring);
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xgene_enet_ring_init(ring);
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xgene_enet_write_ring_state(ring);
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}
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static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
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{
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u32 ring_id_val, ring_id_buf;
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bool is_bufpool;
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is_bufpool = xgene_enet_is_bufpool(ring->id);
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ring_id_val = ring->id & GENMASK(9, 0);
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ring_id_val |= OVERWRITE;
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ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
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ring_id_buf |= PREFETCH_BUF_EN;
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if (is_bufpool)
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ring_id_buf |= IS_BUFFER_POOL;
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xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
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xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
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}
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static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
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{
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u32 ring_id;
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ring_id = ring->id | OVERWRITE;
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xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
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xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
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}
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struct xgene_enet_desc_ring *xgene_enet_setup_ring(
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struct xgene_enet_desc_ring *ring)
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{
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u32 size = ring->size;
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u32 i, data;
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bool is_bufpool;
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xgene_enet_clr_ring_state(ring);
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xgene_enet_set_ring_state(ring);
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xgene_enet_set_ring_id(ring);
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ring->slots = xgene_enet_get_numslots(ring->id, size);
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is_bufpool = xgene_enet_is_bufpool(ring->id);
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if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
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return ring;
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for (i = 0; i < ring->slots; i++)
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xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
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xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
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data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));
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xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
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return ring;
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}
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void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
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{
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u32 data;
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bool is_bufpool;
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is_bufpool = xgene_enet_is_bufpool(ring->id);
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if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
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goto out;
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xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
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data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));
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xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
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out:
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xgene_enet_clr_desc_ring_id(ring);
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xgene_enet_clr_ring_state(ring);
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}
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void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
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struct xgene_enet_pdata *pdata,
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enum xgene_enet_err_code status)
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{
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struct rtnl_link_stats64 *stats = &pdata->stats;
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switch (status) {
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case INGRESS_CRC:
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stats->rx_crc_errors++;
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break;
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case INGRESS_CHECKSUM:
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case INGRESS_CHECKSUM_COMPUTE:
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stats->rx_errors++;
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break;
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case INGRESS_TRUNC_FRAME:
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stats->rx_frame_errors++;
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break;
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case INGRESS_PKT_LEN:
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stats->rx_length_errors++;
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break;
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case INGRESS_PKT_UNDER:
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stats->rx_frame_errors++;
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break;
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case INGRESS_FIFO_OVERRUN:
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stats->rx_fifo_errors++;
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break;
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default:
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break;
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}
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}
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static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 val)
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{
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void __iomem *addr = pdata->eth_csr_addr + offset;
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iowrite32(val, addr);
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}
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static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
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u32 offset, u32 val)
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{
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void __iomem *addr = pdata->eth_ring_if_addr + offset;
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iowrite32(val, addr);
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}
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static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 val)
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{
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void __iomem *addr = pdata->eth_diag_csr_addr + offset;
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iowrite32(val, addr);
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}
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static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 val)
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{
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void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
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iowrite32(val, addr);
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}
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static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
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void __iomem *cmd, void __iomem *cmd_done,
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u32 wr_addr, u32 wr_data)
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{
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u32 done;
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u8 wait = 10;
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iowrite32(wr_addr, addr);
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iowrite32(wr_data, wr);
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iowrite32(XGENE_ENET_WR_CMD, cmd);
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/* wait for write command to complete */
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while (!(done = ioread32(cmd_done)) && wait--)
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udelay(1);
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if (!done)
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return false;
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iowrite32(0, cmd);
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return true;
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}
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static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata *pdata,
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u32 wr_addr, u32 wr_data)
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{
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void __iomem *addr, *wr, *cmd, *cmd_done;
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addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
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wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
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cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
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cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
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if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
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netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
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wr_addr);
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}
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static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 *val)
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{
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void __iomem *addr = pdata->eth_csr_addr + offset;
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*val = ioread32(addr);
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}
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static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 *val)
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{
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void __iomem *addr = pdata->eth_diag_csr_addr + offset;
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*val = ioread32(addr);
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}
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static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata,
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u32 offset, u32 *val)
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{
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void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
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*val = ioread32(addr);
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}
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static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
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void __iomem *cmd, void __iomem *cmd_done,
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u32 rd_addr, u32 *rd_data)
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{
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u32 done;
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u8 wait = 10;
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iowrite32(rd_addr, addr);
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iowrite32(XGENE_ENET_RD_CMD, cmd);
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/* wait for read command to complete */
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while (!(done = ioread32(cmd_done)) && wait--)
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udelay(1);
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if (!done)
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return false;
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*rd_data = ioread32(rd);
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iowrite32(0, cmd);
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return true;
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}
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static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata *pdata,
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u32 rd_addr, u32 *rd_data)
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{
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void __iomem *addr, *rd, *cmd, *cmd_done;
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addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
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rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
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cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
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cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
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if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
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netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
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rd_addr);
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}
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static int xgene_mii_phy_write(struct xgene_enet_pdata *pdata, int phy_id,
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u32 reg, u16 data)
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{
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u32 addr = 0, wr_data = 0;
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u32 done;
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u8 wait = 10;
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PHY_ADDR_SET(&addr, phy_id);
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REG_ADDR_SET(&addr, reg);
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xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr);
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PHY_CONTROL_SET(&wr_data, data);
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xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONTROL_ADDR, wr_data);
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do {
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usleep_range(5, 10);
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xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done);
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} while ((done & BUSY_MASK) && wait--);
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if (done & BUSY_MASK) {
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netdev_err(pdata->ndev, "MII_MGMT write failed\n");
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return -EBUSY;
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}
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return 0;
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}
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static int xgene_mii_phy_read(struct xgene_enet_pdata *pdata,
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u8 phy_id, u32 reg)
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{
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u32 addr = 0;
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u32 data, done;
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u8 wait = 10;
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PHY_ADDR_SET(&addr, phy_id);
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REG_ADDR_SET(&addr, reg);
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xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr);
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xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
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do {
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usleep_range(5, 10);
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xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done);
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} while ((done & BUSY_MASK) && wait--);
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if (done & BUSY_MASK) {
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netdev_err(pdata->ndev, "MII_MGMT read failed\n");
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return -EBUSY;
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}
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xgene_enet_rd_mcx_mac(pdata, MII_MGMT_STATUS_ADDR, &data);
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xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, 0);
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return data;
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}
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static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata)
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{
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u32 addr0, addr1;
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u8 *dev_addr = pdata->ndev->dev_addr;
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addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
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(dev_addr[1] << 8) | dev_addr[0];
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addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
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xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0);
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xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1);
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}
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static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
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{
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struct net_device *ndev = pdata->ndev;
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u32 data;
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u8 wait = 10;
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xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
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do {
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usleep_range(100, 110);
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xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
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} while ((data != 0xffffffff) && wait--);
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if (data != 0xffffffff) {
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netdev_err(ndev, "Failed to release memory from shutdown\n");
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return -ENODEV;
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}
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return 0;
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}
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static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
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{
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xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1);
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xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0);
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}
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static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
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{
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u32 value, mc2;
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u32 intf_ctl, rgmii;
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u32 icm0, icm2;
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xgene_gmac_reset(pdata);
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xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0);
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xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2);
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xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_2_ADDR, &mc2);
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xgene_enet_rd_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, &intf_ctl);
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xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii);
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switch (pdata->phy_speed) {
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case SPEED_10:
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ENET_INTERFACE_MODE2_SET(&mc2, 1);
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CFG_MACMODE_SET(&icm0, 0);
|
|
CFG_WAITASYNCRD_SET(&icm2, 500);
|
|
rgmii &= ~CFG_SPEED_1250;
|
|
break;
|
|
case SPEED_100:
|
|
ENET_INTERFACE_MODE2_SET(&mc2, 1);
|
|
intf_ctl |= ENET_LHD_MODE;
|
|
CFG_MACMODE_SET(&icm0, 1);
|
|
CFG_WAITASYNCRD_SET(&icm2, 80);
|
|
rgmii &= ~CFG_SPEED_1250;
|
|
break;
|
|
default:
|
|
ENET_INTERFACE_MODE2_SET(&mc2, 2);
|
|
intf_ctl |= ENET_GHD_MODE;
|
|
CFG_TXCLK_MUXSEL0_SET(&rgmii, 4);
|
|
xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
|
|
value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
|
|
xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
|
|
break;
|
|
}
|
|
|
|
mc2 |= FULL_DUPLEX2;
|
|
xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2);
|
|
xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl);
|
|
|
|
xgene_gmac_set_mac_addr(pdata);
|
|
|
|
/* Adjust MDC clock frequency */
|
|
xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &value);
|
|
MGMT_CLOCK_SEL_SET(&value, 7);
|
|
xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, value);
|
|
|
|
/* Enable drop if bufpool not available */
|
|
xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value);
|
|
value |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
|
|
xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value);
|
|
|
|
/* Rtype should be copied from FP */
|
|
xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
|
|
xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
|
|
|
|
/* Rx-Tx traffic resume */
|
|
xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
|
|
|
|
xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0);
|
|
xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2);
|
|
|
|
xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value);
|
|
value &= ~TX_DV_GATE_EN0;
|
|
value &= ~RX_DV_GATE_EN0;
|
|
value |= RESUME_RX0;
|
|
xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value);
|
|
|
|
xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
|
|
}
|
|
|
|
static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
|
|
{
|
|
u32 val = 0xffffffff;
|
|
|
|
xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val);
|
|
xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val);
|
|
xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val);
|
|
xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val);
|
|
}
|
|
|
|
static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
|
|
u32 dst_ring_num, u16 bufpool_id)
|
|
{
|
|
u32 cb;
|
|
u32 fpsel;
|
|
|
|
fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
|
|
|
|
xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
|
|
cb |= CFG_CLE_BYPASS_EN0;
|
|
CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
|
|
xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
|
|
|
|
xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
|
|
CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
|
|
CFG_CLE_FPSEL0_SET(&cb, fpsel);
|
|
xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb);
|
|
}
|
|
|
|
static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata)
|
|
{
|
|
u32 data;
|
|
|
|
xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
|
|
xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN);
|
|
}
|
|
|
|
static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata)
|
|
{
|
|
u32 data;
|
|
|
|
xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
|
|
xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN);
|
|
}
|
|
|
|
static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata)
|
|
{
|
|
u32 data;
|
|
|
|
xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
|
|
xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN);
|
|
}
|
|
|
|
static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata)
|
|
{
|
|
u32 data;
|
|
|
|
xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
|
|
xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN);
|
|
}
|
|
|
|
bool xgene_ring_mgr_init(struct xgene_enet_pdata *p)
|
|
{
|
|
if (!ioread32(p->ring_csr_addr + CLKEN_ADDR))
|
|
return false;
|
|
|
|
if (ioread32(p->ring_csr_addr + SRST_ADDR))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
|
|
{
|
|
u32 val;
|
|
|
|
if (!xgene_ring_mgr_init(pdata))
|
|
return -ENODEV;
|
|
|
|
clk_prepare_enable(pdata->clk);
|
|
clk_disable_unprepare(pdata->clk);
|
|
clk_prepare_enable(pdata->clk);
|
|
xgene_enet_ecc_init(pdata);
|
|
xgene_enet_config_ring_if_assoc(pdata);
|
|
|
|
/* Enable auto-incr for scanning */
|
|
xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &val);
|
|
val |= SCAN_AUTO_INCR;
|
|
MGMT_CLOCK_SEL_SET(&val, 1);
|
|
xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata)
|
|
{
|
|
clk_disable_unprepare(pdata->clk);
|
|
}
|
|
|
|
static int xgene_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
|
|
{
|
|
struct xgene_enet_pdata *pdata = bus->priv;
|
|
u32 val;
|
|
|
|
val = xgene_mii_phy_read(pdata, mii_id, regnum);
|
|
netdev_dbg(pdata->ndev, "mdio_rd: bus=%d reg=%d val=%x\n",
|
|
mii_id, regnum, val);
|
|
|
|
return val;
|
|
}
|
|
|
|
static int xgene_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
|
|
u16 val)
|
|
{
|
|
struct xgene_enet_pdata *pdata = bus->priv;
|
|
|
|
netdev_dbg(pdata->ndev, "mdio_wr: bus=%d reg=%d val=%x\n",
|
|
mii_id, regnum, val);
|
|
return xgene_mii_phy_write(pdata, mii_id, regnum, val);
|
|
}
|
|
|
|
static void xgene_enet_adjust_link(struct net_device *ndev)
|
|
{
|
|
struct xgene_enet_pdata *pdata = netdev_priv(ndev);
|
|
struct phy_device *phydev = pdata->phy_dev;
|
|
|
|
if (phydev->link) {
|
|
if (pdata->phy_speed != phydev->speed) {
|
|
pdata->phy_speed = phydev->speed;
|
|
xgene_gmac_init(pdata);
|
|
xgene_gmac_rx_enable(pdata);
|
|
xgene_gmac_tx_enable(pdata);
|
|
phy_print_status(phydev);
|
|
}
|
|
} else {
|
|
xgene_gmac_rx_disable(pdata);
|
|
xgene_gmac_tx_disable(pdata);
|
|
pdata->phy_speed = SPEED_UNKNOWN;
|
|
phy_print_status(phydev);
|
|
}
|
|
}
|
|
|
|
static int xgene_enet_phy_connect(struct net_device *ndev)
|
|
{
|
|
struct xgene_enet_pdata *pdata = netdev_priv(ndev);
|
|
struct device_node *phy_np;
|
|
struct phy_device *phy_dev;
|
|
struct device *dev = &pdata->pdev->dev;
|
|
|
|
phy_np = of_parse_phandle(dev->of_node, "phy-handle", 0);
|
|
if (!phy_np) {
|
|
netdev_dbg(ndev, "No phy-handle found\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
phy_dev = of_phy_connect(ndev, phy_np, &xgene_enet_adjust_link,
|
|
0, pdata->phy_mode);
|
|
if (!phy_dev) {
|
|
netdev_err(ndev, "Could not connect to PHY\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
pdata->phy_speed = SPEED_UNKNOWN;
|
|
phy_dev->supported &= ~SUPPORTED_10baseT_Half &
|
|
~SUPPORTED_100baseT_Half &
|
|
~SUPPORTED_1000baseT_Half;
|
|
phy_dev->advertising = phy_dev->supported;
|
|
pdata->phy_dev = phy_dev;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
|
|
{
|
|
struct net_device *ndev = pdata->ndev;
|
|
struct device *dev = &pdata->pdev->dev;
|
|
struct device_node *child_np;
|
|
struct device_node *mdio_np = NULL;
|
|
struct mii_bus *mdio_bus;
|
|
int ret;
|
|
|
|
for_each_child_of_node(dev->of_node, child_np) {
|
|
if (of_device_is_compatible(child_np, "apm,xgene-mdio")) {
|
|
mdio_np = child_np;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!mdio_np) {
|
|
netdev_dbg(ndev, "No mdio node in the dts\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
mdio_bus = mdiobus_alloc();
|
|
if (!mdio_bus)
|
|
return -ENOMEM;
|
|
|
|
mdio_bus->name = "APM X-Gene MDIO bus";
|
|
mdio_bus->read = xgene_enet_mdio_read;
|
|
mdio_bus->write = xgene_enet_mdio_write;
|
|
snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii",
|
|
ndev->name);
|
|
|
|
mdio_bus->priv = pdata;
|
|
mdio_bus->parent = &ndev->dev;
|
|
|
|
ret = of_mdiobus_register(mdio_bus, mdio_np);
|
|
if (ret) {
|
|
netdev_err(ndev, "Failed to register MDIO bus\n");
|
|
mdiobus_free(mdio_bus);
|
|
return ret;
|
|
}
|
|
pdata->mdio_bus = mdio_bus;
|
|
|
|
ret = xgene_enet_phy_connect(ndev);
|
|
if (ret)
|
|
xgene_enet_mdio_remove(pdata);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata)
|
|
{
|
|
mdiobus_unregister(pdata->mdio_bus);
|
|
mdiobus_free(pdata->mdio_bus);
|
|
pdata->mdio_bus = NULL;
|
|
}
|
|
|
|
struct xgene_mac_ops xgene_gmac_ops = {
|
|
.init = xgene_gmac_init,
|
|
.reset = xgene_gmac_reset,
|
|
.rx_enable = xgene_gmac_rx_enable,
|
|
.tx_enable = xgene_gmac_tx_enable,
|
|
.rx_disable = xgene_gmac_rx_disable,
|
|
.tx_disable = xgene_gmac_tx_disable,
|
|
.set_mac_addr = xgene_gmac_set_mac_addr,
|
|
};
|
|
|
|
struct xgene_port_ops xgene_gport_ops = {
|
|
.reset = xgene_enet_reset,
|
|
.cle_bypass = xgene_enet_cle_bypass,
|
|
.shutdown = xgene_gport_shutdown,
|
|
};
|