178 lines
3.6 KiB
Plaintext
178 lines
3.6 KiB
Plaintext
config IRQCHIP
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def_bool y
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depends on OF_IRQ
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config ARM_GIC
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select MSM_SHOW_RESUME_IRQ
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config GIC_NON_BANKED
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bool
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config ARM_GIC_V3
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select IRQ_DOMAIN_HIERARCHY
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config ARM_GIC_PANIC_HANDLER
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bool "GIC Panic Handler"
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depends on ARM_GIC_V3 || ARM_GIC
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help
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Save GIC distributor registers to RAM buffer on kernel panic.
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gic-v3 will have an additional buffer for router registers.
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Mainly for debugging purposes.
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For production kernels, you should say 'N' here.
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config ARM_GIC_V3_ITS
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bool
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select PCI_MSI_IRQ_DOMAIN
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config ARM_GIC_V3_ACL
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bool "GICv3 Access control"
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depends on ARM_GIC_V3
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help
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Access to GIC ITS address space is controlled by EL2.
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Kernel has no permission to access ITS
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config ARM_GIC_V3_NO_ACCESS_CONTROL
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bool "GICv3 No Access Control Configuration"
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depends on ARM_GIC_V3
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help
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On some SOCs with the access control configurations it is
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not allowed to access certain set of the GIC registers
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from non-secure world. Provide a common flag to protect
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those functionalities and compile them out for such
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configurations, so that specific registers are not touched.
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For production kernels, you should say 'N' here.
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config ARM_NVIC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config ARM_VIC
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config ARM_VIC_NR
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int
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default 4 if ARCH_S5PV210
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default 2
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depends on ARM_VIC
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help
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The maximum number of VICs available in the system, for
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power management.
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config ATMEL_AIC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config ATMEL_AIC5_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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config BRCMSTB_L2_IRQ
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bool
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depends on ARM
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config MSM_SHOW_RESUME_IRQ
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bool "Enable logging of interrupts that could have caused resume"
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depends on ARM_GIC
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default n
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help
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This option logs wake up interrupts that have triggered just before
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the resume loop unrolls. It helps to debug to know any unnecessary
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wake up interrupts that causes system to come out of low power modes.
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Say Y if you want to debug why the system resumed.
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config DW_APB_ICTL
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bool
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select IRQ_DOMAIN
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config IMGPDC_IRQ
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config CLPS711X_IRQCHIP
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bool
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depends on ARCH_CLPS711X
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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default y
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config OR1K_PIC
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bool
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select IRQ_DOMAIN
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config OMAP_IRQCHIP
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bool
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select GENERIC_IRQ_CHIP
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select IRQ_DOMAIN
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config ORION_IRQCHIP
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bool
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select IRQ_DOMAIN
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select MULTI_IRQ_HANDLER
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config RENESAS_INTC_IRQPIN
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bool
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select IRQ_DOMAIN
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config RENESAS_IRQC
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bool
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select IRQ_DOMAIN
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config TB10X_IRQC
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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config XTENSA_MX
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bool
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select IRQ_DOMAIN
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config IRQ_CROSSBAR
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bool
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help
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Support for a CROSSBAR ip that precedes the main interrupt controller.
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The primary irqchip invokes the crossbar's callback which inturn allocates
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a free irq and configures the IP. Thus the peripheral interrupts are
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routed to one of the free irqchip interrupt lines.
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config KEYSTONE_IRQ
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tristate "Keystone 2 IRQ controller IP"
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depends on ARCH_KEYSTONE
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help
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Support for Texas Instruments Keystone 2 IRQ controller IP which
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is part of the Keystone 2 IPC mechanism
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config MSM_IRQ
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bool
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select IRQ_DOMAIN
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